* Re: [PATCH net-next v2 2/9] dt-bindings: net: lan9645x: add LAN9645X switch bindings
From: Jens Emil Schulz Ostergaard @ 2026-04-08 14:59 UTC (permalink / raw)
To: Rob Herring
Cc: UNGLinuxDriver, Andrew Lunn, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Simon Horman,
Krzysztof Kozlowski, Conor Dooley, Woojung Huh, Russell King,
Steen Hegelund, Daniel Machon, linux-kernel, netdev, devicetree
In-Reply-To: <20260407171854.GA2970003-robh@kernel.org>
On Tue, 2026-04-07 at 12:18 -0500, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Tue, Mar 24, 2026 at 11:46:45AM +0100, Jens Emil Schulz Østergaard wrote:
> > Add bindings for LAN9645X switch. We use a fallback compatible for the
> > smallest SKU microchip,lan96455s-switch.
> >
> > Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
> > Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
> > ---
> > Changes in v2:
> > - rename file to microchip,lan96455s-switch.yaml
> > - remove led vendor property
> > - add {rx,tx}-internal-delay-ps for rgmii delay
> > - remove labels from example
> > - remove container node from example
> > ---
> > .../net/dsa/microchip,lan96455s-switch.yaml | 119 +++++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 120 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
> > new file mode 100644
> > index 000000000000..0282e25c05d4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
> > @@ -0,0 +1,119 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/dsa/microchip,lan96455s-switch.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Microchip LAN9645x Ethernet switch
> > +
> > +maintainers:
> > + - Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
> > +
> > +description: |
>
> Don't need '|'
I will remove this.
>
> > + The LAN9645x switch is a multi-port Gigabit AVB/TSN Ethernet switch with
> > + five integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
> > + it supports up to 2 RGMII/RMII, up to 2 BASE-X/SERDES/2.5GBASE-X and one
> > + Quad-SGMII interfaces.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - microchip,lan96455s-switch
> > + - items:
> > + - enum:
> > + - microchip,lan96455f-switch
> > + - microchip,lan96457f-switch
> > + - microchip,lan96459f-switch
> > + - microchip,lan96457s-switch
> > + - microchip,lan96459s-switch
> > + - const: microchip,lan96455s-switch
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +$ref: dsa.yaml#
>
> Since you don't have any custom properties (just constraints), this ref
> should be "dsa.yaml#/$defs/ethernet-ports".
Right, I will update the ref.
>
> > +
> > +patternProperties:
> > + "^(ethernet-)?ports$":
>
> For a new binding, use the preferred name which is ethernet-ports. ports
> and port collide with the graph binding.
>
OK, I will use ethernet-ports and move it from patternProperties to properties.
> > + type: object
> > + additionalProperties: true
> > + patternProperties:
> > + "^(ethernet-)?port@[0-8]$":
>
> And 'ethernet-port'
I will change this and update the example.
>
> > + type: object
> > + description: Ethernet switch ports
> > +
> > + $ref: dsa-port.yaml#
> > +
> > + properties:
> > + rx-internal-delay-ps:
> > + const: 2000
> > +
> > + tx-internal-delay-ps:
> > + const: 2000
> > +
> > + unevaluatedProperties: false
>
> Place this after the $ref.
I will move this.
>
> > +
> > +oneOf:
> > + - required:
> > + - ports
> > + - required:
> > + - ethernet-ports
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + ethernet-switch@4000 {
> > + compatible = "microchip,lan96459f-switch", "microchip,lan96455s-switch";
> > + reg = <0x4000 0x244>;
> > +
> > + ethernet-ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + phy-mode = "gmii";
> > + phy-handle = <&cuphy0>;
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + phy-mode = "gmii";
> > + phy-handle = <&cuphy1>;
> > + };
> > +
> > + port@2 {
> > + reg = <2>;
> > + phy-mode = "gmii";
> > + phy-handle = <&cuphy2>;
> > + };
> > +
> > + port@3 {
> > + reg = <3>;
> > + phy-mode = "gmii";
> > + phy-handle = <&cuphy3>;
> > + };
> > +
> > + port@7 {
> > + reg = <7>;
> > + phy-mode = "rgmii";
> > + ethernet = <&cpu_host_port>;
> > + rx-internal-delay-ps = <2000>;
> > + tx-internal-delay-ps = <2000>;
> > +
> > + fixed-link {
> > + speed = <1000>;
> > + full-duplex;
> > + pause;
> > + };
> > + };
> > + };
> > + };
> > +...
> > +
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7ae698067c41..8232da1b3951 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -17278,6 +17278,7 @@ M: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
> > M: UNGLinuxDriver@microchip.com
> > L: netdev@vger.kernel.org
> > S: Maintained
> > +F: Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
> > F: include/linux/dsa/lan9645x.h
> > F: net/dsa/tag_lan9645x.c
> >
> >
> > --
> > 2.52.0
> >
^ permalink raw reply
* Re: [PATCH v6 10/21] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC
From: Laurent Pinchart @ 2026-04-08 15:00 UTC (permalink / raw)
To: Tommaso Merciai
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <87a18664-d19e-4434-8f92-1c7ce4f3a131@bp.renesas.com>
On Wed, Apr 08, 2026 at 04:44:48PM +0200, Tommaso Merciai wrote:
> On 4/8/26 16:16, Laurent Pinchart wrote:
> > On Wed, Apr 08, 2026 at 04:02:14PM +0200, Tommaso Merciai wrote:
> >> On 4/8/26 14:24, Laurent Pinchart wrote:
> >>> On Wed, Apr 08, 2026 at 12:36:55PM +0200, Tommaso Merciai wrote:
> >>>> The RZ/G3E SoC has 2 LCD controllers (LCDC), each containing a Frame
> >>>> Compression Processor (FCPVD), a Video Signal Processor (VSPD), and a
> >>>> Display Unit (DU).
> >>>>
> >>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >>>>
> >>>> Add a new SoC-specific compatible string 'renesas,r9a09g047-du'.
> >>>>
> >>>> Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" to
> >>>> allow up to four output ports, and explicitly disable port@2 and port@3
> >>>> for existing SoCs that do not expose them.
> >>>>
> >>>> Describe the four output ports of the RZ/G3E DU:
> >>>>
> >>>> - port@0: DSI (available on both LCDC instances)
> >>>> - port@1: DPAD / parallel RGB (LCDC1 only)
> >>>> - port@2: LVDS channel 0 (LCDC0 only)
> >>>> - port@3: LVDS channel 1 (available on both LCDC instances)
> >>>>
> >>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >>>> ---
> >>>> v5->v6:
> >>>> - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
> >>>> explicitly disable port@2 and port@3 for existing SoCs that do not expose
> >>>> them.
> >>>> - Reworked ports numbering + improved/fixed ports descriptions in the
> >>>> bindings documentation.
> >>>> - Improved commit body.
> >>>>
> >>>> v4->v5:
> >>>> - Dropped renesas,id property and updated bindings
> >>>> accordingly.
> >>>>
> >>>> v2->v3:
> >>>> - No changes.
> >>>>
> >>>> v2->v3:
> >>>> - No changes.
> >>>>
> >>>> v1->v2:
> >>>> - Use single compatible string instead of multiple compatible strings
> >>>> for the two DU instances, leveraging a 'renesas,id' property to
> >>>> differentiate between DU0 and DU1.
> >>>> - Updated commit message accordingly.
> >>>>
> >>>> .../bindings/display/renesas,rzg2l-du.yaml | 30 ++++++++++++++++++-
> >>>> 1 file changed, 29 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>> index 5add3b832eab..32da0b5ec88c 100644
> >>>> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>> @@ -20,6 +20,7 @@ properties:
> >>>> - enum:
> >>>> - renesas,r9a07g043u-du # RZ/G2UL
> >>>> - renesas,r9a07g044-du # RZ/G2{L,LC}
> >>>> + - renesas,r9a09g047-du # RZ/G3E
> >>>> - renesas,r9a09g057-du # RZ/V2H(P)
> >>>> - items:
> >>>> - enum:
> >>>> @@ -61,7 +62,7 @@ properties:
> >>>> model-dependent. Each port shall have a single endpoint.
> >>>>
> >>>> patternProperties:
> >>>> - "^port@[0-1]$":
> >>>> + "^port@[0-3]$":
> >>>> $ref: /schemas/graph.yaml#/properties/port
> >>>> unevaluatedProperties: false
> >>>>
> >>>> @@ -103,6 +104,8 @@ allOf:
> >>>> port@0:
> >>>> description: DPI
> >>>> port@1: false
> >>>> + port@2: false
> >>>> + port@3: false
> >>>>
> >>>> required:
> >>>> - port@0
> >>>> @@ -119,6 +122,8 @@ allOf:
> >>>> description: DSI
> >>>> port@1:
> >>>> description: DPI
> >>>> + port@2: false
> >>>> + port@3: false
> >>>>
> >>>> required:
> >>>> - port@0
> >>>> @@ -135,9 +140,32 @@ allOf:
> >>>> port@0:
> >>>> description: DSI
> >>>> port@1: false
> >>>> + port@2: false
> >>>> + port@3: false
> >>>>
> >>>> required:
> >>>> - port@0
> >>>> + - if:
> >>>> + properties:
> >>>> + compatible:
> >>>> + contains:
> >>>> + const: renesas,r9a09g047-du
> >>>> + then:
> >>>> + properties:
> >>>> + ports:
> >>>> + properties:
> >>>> + port@0:
> >>>> + description: DSI
> >>>> + port@1:
> >>>> + description: DPAD
> >>>> + port@2:
> >>>> + description: LVDS, Channel 0
> >>>> + port@3:
> >>>> + description: LVDS, Channel 1
> >>>> +
> >>>> + required:
> >>>> + - port@0
> >>>> + - port@3
> >>>
> >>> Why are ports 1 and 2 not required ?
> >>
> >> About this we had a similar discussion on v5[0]
> >> We are using the same compatible and:
> >>
> >> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >> |
> >> --> then has:
> >> port@0
> >> port@2
> >> port@3
> >>
> >>
> >> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >> |
> >> --> then has:
> >> port@0
> >> port@1
> >> port@3
> >
> > Ah yes, I forget there are two LCDC instances with different output
> > configurations.
> >
> > Something still looks a bit weird to me though. For LCDC1, which
> > supports a single LVDS channel, you use the port described as the second
> > LVDS channel. Is there a reason not to use port@2 ?
>
> 9.11 Low Voltage Differential Signaling (LVDS)
> 9.11.1.2 Block Diagram
> Figure 9.11-1 shows a block diagram of LVDS.
>
> LCDC1 is connected to LVDS, Channel 1
> For this reason I'm using port@3.
Re-reading that, I think I've misinterpreted the hardware architecture.
Doesn't the DU have a single output, that is connected the multiple
encoders (LVDS and DSI for LCDC0 and LVDS, DSI and DPI for LCDC1) ? It
seems modelling it with a single port and multiple endpoints would
better match the device.
For LVDS in particular, I see a single LVDS encoder with two channels,
so there should not be two LVDS output ports in the DU. The two ports
should be on the output of the LVDS device.
> >> Then port@1 is required for DU1 but not for DU0.
> >> Same port@2 is required for DU0 but not for DU1.
> >>
> >> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/ca022fdbba5236c36e0cb3095db4c31e8e0cb1b8.1770996493.git.tommaso.merciai.xr@bp.renesas.com/
> >>
> >>>>
> >>>> examples:
> >>>> # RZ/G2L DU
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v3 0/7] arm64: dts: ti: k3-am62a7-sk: Split r5f memory region
From: Rob Herring @ 2026-04-08 15:03 UTC (permalink / raw)
To: Markus Schneider-Pargmann (TI)
Cc: Bjorn Andersson, Mathieu Poirier, Krzysztof Kozlowski,
Conor Dooley, Suman Anna, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Vishal Mahaveer, Kevin Hilman, Dhruva Gole,
Sebin Francis, Kendall Willis, Akashdeep Kaur, linux-remoteproc,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20260318-topic-am62a-ioddr-dt-v6-19-v3-0-c41473cb23c3@baylibre.com>
On Wed, Mar 18, 2026 at 10:14 AM Markus Schneider-Pargmann (TI)
<msp@baylibre.com> wrote:
>
> Hi,
>
> Split the firmware memory region in more specific parts so it is better
> described where which information is stored. Specifically the LPM metadata
> region is important as bootloader software like U-Boot has to know where
> that data is to be able to read that data and resume from RAM.
>
> IO+DDR is a deep sleep state in which a few pins are set to be sensitive
> for wakeup while the DDR is kept in self refresh. Everything else is
> powered off.
>
> The changes in this series were suggested as part of the IO+DDR u-boot series:
> https://lore.kernel.org/r/814c211f-a9eb-4311-bb84-165b1a69755f@ti.com
>
> There are currently no real users of the memory-region that is split in
> this series. The size of the memory-region in total stays the same.
> The new layout is derived from the software running on the r5f
> processor:
> https://github.com/TexasInstruments/mcupsdk-core-k3/blob/k3_main/examples/drivers/ipc/ipc_rpmsg_echo_linux/am62ax-sk/r5fss0-0_freertos/ti-arm-clang/linker.cmd#L172
> https://github.com/TexasInstruments/mcupsdk-core-k3/blob/k3_main/source/drivers/device_manager/sciclient.h#L459
>
> Additionally the two important devicetree nodes for resuming from IO+DDR
> have the bootph-pre-ram flag added as this data needs to be read before
> the RAM is in use.
>
> Best
> Markus
>
> Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
> ---
> Changes in v3:
> - Squash the enforcement of the memory-region-names requirement in the
> patch adding the memory-region-names, as suggested.
> - Link to v2: https://lore.kernel.org/r/20260312-topic-am62a-ioddr-dt-v6-19-v2-0-37cb7ceec658@baylibre.com
>
> Changes in v2:
> - Make memory-region-names required if memory-region is present
> - Fixup memory-region and memory-region-names conditions. Require either
> 2 or 6 regions for memory-region and memory-region-names
> - Reword and restructure the binding documentation for memory-region and
> memory-region-names
> - Add memory-region-names to all uses of memory-region
> - Link to v1: https://lore.kernel.org/r/20260303-topic-am62a-ioddr-dt-v6-19-v1-0-12fe72bb40d2@baylibre.com
>
> ---
> Markus Schneider-Pargmann (TI) (7):
> dt-bindings: remoteproc: k3-r5f: Split up memory regions
> dt-bindings: remoteproc: k3-r5f: Add memory-region-names
> arm64: dts: ti: k3: Use memory-region-names for r5f
> arm64: dts: ti: k3-am62a7-sk: Split r5f memory region
> arm64: dts: ti: k3-am62p5-sk: Split r5f memory region
> arm64: dts: ti: k3-am62a7-sk: Add r5f nodes to pre-ram bootphase
> arm64: dts: ti: k3-am62p5-sk: Add r5f nodes to pre-ram bootphase
TI folks, Please make sure these dts patches are picked up for 7.1.
There's now a crap load of warnings in next with the binding change:
58 (ti,am62-r5fss): r5f@78000000: 'memory-region-names' is a
required property
30 (ti,am62-r5fss): r5f@79000000: 'memory-region-names' is a
required property
22 (ti,j721s2-r5fss): r5f@5f00000: 'memory-region-names' is a
required property
22 (ti,j721s2-r5fss): r5f@5e00000: 'memory-region-names' is a
required property
22 (ti,j721s2-r5fss): r5f@5d00000: 'memory-region-names' is a
required property
22 (ti,j721s2-r5fss): r5f@5c00000: 'memory-region-names' is a
required property
22 (ti,j721s2-r5fss): r5f@41400000: 'memory-region-names' is a
required property
22 (ti,j721s2-r5fss): r5f@41000000: 'memory-region-names' is a
required property
21 (ti,am64-r5fss): r5f@78600000: 'memory-region-names' is a
required property
21 (ti,am64-r5fss): r5f@78400000: 'memory-region-names' is a
required property
21 (ti,am64-r5fss): r5f@78200000: 'memory-region-names' is a
required property
21 (ti,am64-r5fss): r5f@78000000: 'memory-region-names' is a
required property
12 (ti,j721s2-r5fss): r5f@5a00000: 'memory-region-names' is a
required property
12 (ti,j721s2-r5fss): r5f@5900000: 'memory-region-names' is a
required property
12 (ti,am654-r5fss): r5f@41400000: 'memory-region-names' is a
required property
12 (ti,am654-r5fss): r5f@41000000: 'memory-region-names' is a
required property
9 (ti,j721e-r5fss): r5f@5f00000: 'memory-region-names' is a
required property
9 (ti,j721e-r5fss): r5f@5e00000: 'memory-region-names' is a
required property
9 (ti,j721e-r5fss): r5f@5d00000: 'memory-region-names' is a
required property
9 (ti,j721e-r5fss): r5f@5c00000: 'memory-region-names' is a
required property
9 (ti,j721e-r5fss): r5f@41400000: 'memory-region-names' is a
required property
9 (ti,j721e-r5fss): r5f@41000000: 'memory-region-names' is a
required property
4 (ti,am62-r5fss): r5f@78400000: 'memory-region-names' is a
required property
3 (ti,j7200-r5fss): r5f@5d00000: 'memory-region-names' is a
required property
3 (ti,j7200-r5fss): r5f@5c00000: 'memory-region-names' is a
required property
3 (ti,j7200-r5fss): r5f@41400000: 'memory-region-names' is a
required property
3 (ti,j7200-r5fss): r5f@41000000: 'memory-region-names' is a
required property
If they aren't applied, making 'memory-region-names' required needs
to be dropped from the binding.
Rob
^ permalink raw reply
* Re: [PATCH v6 13/21] drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature
From: Laurent Pinchart @ 2026-04-08 15:08 UTC (permalink / raw)
To: Tommaso Merciai
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <136a9922-48ae-48e2-8cb1-14559206e7af@bp.renesas.com>
On Wed, Apr 08, 2026 at 04:58:01PM +0200, Tommaso Merciai wrote:
> On 4/8/26 16:17, Laurent Pinchart wrote:
> > On Wed, Apr 08, 2026 at 04:12:22PM +0200, Tommaso Merciai wrote:
> >> On 4/8/26 14:31, Laurent Pinchart wrote:
> >>> On Wed, Apr 08, 2026 at 12:36:58PM +0200, Tommaso Merciai wrote:
> >>>> The MIPI DSI ip found in the RZ/G3E SoC select the video input clock
> >>>> based on the DU instance actually connected using the GPO0R register.
> >>>>
> >>>> Add this feature to the driver using `RZ_MIPI_DSI_FEATURE_GPO0R`, update
> >>>> the code accordingly to manage the vclk selection with the introduction
> >>>> of `rzg2l_mipi_dsi_get_input_port()`.
> >>>>
> >>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >>>> ---
> >>>> v5->v6:
> >>>> - Moved rzg2l_mipi_dsi_link_write() into rzv2h_mipi_dsi_dphy_init()
> >>>> + comments from HW Manual.
> >>>>
> >>>> v4->v5:
> >>>> - No changes.
> >>>>
> >>>> v3->v4:
> >>>> - No changes.
> >>>>
> >>>> v2->v3:
> >>>> - No changes.
> >>>>
> >>>> v1->v2:
> >>>> - No changes.
> >>>>
> >>>> .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 71 +++++++++++++++++--
> >>>> .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 3 +
> >>>> 2 files changed, 68 insertions(+), 6 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> >>>> index be6dbf19a24e..947c8e15fc4b 100644
> >>>> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> >>>> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> >>>> @@ -37,7 +37,9 @@ MODULE_IMPORT_NS("RZV2H_CPG");
> >>>>
> >>>> #define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */
> >>>>
> >>>> +#define RZ_MIPI_DSI_MAX_INPUT 2
> >>>> #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0)
> >>>> +#define RZ_MIPI_DSI_FEATURE_GPO0R BIT(1)
> >>>>
> >>>> struct rzg2l_mipi_dsi;
> >>>>
> >>>> @@ -81,13 +83,14 @@ struct rzg2l_mipi_dsi {
> >>>> struct drm_bridge bridge;
> >>>> struct drm_bridge *next_bridge;
> >>>>
> >>>> - struct clk *vclk;
> >>>> + struct clk *vclk[RZ_MIPI_DSI_MAX_INPUT];
> >>>> struct clk *lpclk;
> >>>>
> >>>> enum mipi_dsi_pixel_format format;
> >>>> unsigned int num_data_lanes;
> >>>> unsigned int lanes;
> >>>> unsigned long mode_flags;
> >>>> + u8 vclk_idx;
> >>>>
> >>>> struct rzv2h_dsi_mode_calc mode_calc;
> >>>>
> >>>> @@ -543,8 +546,8 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_f
> >>>> unsigned long vclk_rate;
> >>>> unsigned int bpp;
> >>>>
> >>>> - clk_set_rate(dsi->vclk, mode_freq * KILO);
> >>>> - vclk_rate = clk_get_rate(dsi->vclk);
> >>>> + clk_set_rate(dsi->vclk[dsi->vclk_idx], mode_freq * KILO);
> >>>> + vclk_rate = clk_get_rate(dsi->vclk[dsi->vclk_idx]);
> >>>> if (vclk_rate != mode_freq * KILO)
> >>>> dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
> >>>> mode_freq * KILO, vclk_rate);
> >>>> @@ -687,6 +690,19 @@ static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> >>>> rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R,
> >>>> FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k));
> >>>>
> >>>> + /*
> >>>> + * From RZ/G3E HW manual (Rev.1.15) section 9.5.3 Operation,
> >>>> + * 9.5.3.1 Power on Reset and Initial Settings for All Operations.
> >>>> + * Figure 9.5-4 Power On/Off Sequence show that after writing to
> >>>> + * GPO0R.VICH register we need to wait for more than 1 x tp before
> >>>> + * writing to PLLENR.PLLEN.
> >>>> + *
> >>>> + * Note: GPO0R is a link register, not a PHY register. This setting
> >>>> + * is specific to RZ/G3E.
> >>>> + */
> >>>> + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_GPO0R)
> >>>> + rzg2l_mipi_dsi_link_write(dsi, GPO0R, dsi->vclk_idx);
> >>>> +
> >>>> /*
> >>>> * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
> >>>> * (C) After write to D-PHY registers we need to wait for more than 1 x tp
> >>>> @@ -1005,6 +1021,37 @@ static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
> >>>> return ret;
> >>>> }
> >>>>
> >>>> +static int rzg2l_mipi_dsi_get_input_port(struct rzg2l_mipi_dsi *dsi)
> >>>> +{
> >>>> + struct device_node *np = dsi->dev->of_node;
> >>>> + struct device_node *remote_ep, *ep_node;
> >>>> + struct of_endpoint ep;
> >>>> + bool ep_enabled;
> >>>> + int in_port;
> >>>> +
> >>>> + /* DSI can have only one port enabled */
> >>>
> >>> Why is that ? The hardware supports dynamic input selection, why can't
> >>> it be supported at runtime ?
> >>
> >> For runtime/dynamic you mean using DT overlay??
> >> like, remove:
> >>
> >> Removing - DU0 --> DSI (input 0 | port@0 ) overlay and
> >> install - DU1 --> DSI (input 1 | port@1 ) overlay and
> >> viceversa?
> >
> > No, I mean configurable by userspace, with two CRTCs sharing one DSI
> > encoder.
>
> Sorry, question:
> - Is it possible to create CRTC from user space?
No, the CRTCs are created by the driver, but you can have one DRM device
that covers two LCDCs, with one CRTC each, both connected to the same
DSI encoder (and apparently this applies to the LVDS encoder too).
Userspace then selects which CRTC drives which connector.
> From hardware point only one DSI input is selectable out of 2 LCDC's at
> a time.
>
> References:
> - 9.5.2.2.3 9.5 MIPI DSI Interface (DSI)
> General Purpose Output 0 Register (DSI_LINK_GPO0R)
>
> - 9.5 MIPI DSI Interface (DSI)
> 9.5.1.2 Block Diagram
> Figure 9.5-1 Video Input Interface
>
> >>>> + for_each_endpoint_of_node(np, ep_node) {
> >>>> + of_graph_parse_endpoint(ep_node, &ep);
> >>>> + if (ep.port >= RZ_MIPI_DSI_MAX_INPUT)
> >>>> + break;
> >>>> +
> >>>> + remote_ep = of_graph_get_remote_endpoint(ep_node);
> >>>> + ep_enabled = of_device_is_available(remote_ep);
> >>>> + of_node_put(remote_ep);
> >>>> +
> >>>> + if (ep_enabled) {
> >>>> + in_port = ep.port;
> >>>> + break;
> >>>> + }
> >>>> + }
> >>>> +
> >>>> + if (!ep_enabled)
> >>>> + return -EINVAL;
> >>>> +
> >>>> + dev_dbg(dsi->dev, "input port@%d\n", in_port);
> >>>> + return in_port;
> >>>> +}
> >>>> +
> >>>> /* -----------------------------------------------------------------------------
> >>>> * Bridge
> >>>> */
> >>>> @@ -1425,9 +1472,21 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> >>>> if (IS_ERR(dsi->mmio))
> >>>> return PTR_ERR(dsi->mmio);
> >>>>
> >>>> - dsi->vclk = devm_clk_get(dsi->dev, "vclk");
> >>>> - if (IS_ERR(dsi->vclk))
> >>>> - return PTR_ERR(dsi->vclk);
> >>>> + dsi->vclk[0] = devm_clk_get(dsi->dev, "vclk");
> >>>> + if (IS_ERR(dsi->vclk[0]))
> >>>> + return PTR_ERR(dsi->vclk[0]);
> >>>> +
> >>>> + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_GPO0R) {
> >>>> + dsi->vclk[1] = devm_clk_get(dsi->dev, "vclk2");
> >>>> + if (IS_ERR(dsi->vclk[1]))
> >>>> + return PTR_ERR(dsi->vclk[1]);
> >>>> +
> >>>> + ret = rzg2l_mipi_dsi_get_input_port(dsi);
> >>>> + if (ret < 0)
> >>>> + return dev_err_probe(dsi->dev, -EINVAL,
> >>>> + "No available input port\n");
> >>>> + dsi->vclk_idx = ret;
> >>>> + }
> >>>>
> >>>> dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
> >>>> if (IS_ERR(dsi->lpclk))
> >>>> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> >>>> index 2bef20566648..cee2e0bc5dc5 100644
> >>>> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> >>>> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> >>>> @@ -83,6 +83,9 @@
> >>>> #define LINKSR_SQCHRUN1 BIT(4)
> >>>> #define LINKSR_SQCHRUN0 BIT(0)
> >>>>
> >>>> +/* RZ/G3E General Purpose Output 0 Register */
> >>>> +#define GPO0R 0xc0
> >>>> +
> >>>> /* Tx Set Register */
> >>>> #define TXSETR 0x100
> >>>> #define TXSETR_NUMLANECAP (0x3 << 16)
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH] arm64: dts: rockchip: fix rk809 interrupt pin on rk3566-roc-pc
From: guoweix @ 2026-04-08 15:09 UTC (permalink / raw)
To: heiko
Cc: robh, krzk+dt, conor+dt, f.kardame, pgwipeout, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, guoweix
The RK809 PMIC interrupt pin on the Firefly ROC-RK3566-PC (Station M2)
is physically connected to GPIO0_A3 (RK_PA3) according to the board's
schematic.
Currently, the PMIC node incorrectly specifies RK_PA7 for the interrupt,
which prevents the PMIC from correctly signaling interrupts. (Note that
the pinctrl node 'pmic_int' correctly configures RK_PA3).
Fix this by updating the interrupts property to use RK_PA3.
Fixes: 30ac9b4e25d8 ("arm64: dts: rockchip: add dts for Firefly Station M2 rk3566")
Signed-off-by: guoweix <2298701336@qq.com>
---
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
index 7e499064e035..985770e3a5e2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -245,7 +245,7 @@ rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
- interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata
From: Fidelio LAWSON @ 2026-04-08 15:25 UTC (permalink / raw)
To: Andrew Lunn
Cc: Woojung Huh, UNGLinuxDriver, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Marek Vasut, Maxime Chevallier,
netdev, devicetree, linux-kernel, Fidelio Lawson
In-Reply-To: <a350c4b7-d816-455b-83c0-f4d98299c637@lunn.ch>
On 4/8/26 14:43, Andrew Lunn wrote:
>> The control register defines the following modes:
>> bits [1:0]:
>> 00 = workaround disabled
>> 01 = workaround 1 (DSP EQ training adjustment, LinkMD reg 0x3c)
>> 10 = workaround 2 (receiver LPF bandwidth, LinkMD reg 0x4c)
>
> There was a comment, which i only read after making the suggestion to
> use two bits, of exposing the different low pass filter bandwidths,
> rather than just picking one value. How useful is that?
>
> Andrew
Initially I limited the LPF setting to the single bandwidth explicitly
recommended by the errata (62MHz).
But I’ll extend the implementation to expose all documented LPF
bandwidth options so the interface is more flexible for users.
Best regards,
Fidelio
^ permalink raw reply
* Re: [net-next v1 v1 1/5] dt-bindings: net: starfive,jh7110-dwmac: Remove JH8100
From: Andrew Lunn @ 2026-04-08 15:27 UTC (permalink / raw)
To: Minda Chen
Cc: Alexandre Torgue, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, netdev, linux-kernel, linux-stm32, devicetree
In-Reply-To: <20260408084416.29753-2-minda.chen@starfivetech.com>
On Wed, Apr 08, 2026 at 04:44:12PM +0800, Minda Chen wrote:
> Remove JH8100 dt-bindings because do not support it now.
Could you expand on that. If there are devices out in the field, we
don't just drop support for it because the vendor has something newer.
If the device never made it outside of the vendors lab, then we might
consider dropping it.
Please explain in detail why this is being dropped.
Andrew
^ permalink raw reply
* Re: [net-next v1 v1 3/5] dt-bindings: net: starfive,jh7110-dwmac: Add JHB100 sgmii rx clk
From: Andrew Lunn @ 2026-04-08 15:33 UTC (permalink / raw)
To: Minda Chen
Cc: Alexandre Torgue, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, netdev, linux-kernel, linux-stm32, devicetree
In-Reply-To: <20260408084416.29753-4-minda.chen@starfivetech.com>
> + - description: SGMII RX clock
>
> clock-names:
> - items:
> - - const: stmmaceth
> - - const: pclk
> - - const: ptp_ref
> - - const: tx
> - - const: gtx
> + minItems: 5
> + maxItems: 6
> + contains:
> + enum:
> + - stmmaceth
> + - pclk
> + - ptp_ref
> + - tx
> + - gtx
> + - rx
If this is only used for sgmii, maybe it should have sgmii in the
name?
Andrew
^ permalink raw reply
* Re: [net-next v1 v1 4/5] net: stmmac: starfive: Add JHB100 SGMII interface
From: Andrew Lunn @ 2026-04-08 15:36 UTC (permalink / raw)
To: Minda Chen
Cc: Alexandre Torgue, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, netdev, linux-kernel, linux-stm32, devicetree
In-Reply-To: <20260408084416.29753-5-minda.chen@starfivetech.com>
> + dwmac->sgmii_rx = devm_clk_get_optional(&pdev->dev, "rx");
> + if (IS_ERR(dwmac->sgmii_rx))
> + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->sgmii_rx),
> + "error getting sgmii rx clock\n");
> +
The SGMII clock is optional...
> /* Generally, the rgmii_tx clock is provided by the internal clock,
> * which needs to match the corresponding clock frequency according
> * to different speeds. If the rgmii_tx clock is provided by the
> * external rgmii_rxin, there is no need to configure the clock
> * internally, because rgmii_rxin will be adaptively adjusted.
> */
> - if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk"))
> - plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
> + if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk")) {
> + if (plat_dat->phy_interface == PHY_INTERFACE_MODE_SGMII)
> + plat_dat->set_clk_tx_rate = stmmac_starfive_sgmii_set_clk_rate;
So you probably want to return an error here if it is missing.
Or you might want to look at the compatible, and make the clock
mandatory for this device.
Andrew
^ permalink raw reply
* Re: [PATCH v4 2/4] ASoC: codecs: Add TAS67524 quad-channel audio amplifier driver
From: Mark Brown @ 2026-04-08 15:41 UTC (permalink / raw)
To: Sen Wang
Cc: linux-sound, lgirdwood, robh, krzk+dt, conor+dt, devicetree,
perex, tiwai, shenghao-ding, kevin-lu, baojun.xu, niranjan.hy,
l-badrinarayanan, devarsht, v-singh1, linux-kernel
In-Reply-To: <20260408053149.1369350-3-sen@ti.com>
[-- Attachment #1: Type: text/plain, Size: 2697 bytes --]
On Wed, Apr 08, 2026 at 12:31:46AM -0500, Sen Wang wrote:
> +static int tas675x_dsp_mem_write(struct tas675x_priv *tas, u8 page, u8 reg, u32 val)
> +{
> +out:
> + __tas675x_select_book(tas, TAS675X_BOOK_DEFAULT);
> + mutex_unlock(&tas->io_lock);
Do we really need to restore the book here? The book select register is
marked as volatile so regmap will figure things out if it's the next
thing to write, and anything else will need to set whatever it wants
anyway. Alternatively if the book register were cached (which wouldn't
be a bad idea) then we'd need to restore whatever the cache has or
invalidate the cache.
> +static int tas675x_dsp_mem_read(struct tas675x_priv *tas, u8 page, u8 reg, u32 *val)
> +{
> +out:
> + __tas675x_select_book(tas, TAS675X_BOOK_DEFAULT);
> + mutex_unlock(&tas->io_lock);
Same here
> +static int tas675x_rtldg_thresh_info(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_info *uinfo)
> +{
> + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
> + uinfo->count = 1;
> + uinfo->value.integer.min = 0;
> + /* Accepts 32-bit values, even though 8bit MSB is ignored */
> + uinfo->value.integer.max = 0xFFFFFFFF;
This is going to break on 32 bit architectures since long is a 32 bit
signed value. You want LONG_MAX, or to restrict the value (which would
be more friendly to mixer-test!).
> +static int tas675x_set_dcldg_trigger(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + /* Wait for LOAD_DIAG to exit */
> + regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH1_CH2_REG,
> + state, (state & 0x0F) != TAS675X_STATE_LOAD_DIAG &&
> + (state >> 4) != TAS675X_STATE_LOAD_DIAG,
> + TAS675X_POLL_INTERVAL_US,
> + TAS675X_STATE_TRANSITION_TIMEOUT_US);
> + regmap_read_poll_timeout(tas->regmap, TAS675X_STATE_REPORT_CH3_CH4_REG,
> + state34, (state34 & 0x0F) != TAS675X_STATE_LOAD_DIAG &&
> + (state34 >> 4) != TAS675X_STATE_LOAD_DIAG,
> + TAS675X_POLL_INTERVAL_US,
> + TAS675X_STATE_TRANSITION_TIMEOUT_US);
Don't know how likely it is in practice but we ignore any timeout
failures in this function.
> +static irqreturn_t tas675x_irq_handler(int irq, void *data)
> +{
> + struct tas675x_priv *tas = data;
> +
> + if (!tas675x_check_faults(tas))
> + return IRQ_NONE;
> +
> + regmap_write(tas->regmap, TAS675X_RESET_REG, TAS675X_FAULT_CLEAR);
> + return IRQ_HANDLED;
> +}
This probably ought to take a runtime PM reference to ensure the I2C
controller is woken up, and in case in future you get regulator support.
Even if the device itself shouldn't be generating interrupts while it's
idle the interrupt might be shared or something might fire for some
other reason.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/3] remoteproc: imx_rproc: Pass bootaddr to SM CPU/LMM reset vector
From: Mathieu Poirier @ 2026-04-08 15:46 UTC (permalink / raw)
To: Peng Fan
Cc: Peng Fan (OSS), Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Daniel Baluta, linux-remoteproc@vger.kernel.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <PAXPR04MB8459AA009C932EB9D6139A11885BA@PAXPR04MB8459.eurprd04.prod.outlook.com>
On Wed, Apr 08, 2026 at 01:30:16AM +0000, Peng Fan wrote:
> > Subject: Re: [PATCH v2 2/3] remoteproc: imx_rproc: Pass bootaddr to
> > SM CPU/LMM reset vector
> >
> [...]
> >
> > >
> > > Aligning the ELF entry point with the hardware reset base on
> > Cortex‑M
> > > systems is possible, but it comes with several risks.
> >
> > I'm not asking to align the ELF entry point with the hardware reset base.
> > All I want is to have the correct start address embedded in the ELF file
> > to avoid having to use a mask.
>
> I see, per my understanding:
> FreeRTOS typically exposes __isr_vector, which corresponds to the hardware
> reset / vector table base.
> Zephyr (Cortex‑M) exposes _vector_table, which serves the same purpose.
> I am not certain about other RTOSes, but the pattern seems consistent:
> the vector table base is already available as a named ELF symbol.
>
> Given that, if the preferred approach is to parse the ELF and explicitly
> retrieve the hardware reset base, I can update the implementation accordingly.
> If you prefer to parse the elf file to get the hardware reset base,
> I could update to use them.
>
> Options1: Something as below:
> 1. Include rproc_elf_find_symbol in remoteproc_elf_loader.c
> 2. Use below in imx_rproc.c
> ret = rproc_elf_find_symbol(rproc, fw, "__isr_vector", &vector_base);
> if (ret)
> ret = rproc_elf_find_symbol(rproc, fw, "__vector_table", &vector_base);
>
> if (!ret)
> rproc->bootaddr = vector_base
> else
> dev_info(dev, "no __isr_vector or __vector_table\n")
No
>
> This makes the hardware reset base explicit, avoids masking e_entry.
>
> Option 2: User‑provided reset symbol via sysfs
> As an alternative, we could expose a sysfs attribute,
> e.g. reset_symbol, allowing users to specify the symbol name
> to be used as the reset base:
>
> echo __isr_vector > /sys/class/remoteproc/remoteprocX/reset_symbol
>
Definitely not.
The definition of e_entry in the specification is clear, i.e "the address of the
entry point from where the process starts executing". If masking is required
because the tool that puts the image together gets the wrong address, then it
should be fixed.
> The remoteproc core would then resolve that symbol from
> the ELF and set rproc->bootaddr accordingly.
> This provides maximum flexibility but does introduce a new user‑visible ABI,
> so I see it more as an opt‑in or fallback mechanism.
>
> Please let me know which approach you prefer, and I will update
> this series accordingly in v3..
>
> Thanks,
> Peng.
>
>
> >
> > > 1, Semantic mismatch (ELF vs. hardware behavior) 2, Debuggers may
> > > attempt to set breakpoints or start execution at the entry symbol
> > >
^ permalink raw reply
* Re: [PATCH v2 2/3] remoteproc: imx_rproc: Pass bootaddr to SM CPU/LMM reset vector
From: Daniel Baluta @ 2026-04-08 16:00 UTC (permalink / raw)
To: Peng Fan, Mathieu Poirier, Peng Fan (OSS)
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Daniel Baluta, linux-remoteproc@vger.kernel.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <PAXPR04MB8459AA009C932EB9D6139A11885BA@PAXPR04MB8459.eurprd04.prod.outlook.com>
On 4/8/26 04:30, Peng Fan wrote:
>> Subject: Re: [PATCH v2 2/3] remoteproc: imx_rproc: Pass bootaddr to
>> SM CPU/LMM reset vector
>>
> [...]
>>> Aligning the ELF entry point with the hardware reset base on
>> Cortex‑M
>>> systems is possible, but it comes with several risks.
>> I'm not asking to align the ELF entry point with the hardware reset base.
>> All I want is to have the correct start address embedded in the ELF file
>> to avoid having to use a mask.
> I see, per my understanding:
> FreeRTOS typically exposes __isr_vector, which corresponds to the hardware
> reset / vector table base.
> Zephyr (Cortex‑M) exposes _vector_table, which serves the same purpose.
> I am not certain about other RTOSes, but the pattern seems consistent:
> the vector table base is already available as a named ELF symbol.
>
> Given that, if the preferred approach is to parse the ELF and explicitly
> retrieve the hardware reset base, I can update the implementation accordingly.
> If you prefer to parse the elf file to get the hardware reset base,
> I could update to use them.
>
> Options1: Something as below:
> 1. Include rproc_elf_find_symbol in remoteproc_elf_loader.c
> 2. Use below in imx_rproc.c
> ret = rproc_elf_find_symbol(rproc, fw, "__isr_vector", &vector_base);
> if (ret)
> ret = rproc_elf_find_symbol(rproc, fw, "__vector_table", &vector_base);
>
> if (!ret)
> rproc->bootaddr = vector_base
> else
> dev_info(dev, "no __isr_vector or __vector_table\n")
>
> This makes the hardware reset base explicit, avoids masking e_entry.
>
> Option 2: User‑provided reset symbol via sysfs
> As an alternative, we could expose a sysfs attribute,
> e.g. reset_symbol, allowing users to specify the symbol name
> to be used as the reset base:
>
> echo __isr_vector > /sys/class/remoteproc/remoteprocX/reset_symbol
>
> The remoteproc core would then resolve that symbol from
> the ELF and set rproc->bootaddr accordingly.
> This provides maximum flexibility but does introduce a new user‑visible ABI,
> so I see it more as an opt‑in or fallback mechanism.
>
> Please let me know which approach you prefer, and I will update
> this series accordingly in v3..
I would go with option 1) as this and having something like this:
#define IMX_RPROC_DEFAULT_RST_VECTOR_NAME "..."
later we can expand that with a configurable name via sysfs.
This was along my initial proposal where you would determine
the reset vector address from the elf file.
^ permalink raw reply
* Re: [PATCH 1/6] net: ipa: fix GENERIC_CMD register field masks for IPA v5.0+
From: Simon Horman @ 2026-04-08 16:34 UTC (permalink / raw)
To: Luca Weiss
Cc: Alex Elder, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Alexander Koskovich,
~postmarketos/upstreaming, phone-devel, netdev, linux-kernel,
linux-arm-msm, devicetree
In-Reply-To: <20260403-milos-ipa-v1-1-01e9e4e03d3e@fairphone.com>
On Fri, Apr 03, 2026 at 06:43:47PM +0200, Luca Weiss wrote:
> From: Alexander Koskovich <akoskovich@pm.me>
>
> Fix the field masks to match the hardware layout documented in
> downstream GSI (GSI_V3_0_EE_n_GSI_EE_GENERIC_CMD_*).
>
> Notably this fixes a WARN I was seeing when I tried to send "stop"
> to the MPSS remoteproc while IPA was up.
>
> Fixes: faf0678ec8a0 ("net: ipa: add IPA v5.0 GSI register definitions")
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Simon Horman <horms@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/6] net: ipa: fix event ring index not programmed for IPA v5.0+
From: Simon Horman @ 2026-04-08 16:35 UTC (permalink / raw)
To: Luca Weiss
Cc: Alex Elder, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Alexander Koskovich,
~postmarketos/upstreaming, phone-devel, netdev, linux-kernel,
linux-arm-msm, devicetree
In-Reply-To: <20260403-milos-ipa-v1-2-01e9e4e03d3e@fairphone.com>
On Fri, Apr 03, 2026 at 06:43:48PM +0200, Luca Weiss wrote:
> From: Alexander Koskovich <akoskovich@pm.me>
>
> For IPA v5.0+, the event ring index field moved from CH_C_CNTXT_0 to
> CH_C_CNTXT_1. The v5.0 register definition intended to define this
> field in the CH_C_CNTXT_1 fmask array but used the old identifier of
> ERINDEX instead of CH_ERINDEX.
>
> Without a valid event ring, GSI channels could never signal transfer
> completions. This caused gsi_channel_trans_quiesce() to block
> forever in wait_for_completion().
>
> At least for IPA v5.2 this resolves an issue seen where runtime
> suspend, system suspend, and remoteproc stop all hanged forever. It
> also meant the IPA data path was completely non functional.
>
> Fixes: faf0678ec8a0 ("net: ipa: add IPA v5.0 GSI register definitions")
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Simon Horman <horms@kernel.org>
^ permalink raw reply
* Re: [PATCH 4/6] net: ipa: add IPA v5.2 configuration data
From: Simon Horman @ 2026-04-08 16:36 UTC (permalink / raw)
To: Luca Weiss
Cc: Alex Elder, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio, Alexander Koskovich,
~postmarketos/upstreaming, phone-devel, netdev, linux-kernel,
linux-arm-msm, devicetree
In-Reply-To: <20260403-milos-ipa-v1-4-01e9e4e03d3e@fairphone.com>
On Fri, Apr 03, 2026 at 06:43:50PM +0200, Luca Weiss wrote:
> Add the configuration data required for IPA v5.2, which is used in
> the Qualcomm Milos SoC.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> drivers/net/ipa/Makefile | 2 +-
> drivers/net/ipa/data/ipa_data-v5.2.c | 452 +++++++++++++++++++++++++++++++++++
> drivers/net/ipa/gsi_reg.c | 1 +
> drivers/net/ipa/ipa_data.h | 1 +
> drivers/net/ipa/ipa_main.c | 4 +
> drivers/net/ipa/ipa_reg.c | 1 +
> drivers/net/ipa/ipa_sysfs.c | 2 +
> drivers/net/ipa/ipa_version.h | 2 +
> 8 files changed, 464 insertions(+), 1 deletion(-)
Reviewed-by: Simon Horman <horms@kernel.org>
I'm not suggesting a change to this patch.
But it does seem to me that there is a lot of commonality
between drivers/net/ipa/data/ipa_data-v*.c.
And it would be nice if that could be consolidated somehow.
...
^ permalink raw reply
* [PATCH v2 2/2] fpga: ts73xx-fpga: add OF match table for device tree probing
From: Phil Pemberton @ 2026-04-08 16:52 UTC (permalink / raw)
To: Moritz Fischer, Xu Yilun, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Tom Rix, Florian Fainelli, linux-fpga, devicetree, linux-kernel,
Phil Pemberton
In-Reply-To: <20260408165223.3051759-1-philpem@philpem.me.uk>
The ts73xx-fpga driver currently only matches by platform device name,
which prevents it from being probed when the device is described in a
device tree. Add an of_device_id table so the driver can match against
the "technologic,ts7300-fpga" compatible string.
The TS-7350 and TS-7390 use different FPGAs with a different programming
interface, so while the driver is named "ts73xx-fpga", it doesn't apply
to them.
Signed-off-by: Phil Pemberton <philpem@philpem.me.uk>
---
drivers/fpga/ts73xx-fpga.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
index 4e1d2a4d3df4..3460e4809f86 100644
--- a/drivers/fpga/ts73xx-fpga.c
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -11,6 +11,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <linux/iopoll.h>
@@ -119,9 +120,17 @@ static int ts73xx_fpga_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(mgr);
}
+static const struct of_device_id ts73xx_fpga_of_match[] = {
+ { .compatible = "technologic,ts7300-fpga" },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, ts73xx_fpga_of_match);
+
static struct platform_driver ts73xx_fpga_driver = {
.driver = {
.name = "ts73xx-fpga-mgr",
+ .of_match_table = ts73xx_fpga_of_match,
},
.probe = ts73xx_fpga_probe,
};
--
2.43.0
^ permalink raw reply related
* [PATCH v2 0/2] Add device tree binding for ts73xx-fpga
From: Phil Pemberton @ 2026-04-08 16:52 UTC (permalink / raw)
To: Moritz Fischer, Xu Yilun, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Tom Rix, Florian Fainelli, linux-fpga, devicetree, linux-kernel,
Phil Pemberton
The driver for the Technologic Systems (EmbeddedTS) TS-7300 board's
onboard FPGA didn't have an OF match table. This prevented it from being
instantiated from a device tree. This is undesirable given EP93xx is
moving to device tree, and effectively prevents it from being used.
This patch series adds the OF match table and a device tree binding.
Changes since v1:
- Use specific compatible "technologic,ts7300-fpga" instead of
wildcard "technologic,ts73xx-fpga" (Krzysztof)
- Fix subject line for dt-bindings patch (Krzysztof)
- Simplify example in binding doc (Krzysztof)
Phil Pemberton (2):
dt-bindings: fpga: Technologic Systems TS-7300 FPGA Manager
fpga: ts73xx-fpga: add OF match table for device tree probing
.../fpga/technologic,ts7300-fpga.yaml | 36 +++++++++++++++++++
drivers/fpga/ts73xx-fpga.c | 9 +++++
2 files changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml
--
2.43.0
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: fpga: Technologic Systems TS-7300 FPGA Manager
From: Phil Pemberton @ 2026-04-08 16:52 UTC (permalink / raw)
To: Moritz Fischer, Xu Yilun, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Tom Rix, Florian Fainelli, linux-fpga, devicetree, linux-kernel,
Phil Pemberton
In-Reply-To: <20260408165223.3051759-1-philpem@philpem.me.uk>
Add device tree binding documentation for the Altera Cyclone II FPGA
found on Technologic Systems (now EmbeddedTS) TS-7300 boards, programmed
via the memory-mapped interface in the CPLD.
Signed-off-by: Phil Pemberton <philpem@philpem.me.uk>
---
.../fpga/technologic,ts7300-fpga.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml
diff --git a/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml b/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml
new file mode 100644
index 000000000000..c93e3a1a135b
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/technologic,ts7300-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Technologic Systems TS-7300 FPGA Manager
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+description:
+ FPGA manager for the Altera Cyclone II FPGA on Technologic Systems
+ TS-7300 board. The FPGA is programmed via the memory-mapped interface
+ implemented in the CPLD.
+
+properties:
+ compatible:
+ const: technologic,ts7300-fpga
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ fpga-mgr@13c00000 {
+ compatible = "technologic,ts7300-fpga";
+ reg = <0x13c00000 0x2>;
+ };
+...
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 2/3] nvmem: Add the Raspberry Pi OTP driver
From: Stefan Wahren @ 2026-04-08 16:52 UTC (permalink / raw)
To: Gregor Herburger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Srinivas Kandagatla
Cc: devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel
In-Reply-To: <20260408-rpi-otp-driver-v1-2-e02d1dbe6008@linutronix.de>
Hi Gregor,
[drop Emma's old address]
Am 08.04.26 um 10:00 schrieb Gregor Herburger:
> Raspberry Pis have OTP registers which can be accessed through the
> videocore firmware. Add a nvmem driver to support these OTP registers.
>
> Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
> ---
> drivers/nvmem/Kconfig | 12 +++
> drivers/nvmem/Makefile | 1 +
> drivers/nvmem/raspberrypi-otp.c | 159 +++++++++++++++++++++++++++++
> include/soc/bcm2835/raspberrypi-firmware.h | 2 +
> 4 files changed, 174 insertions(+)
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 74ddbd0f79b0..892d05fe67be 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -483,4 +483,16 @@ config NVMEM_QORIQ_EFUSE
> This driver can also be built as a module. If so, the module
> will be called nvmem_qoriq_efuse.
>
> +config NVMEM_RASPBERRYPI_OTP
> + tristate "Raspberry Pi OTP support"
> + # Make sure not 'y' when RASPBERRYPI_FIRMWARE is 'm'. This can only
> + # happen when COMPILE_TEST=y, hence the added !RASPBERRYPI_FIRMWARE.
I don't think these comments are necessary, because this applies to
other firmware drivers, too.
> + depends on RASPBERRYPI_FIRMWARE || (COMPILE_TEST && !RASPBERRYPI_FIRMWARE)
> + help
> + This driver provides access to the Raspberry Pi OTP memory via the
> + nvmem subsystem. The driver supports the customer otp as well as the
> + device specific private key OTP.
> +
> + This driver can also be built as a module. If so, the module
> + will be called raspberrypi-otp.
> endif
> diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
> index 7252b8ec88d4..8ca2095e068f 100644
> --- a/drivers/nvmem/Makefile
> +++ b/drivers/nvmem/Makefile
> @@ -95,3 +95,4 @@ obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o
> nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o
> obj-$(CONFIG_NVMEM_QORIQ_EFUSE) += nvmem-qoriq-efuse.o
> nvmem-qoriq-efuse-y := qoriq-efuse.o
> +obj-$(CONFIG_NVMEM_RASPBERRYPI_OTP) += raspberrypi-otp.o
> diff --git a/drivers/nvmem/raspberrypi-otp.c b/drivers/nvmem/raspberrypi-otp.c
> new file mode 100644
> index 000000000000..13ee3784b137
> --- /dev/null
> +++ b/drivers/nvmem/raspberrypi-otp.c
> @@ -0,0 +1,159 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <linux/module.h>
> +#include <linux/nvmem-provider.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <soc/bcm2835/raspberrypi-firmware.h>
> +
> +struct rpi_otp_priv {
> + struct rpi_firmware *fw;
> + struct device *dev;
> + u32 read_tag;
> + u32 write_tag;
> +};
> +
> +struct rpi_otp_driver_data {
> + const char *name;
> + u32 read_tag;
> + u32 write_tag;
> +};
> +
> +struct rpi_otp_header {
> + u32 start;
> + u32 count;
> + u32 data[];
> +};
> +
> +static int rpi_otp_read(void *context, unsigned int offset, void *buf, size_t bytes)
> +{
> + struct rpi_otp_priv *priv = context;
> + struct rpi_otp_header *fwbuf;
> + int ret;
> +
> + fwbuf = kmalloc(sizeof(struct rpi_otp_header) + bytes, GFP_KERNEL);
> + if (!fwbuf)
> + return -ENOMEM;
> +
> + fwbuf->start = offset / 4;
> + fwbuf->count = bytes / 4;
> +
> + ret = rpi_firmware_property(priv->fw, priv->read_tag, fwbuf,
> + sizeof(struct rpi_otp_header) + bytes);
> + if (ret)
> + goto out;
> +
> + memcpy(buf, fwbuf->data, bytes);
> +
> +out:
> + kfree(fwbuf);
> + return ret;
> +}
> +
> +static int rpi_otp_write(void *context, unsigned int offset, void *val, size_t bytes)
> +{
> + struct rpi_otp_priv *priv = context;
> + struct rpi_otp_header *fwbuf;
> + int ret;
> +
> + fwbuf = kmalloc(sizeof(struct rpi_otp_header) + bytes, GFP_KERNEL);
> + if (!fwbuf)
> + return -ENOMEM;
> +
> + fwbuf->start = offset / 4;
> + fwbuf->count = bytes / 4;
> + memcpy(fwbuf->data, val, bytes);
> +
> + ret = rpi_firmware_property(priv->fw, priv->write_tag, fwbuf,
> + sizeof(struct rpi_otp_header) + bytes);
> +
> + kfree(fwbuf);
> + return ret;
> +}
> +
> +static const struct rpi_otp_driver_data rpi_otp_customer = {
> + .name = "rpi-otp-customer",
> + .read_tag = RPI_FIRMWARE_GET_CUSTOMER_OTP,
> + .write_tag = RPI_FIRMWARE_SET_CUSTOMER_OTP,
> +};
> +
> +static const struct rpi_otp_driver_data rpi_otp_private = {
> + .name = "rpi-otp-private",
> + .read_tag = RPI_FIRMWARE_GET_PRIVATE_OTP,
> + .write_tag = RPI_FIRMWARE_SET_PRIVATE_OTP,
> +};
> +
> +static int rpi_otp_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct nvmem_device *nvmem;
> + struct rpi_otp_priv *priv;
> + struct device_node *np;
> + const struct rpi_otp_driver_data *data;
> + struct nvmem_config config = {
> + .read_only = false,
> + .word_size = 4,
> + .stride = 4,
> + .reg_read = rpi_otp_read,
> + .reg_write = rpi_otp_write,
> + .size = 32,
> + };
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + data = device_get_match_data(dev);
> + if (!data)
> + return -ENODEV;
> +
> + np = of_get_parent(dev->of_node);
> + if (!np) {
> + dev_err(dev, "Missing firmware node\n");
> + return -ENOENT;
> + }
> +
> + priv->fw = devm_rpi_firmware_get(&pdev->dev, np);
> + of_node_put(np);
> + if (!priv->fw)
> + return -EPROBE_DEFER;
> +
> + priv->dev = dev;
> + priv->read_tag = data->read_tag;
> + priv->write_tag = data->write_tag;
> + config.dev = dev;
> + config.priv = priv;
> + config.name = data->name;
> +
> + nvmem = devm_nvmem_register(dev, &config);
> + if (IS_ERR(nvmem))
> + return dev_err_probe(dev, PTR_ERR(nvmem), "error registering nvmem config\n");
> +
> + return 0;
> +}
Is there any reason, why we cannot register this driver in
rpi_firmware_probe() like hwmon and clk driver?
I like to avoid the complete dt-binding from patch 1.
> +
> +static const struct of_device_id rpi_otp_of_match[] = {
> + {
> + .compatible = "raspberrypi,firmware-otp-customer",
> + .data = &rpi_otp_customer
> + },
> + {
> + .compatible = "raspberrypi,firmware-otp-private",
> + .data = &rpi_otp_private,
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, rpi_otp_of_match);
> +
> +static struct platform_driver raspberry_otp_driver = {
> + .probe = rpi_otp_probe,
> + .driver = {
> + .name = "rpi-otp",
> + .of_match_table = rpi_otp_of_match,
> + },
> +};
> +module_platform_driver(raspberry_otp_driver);
> +
> +MODULE_AUTHOR("Gregor Herburger <gregor.herburger@linutronix.de>");
> +MODULE_DESCRIPTION("Raspberry OTP driver");
Raspberry Pi OTP driver ?
Regards
> +MODULE_LICENSE("GPL");
> diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h
> index e1f87fbfe554..6e94ccf34f47 100644
> --- a/include/soc/bcm2835/raspberrypi-firmware.h
> +++ b/include/soc/bcm2835/raspberrypi-firmware.h
> @@ -92,6 +92,8 @@ enum rpi_firmware_property_tag {
> RPI_FIRMWARE_SET_POE_HAT_VAL = 0x00030050,
> RPI_FIRMWARE_NOTIFY_XHCI_RESET = 0x00030058,
> RPI_FIRMWARE_NOTIFY_DISPLAY_DONE = 0x00030066,
> + RPI_FIRMWARE_GET_PRIVATE_OTP = 0x00030081,
> + RPI_FIRMWARE_SET_PRIVATE_OTP = 0x00038081,
>
> /* Dispmanx TAGS */
> RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001,
>
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: input: adc-keys: allow linux,input-type property
From: Dmitry Torokhov @ 2026-04-08 16:59 UTC (permalink / raw)
To: Rob Herring
Cc: Nicolas Frattaroli, Krzysztof Kozlowski, Krzysztof Kozlowski,
Conor Dooley, Alexandre Belloni, Heiko Stuebner, kernel,
linux-input, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip
In-Reply-To: <20251217133440.GA724723-robh@kernel.org>
On Wed, Dec 17, 2025 at 07:34:40AM -0600, Rob Herring wrote:
> On Wed, Dec 17, 2025 at 01:57:46PM +0100, Nicolas Frattaroli wrote:
> > On Wednesday, 17 December 2025 09:31:15 Central European Standard Time Krzysztof Kozlowski wrote:
> > > On Mon, Dec 15, 2025 at 01:29:29PM +0100, Nicolas Frattaroli wrote:
> > > > adc-keys, unlike gpio-keys, does not allow linux,input-type as a valid
> > > > property. This makes it impossible to model devices that have ADC inputs
> > > > that should generate switch events.
> > >
> > > The solution is to use unevaluatedProps instead, which also allows
> > > dropping other properties.
> > >
> > > Best regards,
> > > Krzysztof
> > >
> > >
> >
> > Hi Krzysztof,
> >
> > to understand the motivation behind this suggestion correctly:
> > are the "linux," vendor prefixed properties, especially with regards
> > to key codes, generally a bit of a thorn in the side of DT bindings
> > maintainers?
>
> Not really. Most have existed for decades. New ones get extra scrutiny
> and often end up dropping the linux prefix.
>
> > I'd imagine so since they technically tie the DT to a specific OS
> > kernel (though of course, others are free to translate those key
> > codes). And the whole idea of configuring which code is emitted
> > from something is basically abusing DT for configuring software
> > rather than describing hardware.
> >
> > I'm mainly interested because this is a thought that has been in
> > the back of my mind for a while now, and I'm curious if the DT
> > binding maintainers happen to have arrived at the same impassé,
> > where linux,input-type et al abuse the DT model for something we
> > would tell any other vendor not to abuse it for, but no better
> > solution exists right now to achieve the same thing.
>
> Not sure what the BSDs do here. It's never come up that I remember. Best
> I can tell is they just make it a userspace problem. So every possible
> keyboard needs a keymap file. Though I'm not sure how that would work
> with GPIO keys as you don't really have a scan code.
Is there an update for this binding or should I apply the current
version? I am OK with the driver changes...
Thanks.
--
Dmitry
^ permalink raw reply
* Re: [PATCH 0/3] pic64gx semantic conflict "fixes"
From: Conor Dooley @ 2026-04-08 17:04 UTC (permalink / raw)
To: linux-riscv, Conor Dooley
Cc: Conor Dooley, Daire McNamara, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
On Tue, 07 Apr 2026 16:36:22 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> CC: Conor Dooley <conor.dooley@microchip.com>
> CC: Daire McNamara <daire.mcnamara@microchip.com>
> CC: Rob Herring <robh@kernel.org>
> CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
> CC: Paul Walmsley <pjw@kernel.org>
> CC: Palmer Dabbelt <palmer@dabbelt.com>
> CC: Albert Ou <aou@eecs.berkeley.edu>
> CC: Alexandre Ghiti <alex@ghiti.fr>
> CC: linux-riscv@lists.infradead.org
> CC: devicetree@vger.kernel.org
> CC: linux-kernel@vger.kernel.org
>
> [...]
Applied to riscv-dt-for-next, thanks!
[1/3] riscv: dts: microchip: add tsu clock to macb on pic64gx
https://git.kernel.org/conor/c/89991efc78d7
[2/3] riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
https://git.kernel.org/conor/c/53c013c3b27b
[3/3] riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
https://git.kernel.org/conor/c/ae488e2669f3
Thanks,
Conor.
^ permalink raw reply
* Re: [PATCH 2/4] ASoC: dt-bindings: Add support for the GPIOs driven amplifier
From: Herve Codina @ 2026-04-08 17:09 UTC (permalink / raw)
To: Rob Herring
Cc: Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley,
Saravana Kannan, Jaroslav Kysela, Takashi Iwai, linux-sound,
devicetree, linux-kernel, Christophe Leroy, Thomas Petazzoni
In-Reply-To: <20260408122901.GA42727-robh@kernel.org>
Hi Rob, Mark,
On Wed, 8 Apr 2026 07:29:01 -0500
Rob Herring <robh@kernel.org> wrote:
...
> > +properties:
> > + compatible:
> > + const: audio-gpio-amp
>
> To be consistent with other GPIO controlled devices: gpio-audio-amp
Ok.
Mark suggested to merge this gpio-audio-amp with simple-amplifier.
This leads to the following question:
Should I keep the 'gpio-audio-amp' compatible string ?
Should I keep two bindings (this one and the simple-audio-amplifier.yaml) or
should I merge bindings?
...
> > + gain-gpios:
> > + description: |
> > + GPIOs to control the amplifier gain
> > +
> > + The gain value is computed from GPIOs value from 0 to 2^N-1 with N the
> > + number of GPIO described. The first GPIO described is the lsb of the gain
> > + value.
> > +
> > + For instance assuming 2 gpios
> > + gain-gpios = <&gpio1 GPIO_ACTIVE_HIGH> <&gpio2 GPIO_ACTIVE_HIGH>;
> > + The gain value will be the following:
> > +
> > + gpio1 | gpio2 | gain
> > + ------+-------+-----
> > + 0 | 0 | 0b00 -> 0
> > + 1 | 0 | 0b01 -> 1
> > + 0 | 1 | 0b10 -> 2
> > + 1 | 1 | 0b11 -> 3
> > + ------+-------+-----
> > +
> > + Note: The gain value, bits set to 1 or 0, indicate the state active (bit
> > + set) or the state inactive (bit unset) of the related GPIO. The
> > + physical voltage corresponding to this active/inactive state is
> > + given by the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags.
> > +
> > + minItems: 1
> > + maxItems: 32
>
> 2^32 levels? Seems like a bit much. Also, unless you can change the
> values of all the GPIOs atomically, aren't you going to get some
> artifacts while the gain is being changed? Unless you mute I guess.
I didn't want to set a particular limit related to the number of GPIOs
used for thje gain value. Of course 2^32 is obviously a lot.
What do you think about 16 for maxItems?
Related to Artifacts, yes they can probably be there. Also the mute feature
is not required. Some hardware use only one GPIO and doesn't implement mute
feature. In that case no artifacts can be present.
If mute is implemented, it is the application responsibility to handle
mute / unmute while changing the gain value. I don't think we can do anything
at driver level to avoid those artifacts if any.
>
> > +
> > + gain-points:
> > + $ref: /schemas/types.yaml#/definitions/int32-matrix
> > + items:
> > + items:
> > + - description: The GPIOs value
>
> Can't this just be the index?
Some GPIOs value can be skipped if they don't make any sense in the hardware
design. With the index, this is not possible.
gpios:
0b00 -3dB
0b01 0dB
0b10 Reserved, should not be used
0b11 +3dB
With just the index, the reserved 0b10 value cannot be skipped. I would like
to handle this kind of cases.
>
> If not, then gain-range could be expressed using gain-points instead.
Do you have in mind something like the following?
gain-range = <0 (-300)>, <3 600>;
defining the range from -3dB to +6dB with GPIOs value 0 for -3dB and 3 for +6dB.
>
> > + - description: The related amplifier gain in 0.01 dB unit
> > + minItems: 2
> > + description: |
> > + List of the GPIOs value / Gain value in dB pair defining the gain
> > + set on each GPIOs value.
> > +
> > + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3.
> > + Assuming that GPIOs values set the hardware gains according to the
> > + following table:
> > +
> > + GPIOs | Hardware
> > + value | amplification
> > + ------+--------------
> > + 0 | -10.0 dB
> > + 1 | +3.0 dB
> > + 2 | 0 dB
> > + 3 | +6.0 dB
> > + ------+--------------
> > +
> > + The description using gain points can be:
> > + gain-points = <0 (-1000)>, <1 300>, <2 0>, <3 600>;
> > +
> > + gain-range:
> > + $ref: /schemas/types.yaml#/definitions/int32-array
> > + items:
> > + - description: Gain in 0.01 dB unit when all GPIOs are inactive
> > + - description: Gain in 0.01 dB unit when all GPIOs are active
> > + description: |
> > + Gains (in 0.01 dB unit) set by the extremum (minimal and maximum) value
> > + of GPIOs. The following formula must be satisfied.
> > +
> > + gain-range[1] - gain-range[0]
> > + Gain = ------------------------------- x GPIO_value + gain-range[0]
> > + 2^N - 1
> > +
> > + With N, the number of GPIOs used to control the gain and Gain computed in
> > + 0.01 dB unit.
> > +
> > + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3.
> > + Assuming that gain value set the hardware according to the following
> > + table:
> > +
> > + GPIOs | Hardware 1 | Hardware 2
> > + value | amplification | amplification
> > + ------+---------------+---------------
> > + 0 | -3.0 dB | +10.0 dB
> > + 1 | 0 dB | +5.0 dB
> > + 2 | +3.0 dB | 0 dB
> > + 3 | +6.0 dB | -5.0 dB
> > + ------+---------------+---------------
> > +
> > + The description for hardware 1 using a gain range can be:
> > + gain-range = <(-300) 600>;
> > +
> > + The description for hardware 2 using a gain range can be:
> > + gain-range = <1000 (-500)>;
> > +
> > + gain-labels:
> > + $ref: /schemas/types.yaml#/definitions/string-array
>
> minItems: 2
> maxItems: 0x100000000
Ok, I will adjust maxItems according to the max number of GPIO supported.
For my curiosity, is there a way to express maxItems with a computation
based on some other properties value ?
What could be relevant here is
maxitems: 2^(number of items available in the gpio-gain properties)
>
> > + description: |
> > + List of the gain labels attached to the combination of GPIOs controlling
> > + the gain. The first label is related to the gain value 0, the second label
> > + is related to the gain value 1 and so on.
> > +
> > + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3.
> > + Assuming that gain value set the hardware according to the following
> > + table:
> > +
> > + GPIOs | Hardware
> > + value | amplification
> > + ------+--------------
> > + 0 | Low
> > + 1 | Middle
> > + 2 | High
> > + 3 | Max
> > + ------+--------------
> > +
> > + The description using gain labels can be:
> > + gain-labels = "Low", "Middle", "High", "Max";
>
> Do we need to allow these to be anything? It's going to get hard to come
> up with 2^32 names.
Well, "Normal" / "Boost" can make sense on some hardware.
I don't think we need to restrict labels to a list of known label here.
Of course 2^32 names is obviously a lot. What could be the limit?
>
> > +
> > +dependencies:
> > + gain-points: [ gain-gpios ]
> > + gain-range: [ gain-gpios ]
> > + gain-labels: [ gain-gpios ]
>
> gain-gpios is really optional?
Yes, we can have an amplifier without any possibility to change the gain
value but with a gpio allowing to mute or bypass the amplifier.
...
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > +
> > + /* Gain controlled by gpios */
> > + amplifier0 {
>
> amplifier-0
Ok, it will be update in the next iteration as well as other node
names available in this example part.
...
> > +
> > + /* A mutable amplifier without any gain control */
> > + amplifier4 {
> > + compatible = "audio-gpio-amp";
> > + vdd-supply = <®ulator>;
> > + mute-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
>
> This case is just simple-amplifier...
No, simple-amplifier uses 'enable' and not 'mute'.
We can have the amplifier enabled ('enable' GPIO active) as it is
used and a switch driven by an other GPIO to mute / un-mute the
amplifier output.
Best regards,
Hervé
^ permalink raw reply
* Re: [PATCH v2 1/4] riscv: add UltraRISC SoC family Kconfig support
From: Conor Dooley @ 2026-04-08 17:10 UTC (permalink / raw)
To: Jia Wang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley, linux-riscv,
linux-kernel, linux-pci, devicetree
In-Reply-To: <177561282495.2731393.9548650582911498336.b4-reply@b4>
[-- Attachment #1: Type: text/plain, Size: 2372 bytes --]
On Wed, Apr 08, 2026 at 09:47:04AM +0800, Jia Wang wrote:
> On 2026-04-07 17:29 +0100, Conor Dooley wrote:
> > On Tue, Apr 07, 2026 at 10:40:52AM +0800, Jia Wang wrote:
> > > The first SoC in the UltraRISC series is UR-DP1000, containing octa
> > > UltraRISC C100 cores.
> >
> > Not gonna lie, I find it odd that pcie is where this platform starts
> > off, but sure. What's the plan for adding the rest of the platform?
> >
>
> Hi Conor,
>
> Thanks for the question.
>
> Our next step is to upstream the pinctrl driver together with the related
> DTS updates. The pinctrl series only affects the SoC’s low-speed peripheral
> interfaces. For GMAC, SPI, I2C, and GPIO, we plan to use the existing
> kernel drivers, so no new controller drivers are needed
And clocks? pinctrl and clocks would be the bare minimum level of
support required before a platform should be merged. Obviously, you can
get device drivers for PCI etc etc merged without clock drivers, but the
initial dts should contain the clocks too.
> > >
> > > Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> > > ---
> > > arch/riscv/Kconfig.socs | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > > index d621b85dd63b..98708569ec6a 100644
> > > --- a/arch/riscv/Kconfig.socs
> > > +++ b/arch/riscv/Kconfig.socs
> > > @@ -84,6 +84,15 @@ config ARCH_THEAD
> > > help
> > > This enables support for the RISC-V based T-HEAD SoCs.
> > >
> > > +config ARCH_ULTRARISC
> > > + bool "UltraRISC RISC-V SoCs"
> > > + help
> > > + This enables support for UltraRISC SoC platform hardware,
> > > + including boards based on the UR-DP1000.
> >
> > > + UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports
> > > + the RV64GCBHX ISA. It supports Hardware Virtualization
> > > + and RISC-V RV64 ISA H(v1.0) Extension.
> >
> > Delete this section IMO, doesn't provide any real value. Don't need nor
> > want the marketing brochure in the help text. The first sentence is
> > sufficient.
> >
>
> I’ll drop the SoC description part from the Kconfig help text as you
> suggested.
>
> > > +
> > > config ARCH_VIRT
> > > bool "QEMU Virt Machine"
> > > select POWER_RESET
> > >
> > > --
> > > 2.34.1
> > >
>
> Best regards,
> Jia Wang
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: input: adc-keys: allow linux,input-type property
From: Nicolas Frattaroli @ 2026-04-08 17:11 UTC (permalink / raw)
To: Rob Herring, Dmitry Torokhov
Cc: Krzysztof Kozlowski, Krzysztof Kozlowski, Conor Dooley,
Alexandre Belloni, Heiko Stuebner, kernel, linux-input,
devicetree, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <adaJOEZHHmvZM_cB@google.com>
On Wednesday, 8 April 2026 18:59:08 Central European Summer Time Dmitry Torokhov wrote:
> On Wed, Dec 17, 2025 at 07:34:40AM -0600, Rob Herring wrote:
> > On Wed, Dec 17, 2025 at 01:57:46PM +0100, Nicolas Frattaroli wrote:
> > > On Wednesday, 17 December 2025 09:31:15 Central European Standard Time Krzysztof Kozlowski wrote:
> > > > On Mon, Dec 15, 2025 at 01:29:29PM +0100, Nicolas Frattaroli wrote:
> > > > > adc-keys, unlike gpio-keys, does not allow linux,input-type as a valid
> > > > > property. This makes it impossible to model devices that have ADC inputs
> > > > > that should generate switch events.
> > > >
> > > > The solution is to use unevaluatedProps instead, which also allows
> > > > dropping other properties.
> > > >
> > > > Best regards,
> > > > Krzysztof
> > > >
> > > >
> > >
> > > Hi Krzysztof,
> > >
> > > to understand the motivation behind this suggestion correctly:
> > > are the "linux," vendor prefixed properties, especially with regards
> > > to key codes, generally a bit of a thorn in the side of DT bindings
> > > maintainers?
> >
> > Not really. Most have existed for decades. New ones get extra scrutiny
> > and often end up dropping the linux prefix.
> >
> > > I'd imagine so since they technically tie the DT to a specific OS
> > > kernel (though of course, others are free to translate those key
> > > codes). And the whole idea of configuring which code is emitted
> > > from something is basically abusing DT for configuring software
> > > rather than describing hardware.
> > >
> > > I'm mainly interested because this is a thought that has been in
> > > the back of my mind for a while now, and I'm curious if the DT
> > > binding maintainers happen to have arrived at the same impassé,
> > > where linux,input-type et al abuse the DT model for something we
> > > would tell any other vendor not to abuse it for, but no better
> > > solution exists right now to achieve the same thing.
> >
> > Not sure what the BSDs do here. It's never come up that I remember. Best
> > I can tell is they just make it a userspace problem. So every possible
> > keyboard needs a keymap file. Though I'm not sure how that would work
> > with GPIO keys as you don't really have a scan code.
>
> Is there an update for this binding or should I apply the current
> version? I am OK with the driver changes...
>
> Thanks.
>
>
I will send a new version that doesn't add the property but allows
unevaluatedProps instead. Thanks for reminding me.
Kind regards,
Nicolas Frattaroli
^ permalink raw reply
* Re: [PATCH v4 0/3] ath10k: Introduce a devicetree quirk to skip host cap QMI requests
From: Jeff Johnson @ 2026-04-08 17:15 UTC (permalink / raw)
To: Johannes Berg, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jeff Johnson, Bjorn Andersson, Konrad Dybcio, Paul Sajna,
David Heidelberg
Cc: Amit Pundir, linux-wireless, devicetree, ath10k, linux-kernel,
linux-arm-msm, phone-devel
In-Reply-To: <20260325-skip-host-cam-qmi-req-v4-0-bc08538487aa@ixit.cz>
On Wed, 25 Mar 2026 18:57:14 +0100, David Heidelberg wrote:
> This quirk is used so far used on:
> - LG G7 ThinQ
> - Xiaomi Poco F1
>
> I'm resending it after ~ 4 years since initial send due to Snapdragon
> 845 being one of best supported platform for mobile phones running
> Linux, so it would be shame to not have shiny support.
>
> [...]
Applied, thanks!
[1/3] dt-bindings: wireless: ath10k: Add quirk to skip host cap QMI requests
commit: 3d7640b6c371a1795e6d9580695d20caf16be9a4
[2/3] ath10k: Add device-tree quirk to skip host cap QMI requests
(no commit info)
[3/3] arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable ath10k host-cap skip quirk
(no commit info)
Best regards,
--
Jeff Johnson <jeff.johnson@oss.qualcomm.com>
^ permalink raw reply
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