* [PATCH v2 04/10] Introduce structured tag value definition
From: Herve Codina @ 2026-04-09 11:54 UTC (permalink / raw)
To: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Luca Ceresoli,
Thomas Petazzoni, Herve Codina
In-Reply-To: <20260409115426.352214-1-herve.codina@bootlin.com>
The goal of structured tag values is to ease the introduction of new
tags in future releases with the capability for an already existing
release to ignore those structured tags. In order to do that data length
related to the unknown tag needs to be identified.
Also add a flag to tell an old release if this tag can be simply skipped
or must lead to an error.
Structured tag value is defined on 32bit and is defined as follow:
Bits | 31 | 30 | 29 28 | 27 0|
------+----+-----------+-------------------+--------+
Fields| 1 | SKIP_SAFE | DATA_LEN_ENCODING | TAG_ID |
------+----+-----------+-------------------+--------+
Bit 31 is always set to 1 to identify a structured tag value.
Bit 30 (SKIP_SAFE) is set to 1 if the tag can be safely ignored when its
TAG_ID value is not a known value (unknown tag). If the SKIP_SAFE bit is
set to 0 this tag must not be ignored and an error should be reported
when its TAG_ID value is not a known value (unknown tag).
Bits 29..28 (DATA_LEN_ENCODING) indicates the length of the data related
to the tag. Following values are possible:
- 0b00: No data.
The tag is followed by the next tag value.
- 0b01: 1 cell data
The tag is followed by a 1 cell (u32) data. The next tag is
available after this cell.
- 0b10: 2 cells data
The tag is followed by a 2 cells (2 * u32) data. The next tag
is available after those two cells.
- 0b11: Data length encoding
The tag is followed by a cell (u32) indicating the size of the
data. This size is given in bytes. Data are available right
after this cell.
The next tag is available after the data. Padding is present
after the data in order to have the next tag aligned on 32bits.
This padding is not included in the size of the data.
Bits 27..0 (TAG_ID) is the tag identifier defining a specific tag.
Introduce the structured tag values definition and some specific tags
reserved for tests based on this structure definition.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
libfdt/fdt.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/libfdt/fdt.h b/libfdt/fdt.h
index a07abfc..e6f75e7 100644
--- a/libfdt/fdt.h
+++ b/libfdt/fdt.h
@@ -49,6 +49,7 @@ struct fdt_property {
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
#define FDT_TAGSIZE sizeof(fdt32_t)
+#define FDT_CELLSIZE sizeof(fdt32_t)
#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
#define FDT_END_NODE 0x2 /* End node */
@@ -57,6 +58,28 @@ struct fdt_property {
#define FDT_NOP 0x4 /* nop */
#define FDT_END 0x9
+/* Tag values flags */
+#define FDT_TAG_STRUCTURED (1<<31)
+#define FDT_TAG_SKIP_SAFE (1<<30)
+#define FDT_TAG_DATA_MASK (3<<28)
+#define FDT_TAG_DATA_NONE (0<<28)
+#define FDT_TAG_DATA_1CELL (1<<28)
+#define FDT_TAG_DATA_2CELLS (2<<28)
+#define FDT_TAG_DATA_VARLEN (3<<28)
+
+#define FDT_TAG_NO_SKIP(tag_data, tag_id) \
+ (FDT_TAG_STRUCTURED | tag_data | tag_id)
+
+#define FDT_TAG_CAN_SKIP(tag_data, tag_id) \
+ (FDT_TAG_STRUCTURED | FDT_TAG_SKIP_SAFE | tag_data | tag_id)
+
+/* Tests reserved tags */
+#define FDT_TEST_NONE_CAN_SKIP FDT_TAG_CAN_SKIP(FDT_TAG_DATA_NONE, 0)
+#define FDT_TEST_1CELL_CAN_SKIP FDT_TAG_CAN_SKIP(FDT_TAG_DATA_1CELL, 0)
+#define FDT_TEST_2CELLS_CAN_SKIP FDT_TAG_CAN_SKIP(FDT_TAG_DATA_2CELLS, 0)
+#define FDT_TEST_VARLEN_CAN_SKIP FDT_TAG_CAN_SKIP(FDT_TAG_DATA_VARLEN, 0)
+#define FDT_TEST_NONE_NO_SKIP FDT_TAG_NO_SKIP(FDT_TAG_DATA_NONE, 0)
+
#define FDT_V1_SIZE (7*sizeof(fdt32_t))
#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t))
#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t))
--
2.53.0
^ permalink raw reply related
* [PATCH v2 03/10] tests: asm: Introduce treehdr_vers macro
From: Herve Codina @ 2026-04-09 11:54 UTC (permalink / raw)
To: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Luca Ceresoli,
Thomas Petazzoni, Herve Codina
In-Reply-To: <20260409115426.352214-1-herve.codina@bootlin.com>
tree.S is used to generate custom dtbs. It uses the treehdr macro to
build the header part.
The current definition of this macro doesn't allow to set custom
settings related to version fields.
In order to easily generate some dtb with custom version values without
duplicating the full header computation, introduce the treehdr_vers
macro.
The modification doesn't introduce any functional changes.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
tests/trees.S | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tests/trees.S b/tests/trees.S
index d69f7f1..4db2b9b 100644
--- a/tests/trees.S
+++ b/tests/trees.S
@@ -8,7 +8,7 @@
.byte (\val) & 0xff
.endm
- .macro treehdr tree
+ .macro treehdr_vers tree vers last_comp_vers
.balign 8
.globl \tree
\tree :
@@ -17,13 +17,17 @@
fdtlong (\tree\()_struct - \tree)
fdtlong (\tree\()_strings - \tree)
fdtlong (\tree\()_rsvmap - \tree)
- fdtlong 0x11
- fdtlong 0x10
+ fdtlong \vers
+ fdtlong \last_comp_vers
fdtlong 0
fdtlong (\tree\()_strings_end - \tree\()_strings)
fdtlong (\tree\()_struct_end - \tree\()_struct)
.endm
+ .macro treehdr tree
+ treehdr_vers \tree 0x11 0x10
+ .endm
+
.macro rsvmape addrh, addrl, lenh, lenl
fdtlong \addrh
fdtlong \addrl
--
2.53.0
^ permalink raw reply related
* [PATCH v2 02/10] libfdt: Don't assume that a FDT_BEGIN_NODE tag is available at offset 0
From: Herve Codina @ 2026-04-09 11:54 UTC (permalink / raw)
To: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Luca Ceresoli,
Thomas Petazzoni, Herve Codina
In-Reply-To: <20260409115426.352214-1-herve.codina@bootlin.com>
In several places, libfdt assumes that a FDT_BEGIN_NODE tag is present
at the offset 0 of the structure block.
This assumption is not correct. Indeed, a FDT_NOP can be present at the
offset 0 and this is a legit case.
fdt_first_node() has been introduced recently to get the offset of the
first node (first FDT_BEGIN_NODE) in a fdt blob.
Use this function to get the first node offset instead of looking for
this node at offset 0.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
libfdt/fdt.c | 14 ++++++++++++--
libfdt/fdt_ro.c | 16 +++++++++++++---
libfdt/fdt_rw.c | 6 ++++++
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/libfdt/fdt.c b/libfdt/fdt.c
index 676c7d7..fb4faba 100644
--- a/libfdt/fdt.c
+++ b/libfdt/fdt.c
@@ -279,11 +279,21 @@ int fdt_first_node(const void *fdt)
int fdt_next_node(const void *fdt, int offset, int *depth)
{
- int nextoffset = 0;
+ int nextoffset = offset;
uint32_t tag;
+ /*
+ * Get the first node if asked for next node from the first node
+ * (offset == 0) or if the given offset is not valid (negative).
+ */
+ if (offset <= 0) {
+ nextoffset = fdt_first_node(fdt);
+ if (nextoffset < 0)
+ return nextoffset;
+ }
+
if (offset >= 0)
- if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0)
+ if ((nextoffset = fdt_check_node_offset_(fdt, nextoffset)) < 0)
return nextoffset;
do {
diff --git a/libfdt/fdt_ro.c b/libfdt/fdt_ro.c
index 63494fb..8e1db7d 100644
--- a/libfdt/fdt_ro.c
+++ b/libfdt/fdt_ro.c
@@ -229,6 +229,12 @@ int fdt_subnode_offset_namelen(const void *fdt, int offset,
FDT_RO_PROBE(fdt);
+ if (!offset) {
+ offset = fdt_first_node(fdt);
+ if (offset < 0)
+ return offset;
+ }
+
for (depth = 0;
(offset >= 0) && (depth >= 0);
offset = fdt_next_node(fdt, offset, &depth))
@@ -251,13 +257,17 @@ int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen)
{
const char *end = path + namelen;
const char *p = path;
- int offset = 0;
+ int offset;
FDT_RO_PROBE(fdt);
if (!can_assume(VALID_INPUT) && namelen <= 0)
return -FDT_ERR_BADPATH;
+ offset = fdt_first_node(fdt);
+ if (offset < 0)
+ return offset;
+
/* see if we have an alias */
if (*path != '/') {
const char *q = memchr(path, '/', end - p);
@@ -579,7 +589,7 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
if (buflen < 2)
return -FDT_ERR_NOSPACE;
- for (offset = 0, depth = 0;
+ for (offset = fdt_first_node(fdt), depth = 0;
(offset >= 0) && (offset <= nodeoffset);
offset = fdt_next_node(fdt, offset, &depth)) {
while (pdepth > depth) {
@@ -617,7 +627,7 @@ int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
else if (offset == -FDT_ERR_BADOFFSET)
return -FDT_ERR_BADSTRUCTURE;
- return offset; /* error from fdt_next_node() */
+ return offset; /* error from fdt_next_node() or fdt_first_node() */
}
int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
diff --git a/libfdt/fdt_rw.c b/libfdt/fdt_rw.c
index 90ea14e..f5c28fc 100644
--- a/libfdt/fdt_rw.c
+++ b/libfdt/fdt_rw.c
@@ -354,6 +354,12 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset,
FDT_RW_PROBE(fdt);
+ if (!parentoffset) {
+ parentoffset = fdt_first_node(fdt);
+ if (parentoffset < 0)
+ return parentoffset;
+ }
+
offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
if (offset >= 0)
return -FDT_ERR_EXISTS;
--
2.53.0
^ permalink raw reply related
* [PATCH v2 01/10] libfdt: Introduce fdt_first_node()
From: Herve Codina @ 2026-04-09 11:54 UTC (permalink / raw)
To: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Luca Ceresoli,
Thomas Petazzoni, Herve Codina
In-Reply-To: <20260409115426.352214-1-herve.codina@bootlin.com>
In several places, libfdt assumes that a FDT_BEGIN_NODE tag is present
at the offset 0 of the structure block.
This assumption is not correct. Indeed, a FDT_NOP can be present at the
offset 0 and this is a legit case.
Indeed, the device-tree specification [0] defines the FDT_NOP tag as
follow:
The FDT_NOP token will be ignored by any program parsing the device
tree. This token has no extra data; so it is followed immediately by
the next token, which can be any valid token. A property or node
definition in the tree can be overwritten with FDT_NOP tokens to
remove it from the tree without needing to move other sections of
the tree’s representation in the devicetree blob.
Nothing refers to any location for this tag and it has to be simply
ignored. Having this tag at offset 0 doesn't make an exception, the tag
has to be ignored.
Introduce fdt_first_node() in order to get the offset of the first node
(first FDT_BEGIN_NODE tag) available in a fdt blob taking care of
FDT_NOP tags.
[0] https://github.com/devicetree-org/devicetree-specification/blob/main/source/chapter5-flattened-format.rst?plain=1#L317
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
libfdt/fdt.c | 25 +++++++++++++++++++++++++
libfdt/libfdt_internal.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/libfdt/fdt.c b/libfdt/fdt.c
index 56d4dcb..676c7d7 100644
--- a/libfdt/fdt.c
+++ b/libfdt/fdt.c
@@ -252,6 +252,31 @@ int fdt_check_prop_offset_(const void *fdt, int offset)
return offset;
}
+int fdt_first_node(const void *fdt)
+{
+ int nextoffset = 0;
+ int offset;
+ uint32_t tag;
+
+ do {
+ offset = nextoffset;
+ tag = fdt_next_tag(fdt, offset, &nextoffset);
+ switch (tag) {
+ case FDT_END_NODE:
+ case FDT_PROP:
+ return -FDT_ERR_BADSTRUCTURE;
+
+ case FDT_BEGIN_NODE:
+ return offset;
+
+ default:
+ break;
+ }
+ } while (tag != FDT_END);
+
+ return (nextoffset < 0) ? nextoffset : -FDT_ERR_NOTFOUND;
+}
+
int fdt_next_node(const void *fdt, int offset, int *depth)
{
int nextoffset = 0;
diff --git a/libfdt/libfdt_internal.h b/libfdt/libfdt_internal.h
index 0e103ca..4c15264 100644
--- a/libfdt/libfdt_internal.h
+++ b/libfdt/libfdt_internal.h
@@ -32,6 +32,7 @@ static inline const char *fdt_find_string_(const char *strtab, int tabsize,
}
int fdt_node_end_offset_(void *fdt, int nodeoffset);
+int fdt_first_node(const void *fdt);
static inline const void *fdt_offset_ptr_(const void *fdt, int offset)
{
--
2.53.0
^ permalink raw reply related
* [PATCH v2 00/10] Add support for structured tags and v18 dtb version
From: Herve Codina @ 2026-04-09 11:54 UTC (permalink / raw)
To: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Luca Ceresoli,
Thomas Petazzoni, Herve Codina
Recently, I sent a RFC series related to support for metadata and addon
device-trees [1].
During the discussion the concept of structured tags and "unknown" tags
emerged as well as the need to have them handled as a prerequisite of
support for metadata and addon.
The conclusion was the need for a new dtb version (v18) with support
for:
- Structured tags and based on them, "unknown" tags.
Those structured tags allow to have an standardized definition of
tags with the capability of skipping a tag and its related data
when a "unknown" tag is incountered by a given version of libfdt,
dtc and tools. Those "unknown" tags are tags defined in future
versions. Even if they exact meaning is unknown for an 'old'
version, they structure is understood and the 'old' version can skip
them without any errors if allowed.
- Flags in the dtb header (dt_flags).
The goal of this field is to have a placeholder to specify the
type of dtb we are dealing with. For instance, addons dtb will set a
flag in this placeholder
- A last compatible version for writing purpose.
The goal of the new dtb header field (last_comp_version_w) is to
disable globally any modification. It works similarly to
last_comp_version but for modification. It can be used to avoid any
modification that could be done by an 'old' version and could lead
to inconsistencies between the modification itself and some
"unknown" tags.
This current series implements those features and leads to the v18 dtb
version.
First patches (patches from 1 to 3) are patches fixing issues or
preparation patches. IMHO, those patches could be taken even if other
patches in the series lead to discussions.
Patch 4 introduces the structured tags. The patch gives definitions
needed to handle those tags.
Patches 5, 6 and 7 handles "unknown" tags in fdtdump, dtc and libfdt.
This is the reading part implementation related to "unknown" tags in
tools and lib.
Patch 8 is a preparation commit for patch 9 and patch 9 itself is
handling modifications (writing part) when unknown tags are involved.
The last patch (patch 10) bumps the dtb version including changes that
cannot be moved out of the version bump without having a v18 without all
expected features.
Also, several tests are added as soon as the related feature is
supported. Those tests are part of the last commit adding the feature.
As already said, this current series is a prerequisite to the support
for metadata and addons. The RFC series related to metadata and addons
[1] will be rebased on top of this prerequisite. Please, keep that in
mind for the review of this current prerequisite series.
[1] https://lore.kernel.org/all/20260112142009.1006236-1-herve.codina@bootlin.com/
This v2 iteration is the continuation of the first (RFC) iteration. It
mainly removes patches already applied and takes into account feedback
received from Luca during the first iteration.
Best regards,
Hervé
Changes:
v1 -> v2
v1: https://lore.kernel.org/devicetree-compiler/20260316171640.6fb0d952@bootlin.com/T/#t
Rebase on top of the last master branch of the dtc repository.
Remove the RFC tag.
- Patches 1, 2, 3, 4 and 7 in v1: Removed
Already applied.
- Patch 1 (5 in v1)
Update the commit log.
- Patch 2 (6 in v1)
Fix a typo in the commit log.
Add a comment related to 'offset <= 0' in fdt_next_node().
- Patch 3 (8 in v1)
No change
- Patch 4 (9 in v1)
Fix typos in commit log.
Replace DATA_LNG_ENCODING by DATA_LEN_ENCODING in commit log.
Use SKIP_SAFE instead of CAN_SKIP in commit log.
Rename FDT_TAG_DATA_LNG to FDT_TAG_DATA_VARLEN in tags definition.
Rename FDT_TEST_LNG_CAN_SKIP to FDT_TEST_VARLEN_CAN_SKIP.
- Patch 5 (10 in v1)
Use FDT_TAG_DATA_VARLEN instead of FDT_TAG_DATA_LNG.
Use FDT_TEST_VARLEN_CAN_SKIP instead of FDT_TEST_LNG_CAN_SKIP.
Update values used in the unknown_tags_can_skip dtb test file.
Use 'len' instead of 'lng'
Update the '-uu' option help message.
Update the fdtdump test to be stricter (avoid removing some specific
comments related to unknown tags in sed command used in the test).
- Patch 6 (11 in v1)
Use FDT_TAG_DATA_VARLEN instead of FDT_TAG_DATA_LNG.
Update the dtc test due to unknown_tags_can_skip dtb changes.
Add 'Reviewed-by: Luca Ceresoli'
- Patch 7 (12 in v1)
Replace fdt_get_next() by fdt_next_tag() in commit title and log.
Fix a typo in commit log.
Use FDT_TAG_DATA_VARLEN instead of FDT_TAG_DATA_LNG.
Update the fdtget test due to unknown_tags_can_skip dtb changes.
Add 'Reviewed-by: Luca Ceresoli'
- Patch 8 (13 in v1)
Fix commit log.
Add 'Reviewed-by: Luca Ceresoli'
- Patch 9 (14 in v1)
Update the fdtput test due to unknown_tags_can_skip dtb and
fdtdump changes.
Add a missing ')' in commit log
Add 'Reviewed-by: Luca Ceresoli'
- Patch 10 (15 in v1)
Fix typos and clarify several parts of the commit log.
Herve Codina (10):
libfdt: Introduce fdt_first_node()
libfdt: Don't assume that a FDT_BEGIN_NODE tag is available at offset
0
tests: asm: Introduce treehdr_vers macro
Introduce structured tag value definition
fdtdump: Handle unknown tags
flattree: Handle unknown tags
libfdt: Handle unknown tags in fdt_next_tag()
libfdt: Introduce fdt_ptr_offset_
libfdt: Handle unknown tags on dtb modifications
Introduce v18 dtb version
dtc.h | 2 +-
fdtdump.c | 53 ++++++-
flattree.c | 102 ++++++++++--
libfdt/fdt.c | 114 +++++++++++++-
libfdt/fdt.h | 28 ++++
libfdt/fdt_ro.c | 16 +-
libfdt/fdt_rw.c | 144 ++++++++++++++++-
libfdt/fdt_sw.c | 3 +
libfdt/libfdt.h | 7 +-
libfdt/libfdt_internal.h | 9 ++
pylibfdt/libfdt.i | 18 +++
tests/dumptrees.c | 5 +-
tests/pylibfdt_tests.py | 10 +-
tests/run_tests.sh | 115 +++++++++++++-
tests/testdata.h | 3 +
tests/testutils.c | 2 +-
tests/trees.S | 149 +++++++++++++++++-
tests/unknown_tags_can_skip.dtb.dts.expect | 19 +++
tests/unknown_tags_can_skip.dtb.expect | 29 ++++
...own_tags_can_skip.fdtput.test.dtb.0.expect | 32 ++++
...own_tags_can_skip.fdtput.test.dtb.1.expect | 36 +++++
...own_tags_can_skip.fdtput.test.dtb.2.expect | 34 ++++
...own_tags_can_skip.fdtput.test.dtb.3.expect | 36 +++++
...own_tags_can_skip.fdtput.test.dtb.4.expect | 35 ++++
...own_tags_can_skip.fdtput.test.dtb.5.expect | 33 ++++
...own_tags_can_skip.fdtput.test.dtb.6.expect | 28 ++++
26 files changed, 1020 insertions(+), 42 deletions(-)
create mode 100644 tests/unknown_tags_can_skip.dtb.dts.expect
create mode 100644 tests/unknown_tags_can_skip.dtb.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.0.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.1.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.2.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.3.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.4.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.5.expect
create mode 100644 tests/unknown_tags_can_skip.fdtput.test.dtb.6.expect
--
2.53.0
^ permalink raw reply
* Re: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Joe Sandom @ 2026-04-09 11:46 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <lusy4sd2q22tvtvzgbb3pbpxauy5ym46ojjtpjq43wyzn72yxy@uxcggqladbnl>
On Thu, Apr 09, 2026 at 04:56:06PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Apr 09, 2026 at 11:04:55AM +0100, Joe Sandom wrote:
> > On Tue, Apr 07, 2026 at 09:44:34PM +0530, Manivannan Sadhasivam wrote:
> > > On Tue, Apr 07, 2026 at 12:39:25PM +0100, Joe Sandom wrote:
> > >
> > > [...]
> > >
> > > > > > +&pcie0 {
> > > > > > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> > > > > > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> > > > > > +
> > > > > > + pinctrl-0 = <&pcie0_default_state>;
> > > > > > + pinctrl-names = "default";
> > > > > > +
> > > > > > + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> > > > > > + <0x100 &apps_smmu 0x1401 0x1>,
> > > > > > + <0x208 &apps_smmu 0x1402 0x1>,
> > > > > > + <0x210 &apps_smmu 0x1403 0x1>,
> > > > > > + <0x218 &apps_smmu 0x1404 0x1>,
> > > > > > + <0x300 &apps_smmu 0x1407 0x1>,
> > > > > > + <0x400 &apps_smmu 0x1408 0x1>,
> > > > > > + <0x500 &apps_smmu 0x140c 0x1>,
> > > > > > + <0x501 &apps_smmu 0x140e 0x1>;
> > > > > > +
> > > > > > + /delete-property/ msi-map;
> > > > >
> > > > > Why?
> > > > I tried extending the msi-map to cover the RIDs from the QPS615
> > > > PCIe switch (matching the iommu-map entries), but this caused
> > > > ITS MAPD command timeouts.
> > >
> > > I'm not aware of any specific issue with ITS on this chipset. At what time did
> > > you see the timeout? During probe?
> > So when I set msi-map to match the iommu-map entries, I got this;
> > [ 0.000000] ITS [mem 0x17140000-0x1717ffff]
> > [ 11.085152] ath12k_wifi7_pci 0001:04:00.0: BAR 0 assigned
> > [ 11.115762] ath12k_wifi7_pci 0001:04:00.0: Wi-Fi 7 Hardware name: wcn7850 hw2.0
> > [ 11.153632] ath12k_wifi7_pci 0001:04:00.0: MSI vectors: 16
> > [ 11.252398] mhi mhi0: Requested to power ON
> > .........
> > [ 101.596274] mhi mhi0: Wait for device to enter SBL or Mission mode
> > [ 101.603098] ath12k_wifi7_pci 0001:04:00.0: failed to set mhi state: POWER_ON(2)
> > [ 101.610632] ath12k_wifi7_pci 0001:04:00.0: failed to start mhi: -110
> > [ 101.617171] ath12k_wifi7_pci 0001:04:00.0: failed to power up :-110
> > [ 101.794431] ath12k_wifi7_pci 0001:04:00.0: probe failed with error -110
> > [ 103.158872] ITS queue timeout (12640 12609)
> > [ 103.163183] ITS cmd its_build_mapd_cmd failed
> >
> > With msi-map removed, I got this;
> > [ 11.469642] ath12k_wifi7_pci 0001:04:00.0: BAR 0 assigned
> > [ 11.490059] ath12k_wifi7_pci 0001:04:00.0: Wi-Fi 7 Hardware name: wcn7850 hw2.0
> > [ 11.497787] ath12k_wifi7_pci 0001:04:00.0: MSI vectors: 16
> > [ 11.559958] mhi mhi0: Requested to power ON
> > [ 11.567375] mhi mhi0: Power on setup success
> > [ 11.693069] mhi mhi0: Wait for device to enter SBL or Mission mode
> > [ 12.185946] ath12k_wifi7_pci 0001:04:00.0: chip_id 0x2 ... soc_id 0x40170200
> > [ 12.482168] ath12k_wifi7_pci 0001:04:00.0 wlP1p4s0: renamed from wlan0
>
> Thanks for the logs. I also checked internally and learned that the timeout is
> due to Gunyah limiting the devices per-port. On SM8550, it currently only
> allows 2 devices per RC instance to save the memory footprint. So when you
> connect a PCIe switch which exposes more than two devices (1 USP + (1+) DSPs),
> you'll run out of ITS mapping in Gunyah, leading to these timeouts.
>
> So either you need to modify Gunyah to allow more devices per-port or switch to
> iMSI-RX which you are already doing.
>
Makes sense! Thanks for checking Mani, good to get to the bottom of that.
I'll leave it as is for now and will look into modifying Gunyah
separately.
In v3 I'll update the commit message to reflect your findings
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
Thanks,
Joe
^ permalink raw reply
* [PATCH v8 5/5] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes
From: Abhinaba Rakshit @ 2026-04-09 11:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Neeraj Soni, Harshal Dev, Kuldeep Singh, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
In-Reply-To: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com>
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.
Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco
platform.
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 487bb682ae8620b819f022162edd11023ed07be8..cb0e554e94d237b0adccb55fa9ed967bae9eea05 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2730,6 +2730,22 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-201600000 {
+ opp-hz = /bits/ 64 <201600000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
crypto: crypto@1dfa000 {
@@ -4797,6 +4813,22 @@ sdhc_ice: crypto@87c8000 {
clock-names = "core",
"iface";
power-domains = <&rpmhpd RPMHPD_CX>;
+
+ operating-points-v2 = <&ice_mmc_opp_table>;
+
+ ice_mmc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
usb_1_hsphy: phy@8904000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v8 4/5] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes
From: Abhinaba Rakshit @ 2026-04-09 11:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Neeraj Soni, Harshal Dev, Kuldeep Singh, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
In-Reply-To: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com>
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.
Add OPP-table for ICE UFS and ICE eMMC device nodes for Kodiak
platform.
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 42 ++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index c899a17026fd2a10ebc528a816629c88ee3bde5d..b0aa1970d42a3bb0b9d371e0e6cd09b8cd164dbe 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1087,6 +1087,27 @@ sdhc_ice: crypto@7c8000 {
clock-names = "core",
"iface";
power-domains = <&rpmhpd SC7280_CX>;
+
+ operating-points-v2 = <&ice_mmc_opp_table>;
+
+ ice_mmc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
gpi_dma0: dma-controller@900000 {
@@ -2597,6 +2618,27 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
cryptobam: dma-controller@1dc4000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v8 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
From: Abhinaba Rakshit @ 2026-04-09 11:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Neeraj Soni, Harshal Dev, Kuldeep Singh, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit, Konrad Dybcio
In-Reply-To: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com>
MMC controller lacks a clock scaling mechanism, unlike the UFS
controller. By default, the MMC controller is set to TURBO mode
during probe, but the ICE clock remains at XO frequency,
leading to read/write performance degradation on eMMC.
To address this, set the ICE clock to TURBO during sdhci_msm_ice_init
to align it with the controller clock. This ensures consistent
performance and avoids mismatches between the controller
and ICE clock frequencies.
For platforms where ICE is represented as a separate device,
use the OPP framework to vote for TURBO mode, maintaining
proper voltage and power domain constraints.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/mmc/host/sdhci-msm.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index da356627d9de6a11ed5779bf057fa8eb23c38bc0..32e3f37fe425f66c00290a373e06e8ab6257824e 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1901,6 +1901,8 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
#ifdef CONFIG_MMC_CRYPTO
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
+static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
+ bool round_ceil); /* forward decl */
static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
struct cqhci_host *cq_host)
@@ -1964,6 +1966,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
}
mmc->caps2 |= MMC_CAP2_CRYPTO;
+
+ err = sdhci_msm_ice_scale_clk(msm_host, INT_MAX, false);
+ if (err && err != -EOPNOTSUPP)
+ dev_warn(dev, "Unable to boost ICE clock to TURBO\n");
+
return 0;
}
@@ -1989,6 +1996,16 @@ static int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
return 0;
}
+static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host,
+ unsigned long target_freq,
+ bool round_ceil)
+{
+ if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
+ return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil);
+
+ return 0;
+}
+
static inline struct sdhci_msm_host *
sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
{
@@ -2114,6 +2131,13 @@ sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
{
return 0;
}
+
+static inline int
+sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
+ bool round_ceil)
+{
+ return 0;
+}
#endif /* !CONFIG_MMC_CRYPTO */
/*****************************************************************************\
--
2.34.1
^ permalink raw reply related
* [PATCH v8 2/5] ufs: host: Add ICE clock scaling during UFS clock changes
From: Abhinaba Rakshit @ 2026-04-09 11:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Neeraj Soni, Harshal Dev, Kuldeep Singh, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
In-Reply-To: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com>
Implement ICE (Inline Crypto Engine) clock scaling in sync with
UFS controller clock scaling. This ensures that the ICE operates at
an appropriate frequency when the UFS clocks are scaled up or down,
improving performance and maintaining stability for crypto operations.
For scale_up operation ensure to pass ~round_ceil (round_floor)
and vice-versa for scale_down operations.
Incase of OPP scaling is not supported by ICE, ensure to not prevent
devfreq for UFS, as ICE OPP-table is optional.
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/ufs/host/ufs-qcom.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 375fd24ba458a7ef65d075ba98e5f99f4aa977c1..aceb2c42969b5d2dcddcddf0167f8824733998ec 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -306,6 +306,15 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile,
return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key);
}
+static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
+ bool round_ceil)
+{
+ if (host->hba->caps & UFSHCD_CAP_CRYPTO)
+ return qcom_ice_scale_clk(host->ice, target_freq, round_ceil);
+
+ return 0;
+}
+
static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
.keyslot_program = ufs_qcom_ice_keyslot_program,
.keyslot_evict = ufs_qcom_ice_keyslot_evict,
@@ -340,6 +349,12 @@ static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
{
}
+static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
+ bool round_ceil)
+{
+ return 0;
+}
+
#endif
static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
@@ -1743,12 +1758,17 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
else
err = ufs_qcom_clk_scale_down_post_change(hba, target_freq);
-
if (err) {
ufshcd_uic_hibern8_exit(hba);
return err;
}
+ err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up);
+ if (err && err != -EOPNOTSUPP) {
+ ufshcd_uic_hibern8_exit(hba);
+ return err;
+ }
+
ufs_qcom_icc_update_bw(host);
ufshcd_uic_hibern8_exit(hba);
}
--
2.34.1
^ permalink raw reply related
* [PATCH v8 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE
From: Abhinaba Rakshit @ 2026-04-09 11:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Neeraj Soni, Harshal Dev, Kuldeep Singh, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
In-Reply-To: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com>
Register optional operation-points-v2 table for ICE device
during device probe. Attach the OPP-table with only the ICE
core clock. Since, dtbinding is on a trasition phase to include
iface clock and clock-names, attaching the opp-table to core clock
remains options such that it does not cause probe failures.
Introduce clock scaling API qcom_ice_scale_clk which scale ICE
core clock based on the target frequency provided and if a valid
OPP-table is registered. Use round_ceil passed to decide on the
rounding of the clock freq against OPP-table. Clock scaling is
disabled when a valid OPP-table is not registered.
This ensures when an ICE-device specific OPP table is available,
use the PM OPP framework to manage frequency scaling and maintain
proper power-domain constraints.
Also, ensure to drop the votes in suspend to prevent power/thermal
retention. Subsequently restore the frequency in resume from
core_clk_freq which stores the last ICE core clock operating frequency.
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/soc/qcom/ice.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/soc/qcom/ice.h | 2 ++
2 files changed, 94 insertions(+)
diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index bf4ab2d9e5c0360d8fe6135cc35f93b6b09e7a0e..9e869e6abc6300c7608b4d9a18e7f3e80c93f5e7 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -16,6 +16,7 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
#include <linux/firmware/qcom/qcom_scm.h>
@@ -112,6 +113,8 @@ struct qcom_ice {
bool use_hwkm;
bool hwkm_init_complete;
u8 hwkm_version;
+ unsigned long core_clk_freq;
+ bool has_opp;
};
static bool qcom_ice_check_supported(struct qcom_ice *ice)
@@ -311,6 +314,10 @@ int qcom_ice_resume(struct qcom_ice *ice)
struct device *dev = ice->dev;
int err;
+ /* Restore the ICE core clk freq */
+ if (ice->has_opp && ice->core_clk_freq)
+ dev_pm_opp_set_rate(ice->dev, ice->core_clk_freq);
+
err = clk_prepare_enable(ice->core_clk);
if (err) {
dev_err(dev, "Failed to enable core clock: %d\n", err);
@@ -331,6 +338,11 @@ int qcom_ice_suspend(struct qcom_ice *ice)
{
clk_disable_unprepare(ice->iface_clk);
clk_disable_unprepare(ice->core_clk);
+
+ /* Drop the clock votes while suspend */
+ if (ice->has_opp)
+ dev_pm_opp_set_rate(ice->dev, 0);
+
ice->hwkm_init_complete = false;
return 0;
@@ -556,6 +568,51 @@ int qcom_ice_import_key(struct qcom_ice *ice,
}
EXPORT_SYMBOL_GPL(qcom_ice_import_key);
+/**
+ * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations
+ * @ice: ICE driver data
+ * @target_freq: requested frequency in Hz
+ * @round_ceil: when true, selects nearest freq >= @target_freq;
+ * otherwise, selects nearest freq <= @target_freq
+ *
+ * Selects an OPP frequency based on @target_freq and the rounding direction
+ * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(),
+ * including any voltage or power-domain transitions handled by the OPP
+ * framework. Updates ice->core_clk_freq on success.
+ *
+ * Return: 0 on success; -EOPNOTSUPP if no OPP table; or error from
+ * dev_pm_opp_set_rate()/OPP lookup.
+ */
+int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
+ bool round_ceil)
+{
+ unsigned long ice_freq = target_freq;
+ struct dev_pm_opp *opp;
+ int ret;
+
+ if (!ice->has_opp)
+ return -EOPNOTSUPP;
+
+ if (round_ceil)
+ opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq);
+ else
+ opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq);
+
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+ dev_pm_opp_put(opp);
+
+ ret = dev_pm_opp_set_rate(ice->dev, ice_freq);
+ if (ret) {
+ dev_err(ice->dev, "Unable to scale ICE clock rate\n");
+ return ret;
+ }
+ ice->core_clk_freq = ice_freq;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(qcom_ice_scale_clk);
+
static struct qcom_ice *qcom_ice_create(struct device *dev,
void __iomem *base)
{
@@ -731,6 +788,7 @@ static int qcom_ice_probe(struct platform_device *pdev)
{
struct qcom_ice *engine;
void __iomem *base;
+ int err;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
@@ -742,6 +800,40 @@ static int qcom_ice_probe(struct platform_device *pdev)
if (IS_ERR(engine))
return PTR_ERR(engine);
+ /* qcom_ice_create() may return NULL if scm calls are not available */
+ if (!engine)
+ return -EOPNOTSUPP;
+
+ err = devm_pm_opp_set_clkname(&pdev->dev, "core");
+ if (err && err != -ENOENT) {
+ dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n");
+ return err;
+ }
+
+ /* OPP table is optional */
+ err = devm_pm_opp_of_add_table(&pdev->dev);
+ if (err && err != -ENODEV) {
+ dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
+ return err;
+ }
+
+ /*
+ * The OPP table is optional. devm_pm_opp_of_add_table() returns
+ * -ENODEV when no OPP table is present in DT, which is not treated
+ * as an error. Therefore, track successful OPP registration only
+ * when the return value is 0.
+ */
+ engine->has_opp = (err == 0);
+ if (!engine->has_opp)
+ dev_info(&pdev->dev, "ICE OPP table is not registered, please update your DT\n");
+
+ /*
+ * Store the core clock rate for suspend resume cycles,
+ * against OPP aware DVFS operations. core_clk_freq will
+ * have a valid value only for non-legacy bindings.
+ */
+ engine->core_clk_freq = clk_get_rate(engine->core_clk);
+
platform_set_drvdata(pdev, engine);
return 0;
diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h
index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..4eb58a264d416e71228ed4b13e7f53c549261fdc 100644
--- a/include/soc/qcom/ice.h
+++ b/include/soc/qcom/ice.h
@@ -30,5 +30,7 @@ int qcom_ice_import_key(struct qcom_ice *ice,
const u8 *raw_key, size_t raw_key_size,
u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
struct qcom_ice *devm_of_qcom_ice_get(struct device *dev);
+int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
+ bool round_ceil);
#endif /* __QCOM_ICE_H__ */
--
2.34.1
^ permalink raw reply related
* [PATCH v8 0/5] Enable ICE clock scaling
From: Abhinaba Rakshit @ 2026-04-09 11:44 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Neeraj Soni, Harshal Dev, Kuldeep Singh, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit, Konrad Dybcio
Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine)
using the OPP framework. During ICE device probe, the driver now attempts to
parse an optional OPP table from the ICE-specific device tree node for
DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver
and is invoked by UFS host controller driver in response to clock scaling
requests, ensuring coordination between ICE and host controller.
For MMC controllers that do not support clock scaling, the ICE clock frequency
is kept aligned with the MMC controller’s clock rate (TURBO) to ensure
consistent operation.
Dynamic clock scaling based on OPP tables enables better power-performance
trade-offs. By adjusting ICE clock frequencies according to workload and power
constraints, the system can achieve higher throughput when needed and
reduce power consumption during idle or low-load conditions.
The OPP table remains optional, absence of the table will not cause
probe failure. However, in the absence of an OPP table, ICE clocks will
remain at their default rates, which may limit performance under
high-load scenarios or prevent performance optimizations during idle periods.
Testing:
* dtbs_check
* Validated on Rb3Gen2 and qcs8300-ride-sx
Merge Order and Dependencies
============================
Patch 2 is dependent on patch 1 for the qcom_ice_scale_clk API to be available.
Patch 3 is dependent on patch 1 for the qcom_ice_scale_clk API to be available.
Due to dependency, all patches should go through Qcom SoC tree.
This patchset supersedes earlier ICE clock scaling series (v1–v7) with updated dependencies.
Hence, this patchset also *Depends-On* the following patchseries:
[1] Add explicit clock vote and enable power-domain for QCOM-ICE
https://lore.kernel.org/linux-arm-msm/20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com
[2] Enable Inline crypto engine for kodiak and monaco
https://lore.kernel.org/lkml/20260310113557.348502-1-neeraj.soni@oss.qualcomm.com/
[3] Enable iface clock and power domain for kodiak and monaco ice sdhc
https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
Changes in v8:
- Instead of scaling to TURBO in ICE probe, sdhci_msm_ice_init calls qcom_ice_scale_clk for setting freq to max.
- Fix error handling in qcom_ice_scale_clk.
- Fix error handling in ufs_qcom_clk_scale_notify for the call to qcom_ice_scale_clk.
- Move the registering of OPP-table to qcom_ice_probe and remove passing legacy_bindings argument to qcom_ice_create.
- Add OPP-table for kodiak and monaco ICE eMMC and UFS device nodes.
- Link to v7: https://lore.kernel.org/r/20260302-enable-ufs-ice-clock-scaling-v7-0-669b96ecadd8@oss.qualcomm.com
Changes in v7:
- Replace the custom rounding flags with 'bool round_ceil' as suggested.
- Update the dev_info log-line.
- Dropped dt-bindings patch (already applied by in previous patchseries).
- Add merge order and dependencies as suggested.
- Link to v6: https://lore.kernel.org/r/20260219-enable-ufs-ice-clock-scaling-v6-0-0c5245117d45@oss.qualcomm.com
Changes in v6:
- Remove scale_up parameter from qcom_ice_scale_clk API.
- Remove having max_freq and min_freq as the checks for overclocking and underclocking is no-longer needed.
- UFS driver passes rounding flags depending on scale_up value.
- Ensure UFS driver does not fail devfreq requests if ICE OPP is not supported.
- Link to v5: https://lore.kernel.org/all/20260211-enable-ufs-ice-clock-scaling-v5-0-221c520a1f2e@oss.qualcomm.com/
Changes in v5:
- Update operating-points-v2 property in dtbindings as suggested.
- Fix comment styles.
- Add argument in qcom_ice_create to distinguish between legacy bindings and newer bindings.
- Ensure to drop votes in suspend and enable the last vote in resume.
- Link to v4: https://lore.kernel.org/r/20260128-enable-ufs-ice-clock-scaling-v4-0-260141e8fce6@oss.qualcomm.com
Changes in v4:
- Enable multiple frequency scaling based OPP-entries as suggested in v3 patchset.
- Include bindings change: https://lore.kernel.org/all/20260123-add-operating-points-v2-property-for-qcom-ice-bindings-v1-1-2155f7aacc28@oss.qualcomm.com/.
- Link to v3: https://lore.kernel.org/r/20260123-enable-ufs-ice-clock-scaling-v3-0-d0d8532abd98@oss.qualcomm.com
Changes in v3:
- Avoid clock scaling in case of legacy bindings as suggested.
- Use of_device_is_compatible to distinguish between legacy and non-legacy bindings.
- Link to v2: https://lore.kernel.org/r/20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com
Changes in v2:
- Use OPP-table instead of freq-table-hz for clock scaling.
- Enable clock scaling for legacy targets as well, by fetching frequencies from storage opp-table.
- Introduce has_opp variable in qcom_ice structure to keep track, if ICE instance has dedicated OPP-table registered.
- Combined the changes for patch-series <20251001-set-ice-clock-to-turbo-v1-1-7b802cf61dda@oss.qualcomm.com> as suggested.
- Link to v1: https://lore.kernel.org/r/20251001-enable-ufs-ice-clock-scaling-v1-0-ec956160b696@oss.qualcomm.com
---
Abhinaba Rakshit (5):
soc: qcom: ice: Add OPP-based clock scaling support for ICE
ufs: host: Add ICE clock scaling during UFS clock changes
mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes
arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes
arch/arm64/boot/dts/qcom/kodiak.dtsi | 42 ++++++++++++++++
arch/arm64/boot/dts/qcom/monaco.dtsi | 32 +++++++++++++
drivers/mmc/host/sdhci-msm.c | 24 ++++++++++
drivers/soc/qcom/ice.c | 92 ++++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-qcom.c | 22 ++++++++-
include/soc/qcom/ice.h | 2 +
6 files changed, 213 insertions(+), 1 deletion(-)
---
base-commit: 95c541ddfb0815a0ea8477af778bb13bb075079a
change-id: 20260408-enable-ice-clock-scaling-5ca54ed63179
prerequisite-message-id: <20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com>
prerequisite-patch-id: 1750aded4cac0105fbf943c5bfd9f844acf4f227
prerequisite-patch-id: 8cf945709b92296c73859515bb67820360d785a2
prerequisite-patch-id: bc8821cbbe222f208c5d86d96f3640c169b972d6
prerequisite-patch-id: a1baf04d3cce803fcb47b1a80591bf7759de8a76
prerequisite-patch-id: b7de0f216e54e264e054f6333b3067abce8d05c5
prerequisite-patch-id: 57f21e8a9505564caebbf89cafa9bd80be1dfe9f
prerequisite-patch-id: 5128586130e3f5847e0417de47ef755b2e2fba93
prerequisite-patch-id: fa46b7d6710907c5eb5ad01e84d28f09a0b26e5a
prerequisite-patch-id: e375d6e54a55c055f5d8673c65d35073df396646
prerequisite-patch-id: ec670d98300863c4b68155a3b0feeace56a4a55a
prerequisite-patch-id: c5ee690afd7f7105963e991dff760de62a403d9b
prerequisite-message-id: <20260310113557.348502-1-neeraj.soni@oss.qualcomm.com>
prerequisite-patch-id: ab9cc8bd28b2e1e27df6e44907e8d758dfeee3df
prerequisite-patch-id: 40f239f7f06573ed45452249f444e54e3565ada7
prerequisite-patch-id: 59129ed0aeba84f6b50f42261d51fe323806a240
prerequisite-message-id: <20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com>
prerequisite-patch-id: 5b6a436bd949a93e44f912d2565103f6bf0ef55a
prerequisite-patch-id: 7f9ff2b708418a77578e154102f72f0da243eb71
Best regards,
--
Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
From: Joe Sandom @ 2026-04-09 11:41 UTC (permalink / raw)
To: Neil Armstrong
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <8ed5aeb8-98fb-4b87-a6a9-983e4fa91db5@linaro.org>
On Tue, Apr 07, 2026 at 07:38:54PM +0200, Neil Armstrong wrote:
> On 4/7/26 17:46, Joe Sandom wrote:
> > Add the MHI register regions to the pcie0 and pcie1 controller nodes
> > so that the MHI bus layer can access controller registers directly.
>
> Can you elaborate more on that ? Looking at the current implementation,
> the pcie host driver only uses the mhi memory zone to show the transition
> count in debugfs.
>
hmm yeah, you're right. As you said, it's only used for transition count
currently. I'll make sure the commit message is clearer in v3.
> Neil
>
> >
> > Signed-off-by: Joe Sandom <jsandom@axon.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++----
> > 1 file changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..055ca931c04859f3a312eb9921aeb7a8cc676822 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -1964,8 +1964,14 @@ pcie0: pcie@1c00000 {
> > <0 0x60000000 0 0xf1d>,
> > <0 0x60000f20 0 0xa8>,
> > <0 0x60001000 0 0x1000>,
> > - <0 0x60100000 0 0x100000>;
> > - reg-names = "parf", "dbi", "elbi", "atu", "config";
> > + <0 0x60100000 0 0x100000>,
> > + <0 0x01c03000 0 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> > @@ -2138,8 +2144,14 @@ pcie1: pcie@1c08000 {
> > <0x0 0x40000000 0x0 0xf1d>,
> > <0x0 0x40000f20 0x0 0xa8>,
> > <0x0 0x40001000 0x0 0x1000>,
> > - <0x0 0x40100000 0x0 0x100000>;
> > - reg-names = "parf", "dbi", "elbi", "atu", "config";
> > + <0x0 0x40100000 0x0 0x100000>,
> > + <0x0 0x01c0b000 0x0 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> >
>
^ permalink raw reply
* [PATCH v2 3/3] ARM: dts: aspeed: anacapa: add EVT2 devicetree and update wrapper
From: Colin Huang @ 2026-04-09 11:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
In-Reply-To: <20260409-anacapa-devlop-phase-devicetree-v2-0-68f328671653@gmail.com>
Add a development-phase devicetree for the Facebook Anacapa BMC EVT2
hardware revision and update the Anacapa wrapper DTS to reference
it.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 1123 ++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +-
2 files changed, 1124 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
new file mode 100644
index 000000000000..6e1e51e6c3f2
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dts
@@ -0,0 +1,1123 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Anacapa BMC";
+ compatible = "facebook,anacapa-bmc-evt2", "aspeed,ast2600";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ i2c16 = &i2c0mux0ch0;
+ i2c17 = &i2c0mux0ch1;
+ i2c18 = &i2c0mux0ch2;
+ i2c19 = &i2c0mux0ch3;
+ i2c20 = &i2c1mux0ch0;
+ i2c21 = &i2c1mux0ch1;
+ i2c22 = &i2c1mux0ch2;
+ i2c23 = &i2c1mux0ch3;
+ i2c24 = &i2c4mux0ch0;
+ i2c25 = &i2c4mux0ch1;
+ i2c26 = &i2c4mux0ch2;
+ i2c27 = &i2c4mux0ch3;
+ i2c28 = &i2c4mux0ch4;
+ i2c29 = &i2c4mux0ch5;
+ i2c30 = &i2c4mux0ch6;
+ i2c31 = &i2c4mux0ch7;
+ i2c32 = &i2c8mux0ch0;
+ i2c33 = &i2c8mux0ch1;
+ i2c34 = &i2c8mux0ch2;
+ i2c35 = &i2c8mux0ch3;
+ i2c36 = &i2c10mux0ch0;
+ i2c37 = &i2c10mux0ch1;
+ i2c38 = &i2c10mux0ch2;
+ i2c39 = &i2c10mux0ch3;
+ i2c40 = &i2c10mux0ch4;
+ i2c41 = &i2c10mux0ch5;
+ i2c42 = &i2c10mux0ch6;
+ i2c43 = &i2c10mux0ch7;
+ i2c44 = &i2c11mux0ch0;
+ i2c45 = &i2c11mux0ch1;
+ i2c46 = &i2c11mux0ch2;
+ i2c47 = &i2c11mux0ch3;
+ i2c48 = &i2c11mux0ch4;
+ i2c49 = &i2c11mux0ch5;
+ i2c50 = &i2c11mux0ch6;
+ i2c51 = &i2c11mux0ch7;
+ i2c52 = &i2c13mux0ch0;
+ i2c53 = &i2c13mux0ch1;
+ i2c54 = &i2c13mux0ch2;
+ i2c55 = &i2c13mux0ch3;
+ i2c56 = &i2c13mux0ch4;
+ i2c57 = &i2c13mux0ch5;
+ i2c58 = &i2c13mux0ch6;
+ i2c59 = &i2c13mux0ch7;
+ };
+
+ chosen {
+ stdout-path = "serial4:57600n8";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "bmc_heartbeat_amber";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "fp_id_amber";
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x02c00000>;
+ alignment = <0x00100000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ p3v3_bmc_aux: regulator-p3v3-bmc-aux {
+ compatible = "regulator-fixed";
+ regulator-name = "p3v3_bmc_aux";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ spi_gpio: spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
+};
+
+&adc0 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+ status = "okay";
+};
+
+&adc1 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc10_default>;
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&gpio0 {
+ gpio-line-names =
+
+ /*A0-A7*/
+ "","","","","","","","",
+
+ /*B0-B7*/
+ "BATTERY_DETECT", "",
+ "BMC_I2C1_FPGA_ALERT", "BMC_READY",
+ "IOEXP_INT_3V3", "FM_ID_LED",
+ "", "",
+
+ /*C0-C7*/
+ "","","","",
+ "PMBUS_REQ_N", "PSU_FW_UPDATE_REQ_N",
+ "", "",
+
+ /*D0-D7*/
+ "","","","","","","","",
+
+ /*E0-E7*/
+ "","","","","","","","",
+
+ /*F0-F7*/
+ "","","","","","","","",
+
+ /*G0-G7*/
+ "FM_MUX1_SEL", "",
+ "", "", "", "",
+ "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
+
+ /*H0-H7*/
+ "","","","","","","","",
+
+ /*I0-I7*/
+ "","","","",
+ "", "FLASH_WP_STATUS",
+ "BMC_JTAG_MUX_SEL", "",
+
+ /*J0-J7*/
+ "","","","","","","","",
+
+ /*K0-K7*/
+ "","","","","","","","",
+
+ /*L0-L7*/
+ "","","","","","","","",
+
+ /*M0-M7*/
+ "PCIE_EP_RST_EN", "BMC_FRU_WP",
+ "SCM_HPM_STBY_RST_N", "SCM_HPM_STBY_EN",
+ "STBY_POWER_PG_3V3", "TH500_SHDN_OK",
+ "", "",
+
+ /*N0-N7*/
+ "LED_POSTCODE_0", "LED_POSTCODE_1",
+ "LED_POSTCODE_2", "LED_POSTCODE_3",
+ "LED_POSTCODE_4", "LED_POSTCODE_5",
+ "LED_POSTCODE_6", "LED_POSTCODE_7",
+
+ /*O0-O7*/
+ "RUN_POWER_PG", "PWR_BRAKE",
+ "CHASSIS_AC_LOSS", "BSM_PRSNT_N",
+ "PSU_SMB_ALERT", "FM_TPM_PRSNT_0_N",
+ "PSU_FW_UPDATING_N", "",
+
+ /*P0-P7*/
+ "PWR_BTN_BMC_BUF_N", "IPEX_CABLE_PRSNT",
+ "ID_RST_BTN_BMC_N", "RST_BMC_RSTBTN_OUT_N",
+ "PWR_LED", "RUN_POWER_EN",
+ "SHDN_FORCE", "BMC_HEARTBEAT_N",
+
+ /*Q0-Q7*/
+ "IRQ_PCH_TPM_SPI_LV3_N", "USB_OC0_REAR_N",
+ "UART_MUX_SEL", "I2C_MUX_RESET",
+ "RSVD_NV_PLT_DETECT", "SPI_TPM_INT",
+ "CPU_JTAG_MUX_SELECT", "THERM_BB_OVERT",
+
+ /*R0-R7*/
+ "THERM_BB_WARN", "SPI_BMC_FPGA_INT",
+ "CPU_BOOT_DONE", "PMBUS_GNT",
+ "CHASSIS_PWR_BRK", "PCIE_WAKE",
+ "PDB_THERM_OVERT", "SHDN_REQ",
+
+ /*S0-S7*/
+ "", "",
+ "SYS_BMC_PWRBTN_N", "FM_TPM_PRSNT_1_N",
+ "FM_BMC_DEBUG_SW_N", "UID_LED_N",
+ "SYS_FAULT_LED_N", "RUN_POWER_FAULT",
+
+ /*T0-T7*/
+ "","","","","","","","",
+
+ /*U0-U7*/
+ "","","","","","","","",
+
+ /*V0-V7*/
+ "L2_RST_REQ_OUT", "L0L1_RST_REQ_OUT",
+ "BMC_ID_BEEP_SEL", "BMC_I2C0_FPGA_ALERT",
+ "SMB_BMC_TMP_ALERT", "PWR_LED_N",
+ "SYS_RST_OUT", "IRQ_TPM_SPI_N",
+
+ /*W0-W7*/
+ "","","","","","","","",
+
+ /*X0-X7*/
+ "","","","","","","","",
+
+ /*Y0-Y7*/
+ "RST_WDTRST_PLD_N", "RST_BMC_SELF_HW",
+ "FM_FLASH_LATCH_N", "BMC_EMMC_RST_N",
+ "","","","",
+
+ /*Z0-Z7*/
+ "","","","","","","","";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/
+ "","","","","","","","",
+
+ /*18B0-18B7*/
+ "","","","",
+ "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
+ "FM_BOARD_BMC_REV_ID2", "",
+
+ /*18C0-18C7*/
+ "", "", "SPI_BMC_BIOS_ROM_IRQ0_N", "",
+ "", "", "", "",
+
+ /*18D0-18D7*/
+ "","","","","","","","",
+
+ /*18E0-18E3*/
+ "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
+};
+
+// L Bridge Board
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c0mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// R Bridge Board
+&i2c1 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c1mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// MB - E1.S
+&i2c4 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// AMC
+&i2c5 {
+ status = "okay";
+};
+
+// MB
+&i2c6 {
+ status = "okay";
+
+ // HPM FRU
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+// SCM
+&i2c7 {
+ status = "okay";
+
+
+};
+
+// MB - PDB
+&i2c8 {
+ status = "okay";
+
+ i2c-mux@72 {
+ compatible = "nxp,pca9546";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c8mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
+ "RPDB_FAN_CT_FAN_FAIL_R_N", "",
+ "", "",
+ "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
+ "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
+ "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
+ "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
+ "RPDB_PGD_P3V3_STBY_PWRGD_R",
+ "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
+ "RPDB_PWRGD_P50V_HSC4_SYS_R",
+ "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
+ "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
+ "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
+ "", "RPDB_FAN1_PRSNT_N_R",
+ "", "RPDB_FAN2_PRSNT_N_R",
+ "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
+ "", "";
+ };
+
+ // R-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
+ "LPDB_FAN_CT_FAN_FAIL_R_N","",
+ "","",
+ "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
+ "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
+ "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
+ "LPDB_PWRGD_P50V_HSC5_SYS_R","";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
+ "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
+ "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
+ "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
+ "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
+ "","",
+ "","",
+ "","";
+ };
+
+ // L-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c8mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// SCM
+&i2c9 {
+ status = "okay";
+
+ // SCM FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
+ // BSM FRU
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+// R Bridge Board
+&i2c10 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c10mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
+ "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
+ "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
+ "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // R Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c10mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// L Bridge Board
+&i2c11 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c11mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
+ "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
+ "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
+ "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // L Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c11mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// Debug Card
+&i2c12 {
+ status = "okay";
+};
+
+// MB
+&i2c13 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c13mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+ };
+ i2c13mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // HPM BRD ID FRU
+ eeprom@51 {
+ compatible = "atmel,24c256";
+ reg = <0x51>;
+ };
+ };
+ i2c13mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@28 {
+ compatible = "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&sgpiom0>;
+ interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+
+// SCM
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&kcs2 {
+ aspeed,lpc-io-reg = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ aspeed,lpc-io-reg = <0xca2>;
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncsi3_default>;
+ use-ncsi;
+};
+
+&sgpiom0 {
+ ngpios = <128>;
+ bus-frequency = <2000000>;
+ gpio-line-names =
+ /*in - out */
+ /* A0-A7 line 0-15 */
+ "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N",
+ "L_BNIC0_FLT", "CPU0_KBRST_N",
+ "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N",
+ "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0",
+ "L_BNIC3_FLT", "Force_I3C_SEL",
+ "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle",
+ "", "",
+ "", "",
+
+ /* B0-B7 line 16-31 */
+ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
+ "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
+ "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
+ "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
+ "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L",
+ "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L",
+ "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330",
+ "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331",
+
+ /* C0-C7 line 32-47 */
+ "RSVD_RMC_GPIO3", "RTM_MUX_L",
+ "LEAK_DETECT_RMC_N", "RTM_MUX_R",
+ "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N",
+ "No_Leak_Sensor_flag", "whdt_sel",
+ "", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* D0-D7 line 48-63 */
+ "PWRGD_CHAD_CPU0_FPGA", "",
+ "PWRGD_CHEH_CPU0_FPGA", "",
+ "PWRGD_CHIL_CPU0_FPGA", "",
+ "PWRGD_CHMP_CPU0_FPGA", "",
+ "AMC_BRD_PRSNT_CPLD_L", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* E0-E7 line 64-79 */
+ "L_PRSNT_B_FENIC_R2_N", "",
+ "L_PRSNT_B_BENIC0_R2_N", "",
+ "L_PRSNT_B_BENIC1_R2_N", "",
+ "L_PRSNT_B_BENIC2_R2_N", "",
+ "L_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* F0-F7 line 80-95 */
+ "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY",
+ "R_PRSNT_B_BENIC0_R2_N", "",
+ "R_PRSNT_B_BENIC1_R2_N", "",
+ "R_PRSNT_B_BENIC2_R2_N", "",
+ "R_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* G0-G7 line 96-111 */
+ "L_PRSNT_EDSFF2_N", "",
+ "L_PRSNT_EDSFF3_N", "",
+ "R_PRSNT_EDSFF2_N", "",
+ "R_PRSNT_EDSFF3_N", "",
+ "", "",
+ "", "",
+ "", "",
+ "PRSNT_NFC_BOARD_R", "",
+
+ /* H0-H7 line 112-127 */
+ "R_FNIC_FLT", "",
+ "R_BNIC0_FLT", "",
+ "R_BNIC1_FLT", "",
+ "R_BNIC2_FLT", "",
+ "R_BNIC3_FLT", "",
+ "R_RTM_SW_FLT", "",
+ "", "",
+ "", "",
+
+ /* I0-I7 line 128-143 */
+ "EAM0_BRD_PRSNT_R_L", "",
+ "EAM1_BRD_PRSNT_R_L", "",
+ "EAM2_BRD_PRSNT_R_L", "",
+ "EAM3_BRD_PRSNT_R_L", "",
+ "FM_TPM_PRSNT_R_N", "",
+ "PDB_PRSNT_R_N", "",
+ "PRSNT_EDSFF0_N", "",
+ "PRSNT_CPU0_N", "",
+
+ /* J0-J7 line 144-159 */
+ "PRSNT_L_BRIDGE_R", "",
+ "PRSNT_R_BRIDGE_R", "",
+ "BRIDGE_L_MAIN_PG_R", "",
+ "BRIDGE_R_MAIN_PG_R", "",
+ "BRIDGE_L_STBY_PG_R", "",
+ "BRIDGE_R_STBY_PG_R", "",
+ "IRQ_NFC_BOARD_R", "",
+ "RSMRST_N", "",
+
+ /* K0-K7 line 160-175 */
+ "ADC_I2C_ALERT_N", "",
+ "TEMP_I2C_ALERT_R_L", "",
+ "CPU0_VR_SMB_ALERT_CPLD_N", "",
+ "COVER_INTRUDER_R_N", "",
+ "HANDLE_INTRUDER_CPLD_N", "",
+ "IRQ_MCIO_CPLD_WAKE_R_N", "",
+ "APML_CPU0_ALERT_R_N", "",
+ "PDB_ALERT_R_N", "",
+
+ /* L0-L7 line 176-191 */
+ "CPU0_SP7R1", "",
+ "CPU0_SP7R2", "",
+ "CPU0_SP7R3", "",
+ "CPU0_SP7R4", "",
+ "CPU0_CORETYPE0", "",
+ "CPU0_CORETYPE1", "",
+ "CPU0_CORETYPE2", "",
+ "FM_BIOS_POST_CMPLT_R_N", "",
+
+ /* M0-M7 line 192-207 */
+ "EAM0_SMERR_CPLD_R_L", "",
+ "EAM1_SMERR_CPLD_R_L", "",
+ "EAM2_SMERR_CPLD_R_L", "",
+ "EAM3_SMERR_CPLD_R_L", "",
+ "CPU0_SMERR_N_R", "",
+ "CPU0_NV_SAVE_N_R", "",
+ "PDB_PWR_LOSS_CPLD_N", "",
+ "IRQ_BMC_SMI_ACTIVE_R_N", "",
+
+ /* N0-N7 line 208-223 */
+ "AMCROT_BMC_S5_RDY_R", "",
+ "AMC_RDY_R", "",
+ "AMC_STBY_PGOOD_R", "",
+ "CPU_AMC_SLP_S5_R_L", "",
+ "AMC_CPU_EAMPG_R", "",
+ "DIMM_PMIC_PG_TIMEOUT", "",
+ "EAM_MOD_PWR_GD_TIMEOUT", "",
+ "CPLD_AMC_STBY_PWR_EN", "",
+
+ /* O0-O7 line 224-239 */
+ "HPM_PWR_FAIL", "Port80_b0",
+ "FM_DIMM_IP_FAIL", "Port80_b1",
+ "FM_DIMM_AH_FAIL", "Port80_b2",
+ "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
+ "cpu_thermtrip_detect", "Port80_b4",
+ "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
+ "CPLD_SGPIO_RDY", "Port80_b6",
+ "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7",
+
+ /* P0-P7 line 240-255 */
+ "CPU0_SLP_S5_N_R", "NFC_VEN",
+ "CPU0_SLP_S3_N_R", "",
+ "FM_CPU0_PWRGD", "",
+ "PWRGD_RMC", "",
+ "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST",
+ "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST",
+ "AMC_FAIL", "HPM_CPLD_RISCV_RST",
+ "wS0_ON_N", "";
+ status = "okay";
+};
+
+// BIOS Flash
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ status = "okay";
+ reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ label = "pnor";
+ spi-max-frequency = <12000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ status = "okay";
+ };
+};
+
+// HOST BIOS Debug
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+// BMC Debug Console
+&uart5 {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&wdt1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 980628af80b0..18b6a7525178 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
-#include "aspeed-bmc-facebook-anacapa-evt1.dts"
+#include "aspeed-bmc-facebook-anacapa-evt2.dts"
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/3] ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it
From: Colin Huang @ 2026-04-09 11:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
In-Reply-To: <20260409-anacapa-devlop-phase-devicetree-v2-0-68f328671653@gmail.com>
This change introduces a development-phase devicetree for the
Facebook Anacapa BMC EVT1 hardware revision and updates the Anacapa
wrapper DTS to reference it.
A dedicated EVT1 DTS is added for revision-specific hardware while
keeping a single, Anacapa entrypoint used by the build and deployment
flow. The top-level aspeed-bmc-facebook-anacapa.dts
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1067 ++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1064 +------------------
2 files changed, 1068 insertions(+), 1063 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
new file mode 100644
index 000000000000..81ad065e114c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dts
@@ -0,0 +1,1067 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Anacapa BMC";
+ compatible = "facebook,anacapa-bmc-evt1", "aspeed,ast2600";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ i2c16 = &i2c0mux0ch0;
+ i2c17 = &i2c0mux0ch1;
+ i2c18 = &i2c0mux0ch2;
+ i2c19 = &i2c0mux0ch3;
+ i2c20 = &i2c1mux0ch0;
+ i2c21 = &i2c1mux0ch1;
+ i2c22 = &i2c1mux0ch2;
+ i2c23 = &i2c1mux0ch3;
+ i2c24 = &i2c4mux0ch0;
+ i2c25 = &i2c4mux0ch1;
+ i2c26 = &i2c4mux0ch2;
+ i2c27 = &i2c4mux0ch3;
+ i2c28 = &i2c4mux0ch4;
+ i2c29 = &i2c4mux0ch5;
+ i2c30 = &i2c4mux0ch6;
+ i2c31 = &i2c4mux0ch7;
+ i2c32 = &i2c8mux0ch0;
+ i2c33 = &i2c8mux0ch1;
+ i2c34 = &i2c8mux0ch2;
+ i2c35 = &i2c8mux0ch3;
+ i2c36 = &i2c10mux0ch0;
+ i2c37 = &i2c10mux0ch1;
+ i2c38 = &i2c10mux0ch2;
+ i2c39 = &i2c10mux0ch3;
+ i2c40 = &i2c10mux0ch4;
+ i2c41 = &i2c10mux0ch5;
+ i2c42 = &i2c10mux0ch6;
+ i2c43 = &i2c10mux0ch7;
+ i2c44 = &i2c11mux0ch0;
+ i2c45 = &i2c11mux0ch1;
+ i2c46 = &i2c11mux0ch2;
+ i2c47 = &i2c11mux0ch3;
+ i2c48 = &i2c11mux0ch4;
+ i2c49 = &i2c11mux0ch5;
+ i2c50 = &i2c11mux0ch6;
+ i2c51 = &i2c11mux0ch7;
+ i2c52 = &i2c13mux0ch0;
+ i2c53 = &i2c13mux0ch1;
+ i2c54 = &i2c13mux0ch2;
+ i2c55 = &i2c13mux0ch3;
+ i2c56 = &i2c13mux0ch4;
+ i2c57 = &i2c13mux0ch5;
+ i2c58 = &i2c13mux0ch6;
+ i2c59 = &i2c13mux0ch7;
+ };
+
+ chosen {
+ stdout-path = "serial4:57600n8";
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
+ <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
+ <&adc1 2>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "bmc_heartbeat_amber";
+ gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "fp_id_amber";
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ video_engine_memory: video {
+ size = <0x02c00000>;
+ alignment = <0x00100000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ p3v3_bmc_aux: regulator-p3v3-bmc-aux {
+ compatible = "regulator-fixed";
+ regulator-name = "p3v3_bmc_aux";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ spi_gpio: spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
+};
+
+&adc0 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+ &pinctrl_adc2_default &pinctrl_adc3_default
+ &pinctrl_adc4_default &pinctrl_adc5_default
+ &pinctrl_adc6_default &pinctrl_adc7_default>;
+ status = "okay";
+};
+
+&adc1 {
+ aspeed,int-vref-microvolt = <2500000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc10_default>;
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&gpio0 {
+ gpio-line-names =
+
+ /*A0-A7*/
+ "","","","","","","","",
+
+ /*B0-B7*/
+ "BATTERY_DETECT", "", "", "BMC_READY",
+ "", "FM_ID_LED", "", "",
+
+ /*C0-C7*/
+ "","","","","","","","",
+
+ /*D0-D7*/
+ "","","","","","","","",
+
+ /*E0-E7*/
+ "","","","","","","","",
+
+ /*F0-F7*/
+ "","","","","","","","",
+
+ /*G0-G7*/
+ "FM_MUX1_SEL", "", "", "",
+ "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
+
+ /*H0-H7*/
+ "","","","","","","","",
+
+ /*I0-I7*/
+ "", "", "", "",
+ "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "",
+
+ /*J0-J7*/
+ "","","","","","","","",
+
+ /*K0-K7*/
+ "","","","","","","","",
+
+ /*L0-L7*/
+ "","","","","","","","",
+
+ /*M0-M7*/
+ "", "BMC_FRU_WP", "", "",
+ "", "", "", "",
+
+ /*N0-N7*/
+ "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3",
+ "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7",
+
+ /*O0-O7*/
+ "","","","","","","","",
+
+ /*P0-P7*/
+ "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "",
+ "PWR_LED", "", "", "BMC_HEARTBEAT_N",
+
+ /*Q0-Q7*/
+ "","","","","","","","",
+
+ /*R0-R7*/
+ "","","","","","","","",
+
+ /*S0-S7*/
+ "", "", "SYS_BMC_PWRBTN_N", "",
+ "", "", "", "RUN_POWER_FAULT",
+
+ /*T0-T7*/
+ "","","","","","","","",
+
+ /*U0-U7*/
+ "","","","","","","","",
+
+ /*V0-V7*/
+ "","","","","","","","",
+
+ /*W0-W7*/
+ "","","","","","","","",
+
+ /*X0-X7*/
+ "","","","","","","","",
+
+ /*Y0-Y7*/
+ "","","","","","","","",
+
+ /*Z0-Z7*/
+ "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK",
+ "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /*18A0-18A7*/
+ "","","","","","","","",
+
+ /*18B0-18B7*/
+ "","","","",
+ "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
+ "FM_BOARD_BMC_REV_ID2", "",
+
+ /*18C0-18C7*/
+ "","","","","","","","",
+
+ /*18D0-18D7*/
+ "","","","","","","","",
+
+ /*18E0-18E3*/
+ "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
+};
+
+// L Bridge Board
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c0mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c0mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// R Bridge Board
+&i2c1 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c2048";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c1mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c1mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// MB - E1.S
+&i2c4 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c4mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// AMC
+&i2c5 {
+ status = "okay";
+};
+
+// MB
+&i2c6 {
+ status = "okay";
+
+ // HPM FRU
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
+// SCM
+&i2c7 {
+ status = "okay";
+
+
+};
+
+// MB - PDB
+&i2c8 {
+ status = "okay";
+
+ i2c-mux@72 {
+ compatible = "nxp,pca9546";
+ reg = <0x72>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c8mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
+ "RPDB_FAN_CT_FAN_FAIL_R_N", "",
+ "", "",
+ "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
+ "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
+ "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
+ "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
+ "RPDB_PGD_P3V3_STBY_PWRGD_R",
+ "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
+ "RPDB_PWRGD_P50V_HSC4_SYS_R",
+ "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
+ "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
+ "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
+ "", "RPDB_FAN1_PRSNT_N_R",
+ "", "RPDB_FAN2_PRSNT_N_R",
+ "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
+ "", "";
+ };
+
+ // R-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
+ "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
+ "LPDB_FAN_CT_FAN_FAIL_R_N","",
+ "","",
+ "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
+ "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
+ "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
+ "LPDB_PWRGD_P50V_HSC5_SYS_R","";
+ };
+
+ gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
+ "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
+ "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
+ "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
+ "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
+ "","",
+ "","",
+ "","";
+ };
+
+ // L-PDB FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+ };
+ i2c8mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c8mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// SCM
+&i2c9 {
+ status = "okay";
+
+ // SCM FRU
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+
+ // BSM FRU
+ eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ };
+};
+
+// R Bridge Board
+&i2c10 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c10mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
+ "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
+ "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
+ "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // R Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c10mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c10mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// L Bridge Board
+&i2c11 {
+ status = "okay";
+
+ i2c-mux@71 {
+ compatible = "nxp,pca9548";
+ reg = <0x71>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c11mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "","",
+ "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
+ "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
+ "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
+ "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
+ "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
+ "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
+ "","";
+ };
+
+ // L Bridge Board FRU
+ eeprom@52 {
+ compatible = "atmel,24c256";
+ reg = <0x52>;
+ };
+ };
+ i2c11mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c11mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+// Debug Card
+&i2c12 {
+ status = "okay";
+};
+
+// MB
+&i2c13 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c13mux0ch0: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch1: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch2: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch3: i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1f {
+ compatible = "ti,adc128d818";
+ reg = <0x1f>;
+ ti,mode = /bits/ 8 <1>;
+ };
+ };
+ i2c13mux0ch4: i2c@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // HPM BRD ID FRU
+ eeprom@51 {
+ compatible = "atmel,24c256";
+ reg = <0x51>;
+ };
+ };
+ i2c13mux0ch5: i2c@5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch6: i2c@6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c13mux0ch7: i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@28 {
+ compatible = "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&sgpiom0>;
+ interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+
+// SCM
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&kcs2 {
+ aspeed,lpc-io-reg = <0xca8>;
+ status = "okay";
+};
+
+&kcs3 {
+ aspeed,lpc-io-reg = <0xca2>;
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ncsi3_default>;
+ use-ncsi;
+};
+
+&sgpiom0 {
+ ngpios = <128>;
+ bus-frequency = <2000000>;
+ gpio-line-names =
+ /*in - out - in - out */
+ /* A0-A7 line 0-15 */
+ "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
+ "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
+ "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
+ "", "", "", "",
+
+ /* B0-B7 line 16-31 */
+ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
+ "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
+ "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
+ "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
+ "Channel4_leakage_Manifold2", "",
+ "Channel5_leakage_EAM1", "",
+ "Channel6_leakage_CPU_DIMM", "",
+ "Channel7_leakage_EAM2", "",
+
+ /* C0-C7 line 32-47 */
+ "RSVD_RMC_GPIO3", "", "", "",
+ "", "", "", "",
+ "LEAK_DETECT_RMC_N", "", "", "",
+ "", "", "", "",
+
+ /* D0-D7 line 48-63 */
+ "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
+ "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
+ "AMC_BRD_PRSNT_CPLD_L", "", "", "",
+ "", "", "", "",
+
+ /* E0-E7 line 64-79 */
+ "AMC_PDB_EAMHSC0_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC1_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC2_CPLD_EN_R", "",
+ "AMC_PDB_EAMHSC3_CPLD_EN_R", "",
+ "", "", "", "",
+ "", "", "", "",
+
+ /* F0-F7 line 80-95 */
+ "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY",
+ "PWRGD_PVDDCR_CPU0_P0", "",
+ "", "", "", "",
+ "", "", "", "",
+
+ /* G0-G7 line 96-111 */
+ "PWRGD_PVDDCR_SOC_P0", "",
+ "PWRGD_PVDDIO_P0", "",
+ "PWRGD_PVDDIO_MEM_S3_P0", "",
+ "PWRGD_CHMP_CPU0_FPGA", "",
+ "PWRGD_CHIL_CPU0_FPGA", "",
+ "PWRGD_CHEH_CPU0_FPGA", "",
+ "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
+ "", "",
+
+ /* H0-H7 line 112-127 */
+ "PWRGD_P3V3", "",
+ "P12V_DDR_IP_PWRGD_R", "",
+ "P12V_DDR_AH_PWRGD_R", "",
+ "PWRGD_P12V_VRM1_CPLD_PG_R", "",
+ "PWRGD_P12V_VRM0_CPLD_PG_R", "",
+ "PWRGD_PDB_HSC4_CPLD_PG_R", "",
+ "PWRGD_PVDD18_S5_P0_PG", "",
+ "PWRGD_PVDD33_S5_P0_PG", "",
+
+ /* I0-I7 line 128-143 */
+ "EAM0_BRD_PRSNT_R_L", "",
+ "EAM1_BRD_PRSNT_R_L", "",
+ "EAM2_BRD_PRSNT_R_L", "",
+ "EAM3_BRD_PRSNT_R_L", "",
+ "EAM0_CPU_MOD_PWR_GD_R", "",
+ "EAM1_CPU_MOD_PWR_GD_R", "",
+ "EAM2_CPU_MOD_PWR_GD_R", "",
+ "EAM3_CPU_MOD_PWR_GD_R", "",
+
+ /* J0-J7 line 144-159 */
+ "PRSNT_L_BIRDGE_R", "",
+ "PRSNT_R_BIRDGE_R", "",
+ "BRIDGE_L_MAIN_PG_R", "",
+ "BRIDGE_R_MAIN_PG_R", "",
+ "BRIDGE_L_STBY_PG_R", "",
+ "BRIDGE_R_STBY_PG_R", "",
+ "", "", "", "",
+
+ /* K0-K7 line 160-175 */
+ "ADC_I2C_ALERT_N", "",
+ "TEMP_I2C_ALERT_R_L", "",
+ "CPU0_VR_SMB_ALERT_CPLD_N", "",
+ "COVER_INTRUDER_R_N", "",
+ "HANDLE_INTRUDER_CPLD_N", "",
+ "IRQ_MCIO_CPLD_WAKE_R_N", "",
+ "APML_CPU0_ALERT_R_N", "",
+ "PDB_ALERT_R_N", "",
+
+ /* L0-L7 line 176-191 */
+ "CPU0_SP7R1", "", "CPU0_SP7R2", "",
+ "CPU0_SP7R3", "", "CPU0_SP7R4", "",
+ "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
+ "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
+
+ /* M0-M7 line 192-207 */
+ "EAM0_SMERR_CPLD_R_L", "",
+ "EAM1_SMERR_CPLD_R_L", "",
+ "EAM2_SMERR_CPLD_R_L", "",
+ "EAM3_SMERR_CPLD_R_L", "",
+ "CPU0_SMERR_N_R", "",
+ "CPU0_NV_SAVE_N_R", "",
+ "PDB_PWR_LOSS_CPLD_N", "",
+ "IRQ_BMC_SMI_ACTIVE_R_N", "",
+
+ /* N0-N7 line 208-223 */
+ "AMCROT_BMC_S5_RDY_R", "",
+ "AMC_RDY_R", "",
+ "AMC_STBY_PGOOD_R", "",
+ "CPU_AMC_SLP_S5_R_L", "",
+ "AMC_CPU_EAMPG_R", "",
+ "", "", "", "",
+
+ /* O0-O7 line 224-239 */
+ "HPM_PWR_FAIL", "Port80_b0",
+ "FM_DIMM_IP_FAIL", "Port80_b1",
+ "FM_DIMM_AH_FAIL", "Port80_b2",
+ "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
+ "FM_CPU0_THERMTRIP_N", "Port80_b4",
+ "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
+ "CPLD_SGPIO_RDY", "Port80_b6",
+ "", "Port80_b7",
+
+ /* P0-P7 line 240-255 */
+ "CPU0_SLP_S5_N_R", "NFC_VEN",
+ "CPU0_SLP_S3_N_R", "",
+ "FM_CPU0_PWRGD", "",
+ "PWRGD_RMC", "",
+ "FM_RST_CPU0_RESET_N", "",
+ "FM_PWRGD_CPU0_PWROK", "",
+ "wS5_PWR_Ready", "",
+ "wS0_ON_N", "PWRGD_P1V0_AUX";
+ status = "okay";
+};
+
+// BIOS Flash
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+ status = "okay";
+ reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ label = "pnor";
+ spi-max-frequency = <12000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ status = "okay";
+ };
+};
+
+// HOST BIOS Debug
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+// BMC Debug Console
+&uart5 {
+ status = "okay";
+};
+
+&uart_routing {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+&wdt1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+ aspeed,reset-type = "soc";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+ aspeed,ext-pulse-duration = <256>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 2cb7bd128d24..980628af80b0 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -1,1067 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
-#include "aspeed-g6.dtsi"
-#include <dt-bindings/gpio/aspeed-gpio.h>
-#include <dt-bindings/i2c/i2c.h>
+#include "aspeed-bmc-facebook-anacapa-evt1.dts"
-/ {
- model = "Facebook Anacapa BMC";
- compatible = "facebook,anacapa-bmc", "aspeed,ast2600";
-
- aliases {
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- i2c16 = &i2c0mux0ch0;
- i2c17 = &i2c0mux0ch1;
- i2c18 = &i2c0mux0ch2;
- i2c19 = &i2c0mux0ch3;
- i2c20 = &i2c1mux0ch0;
- i2c21 = &i2c1mux0ch1;
- i2c22 = &i2c1mux0ch2;
- i2c23 = &i2c1mux0ch3;
- i2c24 = &i2c4mux0ch0;
- i2c25 = &i2c4mux0ch1;
- i2c26 = &i2c4mux0ch2;
- i2c27 = &i2c4mux0ch3;
- i2c28 = &i2c4mux0ch4;
- i2c29 = &i2c4mux0ch5;
- i2c30 = &i2c4mux0ch6;
- i2c31 = &i2c4mux0ch7;
- i2c32 = &i2c8mux0ch0;
- i2c33 = &i2c8mux0ch1;
- i2c34 = &i2c8mux0ch2;
- i2c35 = &i2c8mux0ch3;
- i2c36 = &i2c10mux0ch0;
- i2c37 = &i2c10mux0ch1;
- i2c38 = &i2c10mux0ch2;
- i2c39 = &i2c10mux0ch3;
- i2c40 = &i2c10mux0ch4;
- i2c41 = &i2c10mux0ch5;
- i2c42 = &i2c10mux0ch6;
- i2c43 = &i2c10mux0ch7;
- i2c44 = &i2c11mux0ch0;
- i2c45 = &i2c11mux0ch1;
- i2c46 = &i2c11mux0ch2;
- i2c47 = &i2c11mux0ch3;
- i2c48 = &i2c11mux0ch4;
- i2c49 = &i2c11mux0ch5;
- i2c50 = &i2c11mux0ch6;
- i2c51 = &i2c11mux0ch7;
- i2c52 = &i2c13mux0ch0;
- i2c53 = &i2c13mux0ch1;
- i2c54 = &i2c13mux0ch2;
- i2c55 = &i2c13mux0ch3;
- i2c56 = &i2c13mux0ch4;
- i2c57 = &i2c13mux0ch5;
- i2c58 = &i2c13mux0ch6;
- i2c59 = &i2c13mux0ch7;
- };
-
- chosen {
- stdout-path = "serial4:57600n8";
- };
-
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
- <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
- <&adc1 2>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- label = "bmc_heartbeat_amber";
- gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- label = "fp_id_amber";
- default-state = "off";
- gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- video_engine_memory: video {
- size = <0x02c00000>;
- alignment = <0x00100000>;
- compatible = "shared-dma-pool";
- reusable;
- };
-
- gfx_memory: framebuffer {
- size = <0x01000000>;
- alignment = <0x01000000>;
- compatible = "shared-dma-pool";
- reusable;
- };
- };
-
- p3v3_bmc_aux: regulator-p3v3-bmc-aux {
- compatible = "regulator-fixed";
- regulator-name = "p3v3_bmc_aux";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- spi_gpio: spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
- num-chipselects = <1>;
- status = "okay";
-
- tpm@0 {
- compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
- spi-max-frequency = <33000000>;
- reg = <0>;
- };
- };
-};
-
-&adc0 {
- aspeed,int-vref-microvolt = <2500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
- &pinctrl_adc2_default &pinctrl_adc3_default
- &pinctrl_adc4_default &pinctrl_adc5_default
- &pinctrl_adc6_default &pinctrl_adc7_default>;
- status = "okay";
-};
-
-&adc1 {
- aspeed,int-vref-microvolt = <2500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc10_default>;
- status = "okay";
-};
-
-&ehci1 {
- status = "okay";
-};
-
-&fmc {
- status = "okay";
-
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
- spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-128.dtsi"
- };
-
- flash@1 {
- status = "okay";
- m25p,fast-read;
- label = "alt-bmc";
- spi-max-frequency = <50000000>;
- };
-};
-
-&gfx {
- status = "okay";
- memory-region = <&gfx_memory>;
-};
-
-&gpio0 {
- gpio-line-names =
-
- /*A0-A7*/
- "","","","","","","","",
-
- /*B0-B7*/
- "BATTERY_DETECT", "", "", "BMC_READY",
- "", "FM_ID_LED", "", "",
-
- /*C0-C7*/
- "","","","","","","","",
-
- /*D0-D7*/
- "","","","","","","","",
-
- /*E0-E7*/
- "","","","","","","","",
-
- /*F0-F7*/
- "","","","","","","","",
-
- /*G0-G7*/
- "FM_MUX1_SEL", "", "", "",
- "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
-
- /*H0-H7*/
- "","","","","","","","",
-
- /*I0-I7*/
- "", "", "", "",
- "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "",
-
- /*J0-J7*/
- "","","","","","","","",
-
- /*K0-K7*/
- "","","","","","","","",
-
- /*L0-L7*/
- "","","","","","","","",
-
- /*M0-M7*/
- "", "BMC_FRU_WP", "", "",
- "", "", "", "",
-
- /*N0-N7*/
- "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3",
- "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7",
-
- /*O0-O7*/
- "","","","","","","","",
-
- /*P0-P7*/
- "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "",
- "PWR_LED", "", "", "BMC_HEARTBEAT_N",
-
- /*Q0-Q7*/
- "","","","","","","","",
-
- /*R0-R7*/
- "","","","","","","","",
-
- /*S0-S7*/
- "", "", "SYS_BMC_PWRBTN_N", "",
- "", "", "", "RUN_POWER_FAULT",
-
- /*T0-T7*/
- "","","","","","","","",
-
- /*U0-U7*/
- "","","","","","","","",
-
- /*V0-V7*/
- "","","","","","","","",
-
- /*W0-W7*/
- "","","","","","","","",
-
- /*X0-X7*/
- "","","","","","","","",
-
- /*Y0-Y7*/
- "","","","","","","","",
-
- /*Z0-Z7*/
- "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK",
- "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", "";
-};
-
-&gpio1 {
- gpio-line-names =
- /*18A0-18A7*/
- "","","","","","","","",
-
- /*18B0-18B7*/
- "","","","",
- "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1",
- "FM_BOARD_BMC_REV_ID2", "",
-
- /*18C0-18C7*/
- "","","","","","","","",
-
- /*18D0-18D7*/
- "","","","","","","","",
-
- /*18E0-18E3*/
- "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", "";
-};
-
-// L Bridge Board
-&i2c0 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c2048";
- reg = <0x50>;
- pagesize = <128>;
- };
-
- i2c-mux@70 {
- compatible = "nxp,pca9546";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c0mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c0mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c0mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c0mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// R Bridge Board
-&i2c1 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c2048";
- reg = <0x50>;
- pagesize = <128>;
- };
-
- i2c-mux@70 {
- compatible = "nxp,pca9546";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c1mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c1mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c1mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c1mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// MB - E1.S
-&i2c4 {
- status = "okay";
-
- i2c-mux@70 {
- compatible = "nxp,pca9548";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c4mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c4mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// AMC
-&i2c5 {
- status = "okay";
-};
-
-// MB
-&i2c6 {
- status = "okay";
-
- // HPM FRU
- eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-};
-
-// SCM
-&i2c7 {
- status = "okay";
-
-
-};
-
-// MB - PDB
-&i2c8 {
- status = "okay";
-
- i2c-mux@72 {
- compatible = "nxp,pca9546";
- reg = <0x72>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c8mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc@1f {
- compatible = "ti,adc128d818";
- reg = <0x1f>;
- ti,mode = /bits/ 8 <1>;
- };
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N",
- "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP",
- "RPDB_FAN_CT_FAN_FAIL_R_N", "",
- "", "",
- "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N",
- "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N",
- "RPDB_I2C_P12V_MB_VRM_ALERT_R_N",
- "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N",
- "RPDB_PGD_P3V3_STBY_PWRGD_R",
- "RPDB_P12V_STBY_VRM_PWRGD_BUF_R";
- };
-
- gpio@24 {
- compatible = "nxp,pca9555";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R",
- "RPDB_PWRGD_P50V_HSC4_SYS_R",
- "RPDB_PWRGD_P50V_STBY_SYS_BUF_R",
- "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG",
- "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG",
- "", "RPDB_FAN1_PRSNT_N_R",
- "", "RPDB_FAN2_PRSNT_N_R",
- "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R",
- "", "";
- };
-
- // R-PDB FRU
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
- };
- i2c8mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N",
- "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP",
- "LPDB_FAN_CT_FAN_FAIL_R_N","",
- "","",
- "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N",
- "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N",
- "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R",
- "LPDB_PWRGD_P50V_HSC5_SYS_R","";
- };
-
- gpio@24 {
- compatible = "nxp,pca9555";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG",
- "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG",
- "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R",
- "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R",
- "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R",
- "","",
- "","",
- "","";
- };
-
- // L-PDB FRU
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
- };
- i2c8mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c8mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// SCM
-&i2c9 {
- status = "okay";
-
- // SCM FRU
- eeprom@50 {
- compatible = "atmel,24c128";
- reg = <0x50>;
- };
-
- // BSM FRU
- eeprom@56 {
- compatible = "atmel,24c64";
- reg = <0x56>;
- };
-};
-
-// R Bridge Board
-&i2c10 {
- status = "okay";
-
- i2c-mux@71 {
- compatible = "nxp,pca9548";
- reg = <0x71>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c10mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "","",
- "","RBB_CPLD_REFRESH_IN_PRGRS_R_L",
- "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L",
- "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL",
- "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N",
- "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N",
- "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N",
- "","";
- };
-
- // R Bridge Board FRU
- eeprom@52 {
- compatible = "atmel,24c256";
- reg = <0x52>;
- };
- };
- i2c10mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c10mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// L Bridge Board
-&i2c11 {
- status = "okay";
-
- i2c-mux@71 {
- compatible = "nxp,pca9548";
- reg = <0x71>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c11mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio@22 {
- compatible = "nxp,pca9555";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
-
- gpio-line-names =
- "","",
- "","LBB_CPLD_REFRESH_IN_PRGRS_R_L",
- "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L",
- "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL",
- "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N",
- "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N",
- "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N",
- "","";
- };
-
- // L Bridge Board FRU
- eeprom@52 {
- compatible = "atmel,24c256";
- reg = <0x52>;
- };
- };
- i2c11mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c11mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-// Debug Card
-&i2c12 {
- status = "okay";
-};
-
-// MB
-&i2c13 {
- status = "okay";
-
- i2c-mux@70 {
- compatible = "nxp,pca9548";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-mux-idle-disconnect;
-
- i2c13mux0ch0: i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch1: i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch2: i2c@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch3: i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc@1f {
- compatible = "ti,adc128d818";
- reg = <0x1f>;
- ti,mode = /bits/ 8 <1>;
- };
- };
- i2c13mux0ch4: i2c@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- // HPM BRD ID FRU
- eeprom@51 {
- compatible = "atmel,24c256";
- reg = <0x51>;
- };
- };
- i2c13mux0ch5: i2c@5 {
- reg = <5>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch6: i2c@6 {
- reg = <6>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- i2c13mux0ch7: i2c@7 {
- reg = <7>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- nfc@28 {
- compatible = "nxp,nxp-nci-i2c";
- reg = <0x28>;
-
- interrupt-parent = <&sgpiom0>;
- interrupts = <156 IRQ_TYPE_LEVEL_HIGH>;
-
- enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>;
- };
- };
- };
-};
-
-// SCM
-&i2c14 {
- status = "okay";
-};
-
-&i2c15 {
- status = "okay";
-};
-
-&kcs2 {
- aspeed,lpc-io-reg = <0xca8>;
- status = "okay";
-};
-
-&kcs3 {
- aspeed,lpc-io-reg = <0xca2>;
- status = "okay";
-};
-
-&lpc_ctrl {
- status = "okay";
-};
-
-&mac2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ncsi3_default>;
- use-ncsi;
-};
-
-&sgpiom0 {
- ngpios = <128>;
- bus-frequency = <2000000>;
- gpio-line-names =
- /*in - out - in - out */
- /* A0-A7 line 0-15 */
- "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
- "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
- "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
- "", "", "", "",
-
- /* B0-B7 line 16-31 */
- "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
- "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
- "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
- "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
- "Channel4_leakage_Manifold2", "",
- "Channel5_leakage_EAM1", "",
- "Channel6_leakage_CPU_DIMM", "",
- "Channel7_leakage_EAM2", "",
-
- /* C0-C7 line 32-47 */
- "RSVD_RMC_GPIO3", "", "", "",
- "", "", "", "",
- "LEAK_DETECT_RMC_N", "", "", "",
- "", "", "", "",
-
- /* D0-D7 line 48-63 */
- "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
- "AMC_BRD_PRSNT_CPLD_L", "", "", "",
- "", "", "", "",
-
- /* E0-E7 line 64-79 */
- "AMC_PDB_EAMHSC0_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC1_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC2_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC3_CPLD_EN_R", "",
- "", "", "", "",
- "", "", "", "",
-
- /* F0-F7 line 80-95 */
- "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY",
- "PWRGD_PVDDCR_CPU0_P0", "",
- "", "", "", "",
- "", "", "", "",
-
- /* G0-G7 line 96-111 */
- "PWRGD_PVDDCR_SOC_P0", "",
- "PWRGD_PVDDIO_P0", "",
- "PWRGD_PVDDIO_MEM_S3_P0", "",
- "PWRGD_CHMP_CPU0_FPGA", "",
- "PWRGD_CHIL_CPU0_FPGA", "",
- "PWRGD_CHEH_CPU0_FPGA", "",
- "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
- "", "",
-
- /* H0-H7 line 112-127 */
- "PWRGD_P3V3", "",
- "P12V_DDR_IP_PWRGD_R", "",
- "P12V_DDR_AH_PWRGD_R", "",
- "PWRGD_P12V_VRM1_CPLD_PG_R", "",
- "PWRGD_P12V_VRM0_CPLD_PG_R", "",
- "PWRGD_PDB_HSC4_CPLD_PG_R", "",
- "PWRGD_PVDD18_S5_P0_PG", "",
- "PWRGD_PVDD33_S5_P0_PG", "",
-
- /* I0-I7 line 128-143 */
- "EAM0_BRD_PRSNT_R_L", "",
- "EAM1_BRD_PRSNT_R_L", "",
- "EAM2_BRD_PRSNT_R_L", "",
- "EAM3_BRD_PRSNT_R_L", "",
- "EAM0_CPU_MOD_PWR_GD_R", "",
- "EAM1_CPU_MOD_PWR_GD_R", "",
- "EAM2_CPU_MOD_PWR_GD_R", "",
- "EAM3_CPU_MOD_PWR_GD_R", "",
-
- /* J0-J7 line 144-159 */
- "PRSNT_L_BIRDGE_R", "",
- "PRSNT_R_BIRDGE_R", "",
- "BRIDGE_L_MAIN_PG_R", "",
- "BRIDGE_R_MAIN_PG_R", "",
- "BRIDGE_L_STBY_PG_R", "",
- "BRIDGE_R_STBY_PG_R", "",
- "", "", "", "",
-
- /* K0-K7 line 160-175 */
- "ADC_I2C_ALERT_N", "",
- "TEMP_I2C_ALERT_R_L", "",
- "CPU0_VR_SMB_ALERT_CPLD_N", "",
- "COVER_INTRUDER_R_N", "",
- "HANDLE_INTRUDER_CPLD_N", "",
- "IRQ_MCIO_CPLD_WAKE_R_N", "",
- "APML_CPU0_ALERT_R_N", "",
- "PDB_ALERT_R_N", "",
-
- /* L0-L7 line 176-191 */
- "CPU0_SP7R1", "", "CPU0_SP7R2", "",
- "CPU0_SP7R3", "", "CPU0_SP7R4", "",
- "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
- "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
-
- /* M0-M7 line 192-207 */
- "EAM0_SMERR_CPLD_R_L", "",
- "EAM1_SMERR_CPLD_R_L", "",
- "EAM2_SMERR_CPLD_R_L", "",
- "EAM3_SMERR_CPLD_R_L", "",
- "CPU0_SMERR_N_R", "",
- "CPU0_NV_SAVE_N_R", "",
- "PDB_PWR_LOSS_CPLD_N", "",
- "IRQ_BMC_SMI_ACTIVE_R_N", "",
-
- /* N0-N7 line 208-223 */
- "AMCROT_BMC_S5_RDY_R", "",
- "AMC_RDY_R", "",
- "AMC_STBY_PGOOD_R", "",
- "CPU_AMC_SLP_S5_R_L", "",
- "AMC_CPU_EAMPG_R", "",
- "", "", "", "",
-
- /* O0-O7 line 224-239 */
- "HPM_PWR_FAIL", "Port80_b0",
- "FM_DIMM_IP_FAIL", "Port80_b1",
- "FM_DIMM_AH_FAIL", "Port80_b2",
- "HPM_AMC_THERMTRIP_R_L", "Port80_b3",
- "FM_CPU0_THERMTRIP_N", "Port80_b4",
- "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
- "CPLD_SGPIO_RDY", "Port80_b6",
- "", "Port80_b7",
-
- /* P0-P7 line 240-255 */
- "CPU0_SLP_S5_N_R", "NFC_VEN",
- "CPU0_SLP_S3_N_R", "",
- "FM_CPU0_PWRGD", "",
- "PWRGD_RMC", "",
- "FM_RST_CPU0_RESET_N", "",
- "FM_PWRGD_CPU0_PWROK", "",
- "wS5_PWR_Ready", "",
- "wS0_ON_N", "PWRGD_P1V0_AUX";
- status = "okay";
-};
-
-// BIOS Flash
-&spi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2_default>;
- status = "okay";
- reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- label = "pnor";
- spi-max-frequency = <12000000>;
- spi-tx-bus-width = <2>;
- spi-rx-bus-width = <2>;
- status = "okay";
- };
-};
-
-// HOST BIOS Debug
-&uart1 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-// BMC Debug Console
-&uart5 {
- status = "okay";
-};
-
-&uart_routing {
- status = "okay";
-};
-
-&uhci {
- status = "okay";
-};
-
-&vhub {
- status = "okay";
- pinctrl-names = "default";
-};
-
-&video {
- status = "okay";
- memory-region = <&video_engine_memory>;
-};
-
-&wdt1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdtrst1_default>;
- aspeed,reset-type = "soc";
- aspeed,external-signal;
- aspeed,ext-push-pull;
- aspeed,ext-active-high;
- aspeed,ext-pulse-duration = <256>;
- status = "okay";
-};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/3] dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 board
From: Colin Huang @ 2026-04-09 11:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
In-Reply-To: <20260409-anacapa-devlop-phase-devicetree-v2-0-68f328671653@gmail.com>
Document Anacapa BMC EVT1 and EVT2 compatibles.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 8ec7a3e74a21..c4b87c014941 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -84,6 +84,8 @@ properties:
- asus,ast2600-kommando-ipmi-card
- asus,x4tf-bmc
- facebook,anacapa-bmc
+ - facebook,anacapa-bmc-evt1
+ - facebook,anacapa-bmc-evt2
- facebook,bletchley-bmc
- facebook,catalina-bmc
- facebook,clemente-bmc
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/3] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase
From: Colin Huang @ 2026-04-09 11:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang
This series refactors the Anacapa BMC devicetree layout to better support
development-phase hardware revisions (EVT1/EVT2) while keeping a platform
entrypoint.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
Changes in v2:
- Fix dtbs_check fail.
Validated by following command:
make dt_binding_check DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa.dtb
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt1.dtb
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt2.dtb
- Link to v1: https://lore.kernel.org/r/20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com
---
Colin Huang (3):
dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 board
ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it
ARM: dts: aspeed: anacapa: add EVT2 devicetree and update wrapper
.../devicetree/bindings/arm/aspeed/aspeed.yaml | 2 +
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1067 +++++++++++++++++++
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 1123 ++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1064 +------------------
4 files changed, 2193 insertions(+), 1063 deletions(-)
---
base-commit: cd44dc5ead3042f2873244b0598e39a16dc7b940
change-id: 20260407-anacapa-devlop-phase-devicetree-4101d3f312c0
Best regards,
--
Colin Huang <u8813345@gmail.com>
^ permalink raw reply
* Re: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Manivannan Sadhasivam @ 2026-04-09 11:26 UTC (permalink / raw)
To: Joe Sandom
Cc: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20260409100455.foytyzse3k5ty55l@linaro>
On Thu, Apr 09, 2026 at 11:04:55AM +0100, Joe Sandom wrote:
> On Tue, Apr 07, 2026 at 09:44:34PM +0530, Manivannan Sadhasivam wrote:
> > On Tue, Apr 07, 2026 at 12:39:25PM +0100, Joe Sandom wrote:
> >
> > [...]
> >
> > > > > +&pcie0 {
> > > > > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> > > > > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> > > > > +
> > > > > + pinctrl-0 = <&pcie0_default_state>;
> > > > > + pinctrl-names = "default";
> > > > > +
> > > > > + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> > > > > + <0x100 &apps_smmu 0x1401 0x1>,
> > > > > + <0x208 &apps_smmu 0x1402 0x1>,
> > > > > + <0x210 &apps_smmu 0x1403 0x1>,
> > > > > + <0x218 &apps_smmu 0x1404 0x1>,
> > > > > + <0x300 &apps_smmu 0x1407 0x1>,
> > > > > + <0x400 &apps_smmu 0x1408 0x1>,
> > > > > + <0x500 &apps_smmu 0x140c 0x1>,
> > > > > + <0x501 &apps_smmu 0x140e 0x1>;
> > > > > +
> > > > > + /delete-property/ msi-map;
> > > >
> > > > Why?
> > > I tried extending the msi-map to cover the RIDs from the QPS615
> > > PCIe switch (matching the iommu-map entries), but this caused
> > > ITS MAPD command timeouts.
> >
> > I'm not aware of any specific issue with ITS on this chipset. At what time did
> > you see the timeout? During probe?
> So when I set msi-map to match the iommu-map entries, I got this;
> [ 0.000000] ITS [mem 0x17140000-0x1717ffff]
> [ 11.085152] ath12k_wifi7_pci 0001:04:00.0: BAR 0 assigned
> [ 11.115762] ath12k_wifi7_pci 0001:04:00.0: Wi-Fi 7 Hardware name: wcn7850 hw2.0
> [ 11.153632] ath12k_wifi7_pci 0001:04:00.0: MSI vectors: 16
> [ 11.252398] mhi mhi0: Requested to power ON
> .........
> [ 101.596274] mhi mhi0: Wait for device to enter SBL or Mission mode
> [ 101.603098] ath12k_wifi7_pci 0001:04:00.0: failed to set mhi state: POWER_ON(2)
> [ 101.610632] ath12k_wifi7_pci 0001:04:00.0: failed to start mhi: -110
> [ 101.617171] ath12k_wifi7_pci 0001:04:00.0: failed to power up :-110
> [ 101.794431] ath12k_wifi7_pci 0001:04:00.0: probe failed with error -110
> [ 103.158872] ITS queue timeout (12640 12609)
> [ 103.163183] ITS cmd its_build_mapd_cmd failed
>
> With msi-map removed, I got this;
> [ 11.469642] ath12k_wifi7_pci 0001:04:00.0: BAR 0 assigned
> [ 11.490059] ath12k_wifi7_pci 0001:04:00.0: Wi-Fi 7 Hardware name: wcn7850 hw2.0
> [ 11.497787] ath12k_wifi7_pci 0001:04:00.0: MSI vectors: 16
> [ 11.559958] mhi mhi0: Requested to power ON
> [ 11.567375] mhi mhi0: Power on setup success
> [ 11.693069] mhi mhi0: Wait for device to enter SBL or Mission mode
> [ 12.185946] ath12k_wifi7_pci 0001:04:00.0: chip_id 0x2 ... soc_id 0x40170200
> [ 12.482168] ath12k_wifi7_pci 0001:04:00.0 wlP1p4s0: renamed from wlan0
Thanks for the logs. I also checked internally and learned that the timeout is
due to Gunyah limiting the devices per-port. On SM8550, it currently only
allows 2 devices per RC instance to save the memory footprint. So when you
connect a PCIe switch which exposes more than two devices (1 USP + (1+) DSPs),
you'll run out of ITS mapping in Gunyah, leading to these timeouts.
So either you need to modify Gunyah to allow more devices per-port or switch to
iMSI-RX which you are already doing.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Konrad Dybcio @ 2026-04-09 11:24 UTC (permalink / raw)
To: Joe Sandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260409112309.vaibvwsmfdjardvy@linaro>
On 4/9/26 1:23 PM, Joe Sandom wrote:
> On Wed, Apr 08, 2026 at 11:57:18AM +0200, Konrad Dybcio wrote:
>> On 4/7/26 5:46 PM, Joe Sandom via B4 Relay wrote:
>>> From: Joe Sandom <jsandom@axon.com>
[...]
>>> + can@0 {
>>> + compatible = "microchip,mcp2518fd";
>>> + reg = <0>;
>>> + interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>;
>>> + clocks = <&clk40m>;
>>> + spi-max-frequency = <10000000>;
>>> + vdd-supply = <&vreg_l14b_3p2>;
>>> + xceiver-supply = <&vreg_l14b_3p2>;
>>
>> It may be that for this chip to actually be able to communiate with devices
>> on the bus, you need to set the new 'microchip,xstbyen' property
>>
>> see:
>>
>> https://urldefense.com/v3/__https://lore.kernel.org/linux-arm-msm/20260321135031.3107408-1-viken.dadhaniya@oss.qualcomm.com/__;!!K76kBA!3JvIWVouSl6ZkbxojAFYUus-8UPRvjrHx0qENKOyIIBpZ9knecOfH0NCBAr8ESxNXg2H6982UXqs_8QyR_k9NuKnmA$
>>
> Good to know. Confirmed that it will be needed.
> Happy to provide a follow-up patch once the above series lands if that
> works for you?
Sure thing, thanks for confirming!
Konrad
^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Joe Sandom @ 2026-04-09 11:23 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <4359bb07-d848-4b77-b1a9-f1c6f53caa10@oss.qualcomm.com>
On Wed, Apr 08, 2026 at 11:57:18AM +0200, Konrad Dybcio wrote:
> On 4/7/26 5:46 PM, Joe Sandom via B4 Relay wrote:
> > From: Joe Sandom <jsandom@axon.com>
> >
> > The RB5gen2 is an embedded development platform for the
> > QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
>
> [...]
>
>
> > + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */
> > + /* Workaround is to use bit-banged I2C */
>
> Interesting.. I was under the impression that it was only an issue on
> RB1 and RB2 boards.. perhaps we're missing some magic register write..
>
>
> [...]
>
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>,
> > + <&pmk8550_sleep_clk>;
>
> nit: let's keep the order of
>
> property-n
> property-names
>
> file-wide
>
Agree. Good catch - will amend this in v3.
> [...]
>
> > +&sdhc_2 {
> > + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
> > +
> > + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
> > + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
> > + pinctrl-names = "default", "sleep";
> > +
> > + vmmc-supply = <&vreg_l9b_2p9>;
> > + vqmmc-supply = <&vreg_l8b_1p8>;
> > +
> > + max-sd-hs-hz = <37000000>;
>
> Are you sure you want to overwrite that? The value in the SoC DTSI is
> set to half a MHz higher
This was originally carried over from the downstream workaround for
clock driver ceiling behaviour that I saw;
/*
* Due to level shifter insertion, HS mode frequency is reduced to 37.5MHz
* but clk's driver supply 37MHz only and uses ceil ops. So vote for
* 37MHz to avoid picking next ceil value.
*/
#define LEVEL_SHIFTER_HIGH_SPEED_FREQ 37000000
But I now realise this isn't an issue in the upstream driver, so I will
drop this in v3. Thanks!
>
> > +
> > + no-sdio;
> > + no-mmc;
> > +
> > + status = "okay";
> > +};
> > +
> > +&sleep_clk {
> > + clock-frequency = <32764>;
> > +};
> > +
> > +&spi11 {
> > + status = "okay";
> > +
> > + can@0 {
> > + compatible = "microchip,mcp2518fd";
> > + reg = <0>;
> > + interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clk40m>;
> > + spi-max-frequency = <10000000>;
> > + vdd-supply = <&vreg_l14b_3p2>;
> > + xceiver-supply = <&vreg_l14b_3p2>;
>
> It may be that for this chip to actually be able to communiate with devices
> on the bus, you need to set the new 'microchip,xstbyen' property
>
> see:
>
> https://urldefense.com/v3/__https://lore.kernel.org/linux-arm-msm/20260321135031.3107408-1-viken.dadhaniya@oss.qualcomm.com/__;!!K76kBA!3JvIWVouSl6ZkbxojAFYUus-8UPRvjrHx0qENKOyIIBpZ9knecOfH0NCBAr8ESxNXg2H6982UXqs_8QyR_k9NuKnmA$
>
Good to know. Confirmed that it will be needed.
Happy to provide a follow-up patch once the above series lands if that
works for you?
> [...]
>
> > +&tlmm {
> > + gpio-reserved-ranges = <32 8>;
>
> Would you happen to know what these pins are connected to, and if
> so, add a comment (like in arch/arm64/boot/dts/qcom/x1-crd.dtsi)?
Yes, 32-35 for NFC and 36-39 for fingerprint sensor. I'll add a comment
in v3 so it's clear.
>
>
> > +
> > + bt_default: bt-default-state {
> > + pins = "gpio81";
>
> It would be best to keep these entries ordered by pin idx
Fair point. Will amend this for v3.
>
> > + function = "gpio";
> > + drive-strength = <16>;
> > + bias-disable;
> > + };
> > +
> > + sw_ctrl_default: sw-ctrl-default-state {
> > + pins = "gpio82";
> > + function = "gpio";
> > + bias-pull-down;
> > + };
> > +
> > + lt9611_irq_pin: lt9611-irq-state {
> > + pins = "gpio40";
> > + function = "gpio";
> > + bias-disable;
> > + };
> > +
> > + lt9611_rst_pin: lt9611-rst-state {
> > + pins = "gpio7";
> > + function = "gpio";
> > + output-high;
>
> You shouldn't need to assert the GPIO state in the pin entry node
> - the driver should take care of that
Fair point. Will amend this for v3.
>
>
> > + };
> > +
> > + ntn0_en: ntn0-en-state {
> > + pins = "gpio67";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-disable;
> > + };
> > +
> > + ntn1_en: ntn1-en-state {
> > + pins = "gpio42";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-disable;
> > + };
> > +
> > + upd_1p05_en: upd-1p05-en-state {
> > + pins = "gpio179";
> > + function = "gpio";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
>
> I don't know if pulling up an active-high pin is what you want
> (there's some more occurences)
>
Good point. Will amend this for v3.
> Konrad
^ permalink raw reply
* Re: [PATCH v6 10/21] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC
From: Tommaso Merciai @ 2026-04-09 11:15 UTC (permalink / raw)
To: Laurent Pinchart
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <20260408150053.GC1965119@killaraus.ideasonboard.com>
Hi Laurent,
Thanks for your comments.
On 4/8/26 17:00, Laurent Pinchart wrote:
> On Wed, Apr 08, 2026 at 04:44:48PM +0200, Tommaso Merciai wrote:
>> On 4/8/26 16:16, Laurent Pinchart wrote:
>>> On Wed, Apr 08, 2026 at 04:02:14PM +0200, Tommaso Merciai wrote:
>>>> On 4/8/26 14:24, Laurent Pinchart wrote:
>>>>> On Wed, Apr 08, 2026 at 12:36:55PM +0200, Tommaso Merciai wrote:
>>>>>> The RZ/G3E SoC has 2 LCD controllers (LCDC), each containing a Frame
>>>>>> Compression Processor (FCPVD), a Video Signal Processor (VSPD), and a
>>>>>> Display Unit (DU).
>>>>>>
>>>>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
>>>>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
>>>>>>
>>>>>> Add a new SoC-specific compatible string 'renesas,r9a09g047-du'.
>>>>>>
>>>>>> Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" to
>>>>>> allow up to four output ports, and explicitly disable port@2 and port@3
>>>>>> for existing SoCs that do not expose them.
>>>>>>
>>>>>> Describe the four output ports of the RZ/G3E DU:
>>>>>>
>>>>>> - port@0: DSI (available on both LCDC instances)
>>>>>> - port@1: DPAD / parallel RGB (LCDC1 only)
>>>>>> - port@2: LVDS channel 0 (LCDC0 only)
>>>>>> - port@3: LVDS channel 1 (available on both LCDC instances)
>>>>>>
>>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>>>>>> ---
>>>>>> v5->v6:
>>>>>> - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
>>>>>> explicitly disable port@2 and port@3 for existing SoCs that do not expose
>>>>>> them.
>>>>>> - Reworked ports numbering + improved/fixed ports descriptions in the
>>>>>> bindings documentation.
>>>>>> - Improved commit body.
>>>>>>
>>>>>> v4->v5:
>>>>>> - Dropped renesas,id property and updated bindings
>>>>>> accordingly.
>>>>>>
>>>>>> v2->v3:
>>>>>> - No changes.
>>>>>>
>>>>>> v2->v3:
>>>>>> - No changes.
>>>>>>
>>>>>> v1->v2:
>>>>>> - Use single compatible string instead of multiple compatible strings
>>>>>> for the two DU instances, leveraging a 'renesas,id' property to
>>>>>> differentiate between DU0 and DU1.
>>>>>> - Updated commit message accordingly.
>>>>>>
>>>>>> .../bindings/display/renesas,rzg2l-du.yaml | 30 ++++++++++++++++++-
>>>>>> 1 file changed, 29 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
>>>>>> index 5add3b832eab..32da0b5ec88c 100644
>>>>>> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
>>>>>> @@ -20,6 +20,7 @@ properties:
>>>>>> - enum:
>>>>>> - renesas,r9a07g043u-du # RZ/G2UL
>>>>>> - renesas,r9a07g044-du # RZ/G2{L,LC}
>>>>>> + - renesas,r9a09g047-du # RZ/G3E
>>>>>> - renesas,r9a09g057-du # RZ/V2H(P)
>>>>>> - items:
>>>>>> - enum:
>>>>>> @@ -61,7 +62,7 @@ properties:
>>>>>> model-dependent. Each port shall have a single endpoint.
>>>>>>
>>>>>> patternProperties:
>>>>>> - "^port@[0-1]$":
>>>>>> + "^port@[0-3]$":
>>>>>> $ref: /schemas/graph.yaml#/properties/port
>>>>>> unevaluatedProperties: false
>>>>>>
>>>>>> @@ -103,6 +104,8 @@ allOf:
>>>>>> port@0:
>>>>>> description: DPI
>>>>>> port@1: false
>>>>>> + port@2: false
>>>>>> + port@3: false
>>>>>>
>>>>>> required:
>>>>>> - port@0
>>>>>> @@ -119,6 +122,8 @@ allOf:
>>>>>> description: DSI
>>>>>> port@1:
>>>>>> description: DPI
>>>>>> + port@2: false
>>>>>> + port@3: false
>>>>>>
>>>>>> required:
>>>>>> - port@0
>>>>>> @@ -135,9 +140,32 @@ allOf:
>>>>>> port@0:
>>>>>> description: DSI
>>>>>> port@1: false
>>>>>> + port@2: false
>>>>>> + port@3: false
>>>>>>
>>>>>> required:
>>>>>> - port@0
>>>>>> + - if:
>>>>>> + properties:
>>>>>> + compatible:
>>>>>> + contains:
>>>>>> + const: renesas,r9a09g047-du
>>>>>> + then:
>>>>>> + properties:
>>>>>> + ports:
>>>>>> + properties:
>>>>>> + port@0:
>>>>>> + description: DSI
>>>>>> + port@1:
>>>>>> + description: DPAD
>>>>>> + port@2:
>>>>>> + description: LVDS, Channel 0
>>>>>> + port@3:
>>>>>> + description: LVDS, Channel 1
>>>>>> +
>>>>>> + required:
>>>>>> + - port@0
>>>>>> + - port@3
>>>>>
>>>>> Why are ports 1 and 2 not required ?
>>>>
>>>> About this we had a similar discussion on v5[0]
>>>> We are using the same compatible and:
>>>>
>>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
>>>> |
>>>> --> then has:
>>>> port@0
>>>> port@2
>>>> port@3
>>>>
>>>>
>>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
>>>> |
>>>> --> then has:
>>>> port@0
>>>> port@1
>>>> port@3
>>>
>>> Ah yes, I forget there are two LCDC instances with different output
>>> configurations.
>>>
>>> Something still looks a bit weird to me though. For LCDC1, which
>>> supports a single LVDS channel, you use the port described as the second
>>> LVDS channel. Is there a reason not to use port@2 ?
>>
>> 9.11 Low Voltage Differential Signaling (LVDS)
>> 9.11.1.2 Block Diagram
>> Figure 9.11-1 shows a block diagram of LVDS.
>>
>> LCDC1 is connected to LVDS, Channel 1
>> For this reason I'm using port@3.
>
> Re-reading that, I think I've misinterpreted the hardware architecture.
> Doesn't the DU have a single output, that is connected the multiple
> encoders (LVDS and DSI for LCDC0 and LVDS, DSI and DPI for LCDC1) ? It
> seems modelling it with a single port and multiple endpoints would
> better match the device.
>
> For LVDS in particular, I see a single LVDS encoder with two channels,
> so there should not be two LVDS output ports in the DU. The two ports
> should be on the output of the LVDS device.
You are suggesting the following dt architecture:
du0: display@16460000 {
compatible = "renesas,r9a09g047-du";
reg = <0 0x16460000 0 0x10000>;
interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0xed>,
<&cpg CPG_MOD 0xee>,
<&cpg CPG_MOD 0xef>;
clock-names = "aclk", "pclk", "vclk";
power-domains = <&cpg>;
resets = <&cpg 0xdc>;
renesas,vsps = <&vspd0 0>;
status = "disabled";
port {
du0_out_dsi: endpoint@0 {
reg = <0>;
};
du0_out_lvds0: endpoint@2 {
reg = <2>;
};
du0_out_lvds1: endpoint@3 {
reg = <3>;
};
}
};
du1: display@16490000 {
compatible = "renesas,r9a09g047-du";
reg = <0 0x16490000 0 0x10000>;
interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 0x1a8>,
<&cpg CPG_MOD 0x1a9>,
<&cpg CPG_MOD 0x1aa>;
clock-names = "aclk", "pclk", "vclk";
power-domains = <&cpg>;
resets = <&cpg 0x11e>;
renesas,vsps = <&vspd1 0>;
status = "disabled";
port {
du1_out_dsi: endpoint@0 {
reg = <0>;
};
du1_out_rgb: endpoint@1 {
reg = <1>;
};
du1_out_lvds1: endpoint@3 {
reg = <3>;
};
}
};
Please correct me if I'm wrong.
Kind Regards,
Tommaso
>
>>>> Then port@1 is required for DU1 but not for DU0.
>>>> Same port@2 is required for DU0 but not for DU1.
>>>>
>>>> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/ca022fdbba5236c36e0cb3095db4c31e8e0cb1b8.1770996493.git.tommaso.merciai.xr@bp.renesas.com/
>>>>
>>>>>>
>>>>>> examples:
>>>>>> # RZ/G2L DU
>
^ permalink raw reply
* Re: [PATCH v6 13/21] drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature
From: Tommaso Merciai @ 2026-04-09 11:14 UTC (permalink / raw)
To: Laurent Pinchart
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <20260408150807.GD1965119@killaraus.ideasonboard.com>
Hi Laurent,
Thanks for your comments.
On 4/8/26 17:08, Laurent Pinchart wrote:
> On Wed, Apr 08, 2026 at 04:58:01PM +0200, Tommaso Merciai wrote:
>> On 4/8/26 16:17, Laurent Pinchart wrote:
>>> On Wed, Apr 08, 2026 at 04:12:22PM +0200, Tommaso Merciai wrote:
>>>> On 4/8/26 14:31, Laurent Pinchart wrote:
>>>>> On Wed, Apr 08, 2026 at 12:36:58PM +0200, Tommaso Merciai wrote:
>>>>>> The MIPI DSI ip found in the RZ/G3E SoC select the video input clock
>>>>>> based on the DU instance actually connected using the GPO0R register.
>>>>>>
>>>>>> Add this feature to the driver using `RZ_MIPI_DSI_FEATURE_GPO0R`, update
>>>>>> the code accordingly to manage the vclk selection with the introduction
>>>>>> of `rzg2l_mipi_dsi_get_input_port()`.
>>>>>>
>>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>>>>>> ---
>>>>>> v5->v6:
>>>>>> - Moved rzg2l_mipi_dsi_link_write() into rzv2h_mipi_dsi_dphy_init()
>>>>>> + comments from HW Manual.
>>>>>>
>>>>>> v4->v5:
>>>>>> - No changes.
>>>>>>
>>>>>> v3->v4:
>>>>>> - No changes.
>>>>>>
>>>>>> v2->v3:
>>>>>> - No changes.
>>>>>>
>>>>>> v1->v2:
>>>>>> - No changes.
>>>>>>
>>>>>> .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 71 +++++++++++++++++--
>>>>>> .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 3 +
>>>>>> 2 files changed, 68 insertions(+), 6 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
>>>>>> index be6dbf19a24e..947c8e15fc4b 100644
>>>>>> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
>>>>>> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
>>>>>> @@ -37,7 +37,9 @@ MODULE_IMPORT_NS("RZV2H_CPG");
>>>>>>
>>>>>> #define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */
>>>>>>
>>>>>> +#define RZ_MIPI_DSI_MAX_INPUT 2
>>>>>> #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0)
>>>>>> +#define RZ_MIPI_DSI_FEATURE_GPO0R BIT(1)
>>>>>>
>>>>>> struct rzg2l_mipi_dsi;
>>>>>>
>>>>>> @@ -81,13 +83,14 @@ struct rzg2l_mipi_dsi {
>>>>>> struct drm_bridge bridge;
>>>>>> struct drm_bridge *next_bridge;
>>>>>>
>>>>>> - struct clk *vclk;
>>>>>> + struct clk *vclk[RZ_MIPI_DSI_MAX_INPUT];
>>>>>> struct clk *lpclk;
>>>>>>
>>>>>> enum mipi_dsi_pixel_format format;
>>>>>> unsigned int num_data_lanes;
>>>>>> unsigned int lanes;
>>>>>> unsigned long mode_flags;
>>>>>> + u8 vclk_idx;
>>>>>>
>>>>>> struct rzv2h_dsi_mode_calc mode_calc;
>>>>>>
>>>>>> @@ -543,8 +546,8 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_f
>>>>>> unsigned long vclk_rate;
>>>>>> unsigned int bpp;
>>>>>>
>>>>>> - clk_set_rate(dsi->vclk, mode_freq * KILO);
>>>>>> - vclk_rate = clk_get_rate(dsi->vclk);
>>>>>> + clk_set_rate(dsi->vclk[dsi->vclk_idx], mode_freq * KILO);
>>>>>> + vclk_rate = clk_get_rate(dsi->vclk[dsi->vclk_idx]);
>>>>>> if (vclk_rate != mode_freq * KILO)
>>>>>> dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
>>>>>> mode_freq * KILO, vclk_rate);
>>>>>> @@ -687,6 +690,19 @@ static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
>>>>>> rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R,
>>>>>> FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k));
>>>>>>
>>>>>> + /*
>>>>>> + * From RZ/G3E HW manual (Rev.1.15) section 9.5.3 Operation,
>>>>>> + * 9.5.3.1 Power on Reset and Initial Settings for All Operations.
>>>>>> + * Figure 9.5-4 Power On/Off Sequence show that after writing to
>>>>>> + * GPO0R.VICH register we need to wait for more than 1 x tp before
>>>>>> + * writing to PLLENR.PLLEN.
>>>>>> + *
>>>>>> + * Note: GPO0R is a link register, not a PHY register. This setting
>>>>>> + * is specific to RZ/G3E.
>>>>>> + */
>>>>>> + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_GPO0R)
>>>>>> + rzg2l_mipi_dsi_link_write(dsi, GPO0R, dsi->vclk_idx);
>>>>>> +
>>>>>> /*
>>>>>> * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
>>>>>> * (C) After write to D-PHY registers we need to wait for more than 1 x tp
>>>>>> @@ -1005,6 +1021,37 @@ static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
>>>>>> return ret;
>>>>>> }
>>>>>>
>>>>>> +static int rzg2l_mipi_dsi_get_input_port(struct rzg2l_mipi_dsi *dsi)
>>>>>> +{
>>>>>> + struct device_node *np = dsi->dev->of_node;
>>>>>> + struct device_node *remote_ep, *ep_node;
>>>>>> + struct of_endpoint ep;
>>>>>> + bool ep_enabled;
>>>>>> + int in_port;
>>>>>> +
>>>>>> + /* DSI can have only one port enabled */
>>>>>
>>>>> Why is that ? The hardware supports dynamic input selection, why can't
>>>>> it be supported at runtime ?
>>>>
>>>> For runtime/dynamic you mean using DT overlay??
>>>> like, remove:
>>>>
>>>> Removing - DU0 --> DSI (input 0 | port@0 ) overlay and
>>>> install - DU1 --> DSI (input 1 | port@1 ) overlay and
>>>> viceversa?
>>>
>>> No, I mean configurable by userspace, with two CRTCs sharing one DSI
>>> encoder.
>>
>> Sorry, question:
>> - Is it possible to create CRTC from user space?
>
> No, the CRTCs are created by the driver, but you can have one DRM device
> that covers two LCDCs, with one CRTC each, both connected to the same
> DSI encoder (and apparently this applies to the LVDS encoder too).
> Userspace then selects which CRTC drives which connector.
Which user space tool would you suggest I use for testing this?
And also, which user space tool is the user supposed to use at
runtime on his final/production system to perform that selection?
Kind Regards,
Tommaso
>
>> From hardware point only one DSI input is selectable out of 2 LCDC's at
>> a time.
>>
>> References:
>> - 9.5.2.2.3 9.5 MIPI DSI Interface (DSI)
>> General Purpose Output 0 Register (DSI_LINK_GPO0R)
>>
>> - 9.5 MIPI DSI Interface (DSI)
>> 9.5.1.2 Block Diagram
>> Figure 9.5-1 Video Input Interface
>>
>>>>>> + for_each_endpoint_of_node(np, ep_node) {
>>>>>> + of_graph_parse_endpoint(ep_node, &ep);
>>>>>> + if (ep.port >= RZ_MIPI_DSI_MAX_INPUT)
>>>>>> + break;
>>>>>> +
>>>>>> + remote_ep = of_graph_get_remote_endpoint(ep_node);
>>>>>> + ep_enabled = of_device_is_available(remote_ep);
>>>>>> + of_node_put(remote_ep);
>>>>>> +
>>>>>> + if (ep_enabled) {
>>>>>> + in_port = ep.port;
>>>>>> + break;
>>>>>> + }
>>>>>> + }
>>>>>> +
>>>>>> + if (!ep_enabled)
>>>>>> + return -EINVAL;
>>>>>> +
>>>>>> + dev_dbg(dsi->dev, "input port@%d\n", in_port);
>>>>>> + return in_port;
>>>>>> +}
>>>>>> +
>>>>>> /* -----------------------------------------------------------------------------
>>>>>> * Bridge
>>>>>> */
>>>>>> @@ -1425,9 +1472,21 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>>>>>> if (IS_ERR(dsi->mmio))
>>>>>> return PTR_ERR(dsi->mmio);
>>>>>>
>>>>>> - dsi->vclk = devm_clk_get(dsi->dev, "vclk");
>>>>>> - if (IS_ERR(dsi->vclk))
>>>>>> - return PTR_ERR(dsi->vclk);
>>>>>> + dsi->vclk[0] = devm_clk_get(dsi->dev, "vclk");
>>>>>> + if (IS_ERR(dsi->vclk[0]))
>>>>>> + return PTR_ERR(dsi->vclk[0]);
>>>>>> +
>>>>>> + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_GPO0R) {
>>>>>> + dsi->vclk[1] = devm_clk_get(dsi->dev, "vclk2");
>>>>>> + if (IS_ERR(dsi->vclk[1]))
>>>>>> + return PTR_ERR(dsi->vclk[1]);
>>>>>> +
>>>>>> + ret = rzg2l_mipi_dsi_get_input_port(dsi);
>>>>>> + if (ret < 0)
>>>>>> + return dev_err_probe(dsi->dev, -EINVAL,
>>>>>> + "No available input port\n");
>>>>>> + dsi->vclk_idx = ret;
>>>>>> + }
>>>>>>
>>>>>> dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
>>>>>> if (IS_ERR(dsi->lpclk))
>>>>>> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
>>>>>> index 2bef20566648..cee2e0bc5dc5 100644
>>>>>> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
>>>>>> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
>>>>>> @@ -83,6 +83,9 @@
>>>>>> #define LINKSR_SQCHRUN1 BIT(4)
>>>>>> #define LINKSR_SQCHRUN0 BIT(0)
>>>>>>
>>>>>> +/* RZ/G3E General Purpose Output 0 Register */
>>>>>> +#define GPO0R 0xc0
>>>>>> +
>>>>>> /* Tx Set Register */
>>>>>> #define TXSETR 0x100
>>>>>> #define TXSETR_NUMLANECAP (0x3 << 16)
>
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-04-09 11:14 UTC (permalink / raw)
To: Andrew Lunn
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Yazan Shhady, Mikhail Anikin, Alexander Dahl,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org
In-Reply-To: <3024c143-520e-49ea-af17-33344ebf7149@lunn.ch>
Hi Andrew,
Am 08.04.26 um 22:12 schrieb Andrew Lunn:
>> +&eqos {
>> + phy-mode = "rgmii-id";
>> + pinctrl-0 = <&eqos_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + fixed-link {
>> + full-duplex;
>> + speed = <1000>;
>> + };
>> +};
>> + ethernet-switch@0 {
>> + compatible = "nxp,sja1110a";
> ....
>
>> +
>> + /* to CPU */
>> + port@2 {
>> + reg = <0x2>;
>> + ethernet = <&eqos>;
>> + label = "cpu";
>> + phy-mode = "rgmii-id";
>> + rx-internal-delay-ps = <2000>;
>> + tx-internal-delay-ps = <2000>;
> The eqos is using rgmii-id, this port is using rmgii-id, and you set
> the delays to 2000ns. How is this not resulting in 4000ns delays?
It appears that dwmac-imx driver which binds to imx8dxl eqos does not
evaluate phy-mode, unlike several other dwmac-* drivers.
This likely means that either imx8dxl eqos mac can't add delays,
or they are fixed.
The ethernet switch driver however adds delays as specified.
So we ended up with 2ns each direction as intended, and the network
connection works well (tested).
Would it be correct to change phy-mode on the mac to "rgmii",
and leave switch port as is?
sincerely
Josua Mayer
^ permalink raw reply
* [PATCH v2 1/1] ARM: dts: imx6ul: add #io-channel-cells to ADC
From: Alexander Stein @ 2026-04-09 11:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Markus Niebel, devicetree, imx, linux-arm-kernel, linux-kernel,
Alexander Stein
From: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Add #io-channel-cells property to the ADC node. This property is required
for an IIO consumer driver to work.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
Changes in v2:
* Use imperative wording in commit message
arch/arm/boot/dts/nxp/imx/imx6ul.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
index 24541fdf49ceb..d2bfa08b5e767 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
@@ -951,6 +951,7 @@ adc1: adc@2198000 {
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ADC1>;
clock-names = "adc";
+ #io-channel-cells = <1>;
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2 02/13] ACPICA: Read LVR from the I2C resource descriptor
From: Rafael J. Wysocki @ 2026-04-09 11:07 UTC (permalink / raw)
To: Akhil R
Cc: Alexandre Belloni, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rafael J . Wysocki, Robert Moore, Len Brown,
Guenter Roeck, Philipp Zabel, Eric Biggers, Sakari Ailus,
Wolfram Sang, Miquel Raynal, linux-i3c, devicetree, linux-kernel,
linux-acpi, acpica-devel, linux-hwmon
In-Reply-To: <20260409105747.48158-3-akhilrajeev@nvidia.com>
On Thu, Apr 9, 2026 at 12:59 PM Akhil R <akhilrajeev@nvidia.com> wrote:
>
> ACPI 6.3 specifies byte 8 of I2C Serial Bus Connection descriptor to be
> used for Legacy Virtual Register (LVR) data as specified in the MIPI
> I3C Specification for an I2C device connected to an I3C Host Controller.
> LVR will be read by I3C host controller drivers and it provides details
> about the specific speed and 50ns spike filter capabilities of I2C
> devices.
>
> Update the rsconvert_info to include this field. For I2C devices on an
> I2C bus, this field is Reserved and unused.
>
> This commit is the result of squashing the following:
> ACPICA commit 70082dc8fc847673ac7f4bbb1541776730f0b63e
> ACPICA commit e62e74baf7e08cf059ec82049aeccd565b24d661
> ACPICA commit c404118235108012cad396c834b5aabe2dd1b51a
> ACPICA commit 7650d4a889ea7907060bfce89f4f780ce83e7b28
> ACPICA commit 014fa9f2dbcc6b1bd42a4a4a6f6705d9cf7d460b
>
> Link: https://github.com/acpica/acpica/commit/70082dc8
> Link: https://github.com/acpica/acpica/commit/b3c38dc9
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org> # ACPI
> ---
> drivers/acpi/acpica/rsserial.c | 6 +++++-
> include/acpi/acrestyp.h | 1 +
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/acpi/acpica/rsserial.c b/drivers/acpi/acpica/rsserial.c
> index 279bfa27da94..c06e918ab889 100644
> --- a/drivers/acpi/acpica/rsserial.c
> +++ b/drivers/acpi/acpica/rsserial.c
> @@ -315,7 +315,7 @@ struct acpi_rsconvert_info acpi_rs_convert_csi2_serial_bus[14] = {
> *
> ******************************************************************************/
>
> -struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[17] = {
> +struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[18] = {
> {ACPI_RSC_INITGET, ACPI_RESOURCE_TYPE_SERIAL_BUS,
> ACPI_RS_SIZE(struct acpi_resource_i2c_serialbus),
> ACPI_RSC_TABLE_SIZE(acpi_rs_convert_i2c_serial_bus)},
> @@ -391,6 +391,10 @@ struct acpi_rsconvert_info acpi_rs_convert_i2c_serial_bus[17] = {
> AML_OFFSET(i2c_serial_bus.type_specific_flags),
> 0},
>
> + {ACPI_RSC_MOVE8, ACPI_RS_OFFSET(data.i2c_serial_bus.lvr),
> + AML_OFFSET(i2c_serial_bus.type_specific_flags) + 1,
> + 1},
> +
> {ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.i2c_serial_bus.connection_speed),
> AML_OFFSET(i2c_serial_bus.connection_speed),
> 1},
> diff --git a/include/acpi/acrestyp.h b/include/acpi/acrestyp.h
> index 842f932e2c2b..38a19b1d19ac 100644
> --- a/include/acpi/acrestyp.h
> +++ b/include/acpi/acrestyp.h
> @@ -423,6 +423,7 @@ struct acpi_resource_i2c_serialbus {
> ACPI_RESOURCE_SERIAL_COMMON u8 access_mode;
> u16 slave_address;
> u32 connection_speed;
> + u8 lvr;
> };
>
> /* Values for access_mode field above */
> --
> 2.50.1
>
>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox