* [PATCH v3 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
From: Joe Sandom via B4 Relay @ 2026-04-09 15:26 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260409-rb5gen2-dts-v3-0-be736355d4b4@axon.com>
From: Joe Sandom <jsandom@axon.com>
Add the MHI register regions to the pcie0 and pcie1 controller nodes
to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
via debugfs. The PCIe host driver uses this region to read the
link_transition_count from the MHI registers.
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..055ca931c04859f3a312eb9921aeb7a8cc676822 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1964,8 +1964,14 @@ pcie0: pcie@1c00000 {
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
- <0 0x60100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
@@ -2138,8 +2144,14 @@ pcie1: pcie@1c08000 {
<0x0 0x40000000 0x0 0xf1d>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
- <0x0 0x40100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c0b000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support
From: Joe Sandom via B4 Relay @ 2026-04-09 15:26 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Neil Armstrong, Dmitry Baryshkov, Krzysztof Kozlowski
This series adds device tree support for the Thundercomm RB5Gen2
development kit, based on the Qualcomm QCS8550 chipset.
Patches 1-3 prepares for the RB5gen2 device tree by adding MHI register
regions and port labels to the PCIe controller nodes, as well as moving
common IPA properties into sm8550.dtsi. Then update the existing HDK
and QRD board files accordingly.
Patches 4-5 add the dt-bindings documentation and the board device tree
for the RB5Gen2. This initial submission covers the main board; the vision
mezzanine will be supported in a follow-up series.
Product page:
https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
Changes in v3:
- Reworded MHI commit message to describe actual usage (debugfs
link_transition_count) per Neil's feedback
- Reordered pinctrl-0 before pinctrl-names file-wide per Konrad's
feedback
- Removed output-high from lt9611_rst_pin since the driver handles
reset sequencing
- Reordered tlmm pinctrl entries by GPIO number
- Changed bias-pull-up to bias-disable for regulator enable pins
(upd_1p05_en, upd_3p3_en) since these are active-high enables
- Added comments for gpio-reserved-ranges explaining GPIOs 32-35
are for NFC secure element and 36-39 for fingerprint sensor
- Removed max-sd-hs-hz override since upstream clock driver already
provides the correct 37.5MHz frequency
- Updated msi-map deletion rationale with root cause: Gunyah limits
ITS device mappings to two per root complex on SM8550
- Link to v2: https://lore.kernel.org/r/20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com
Changes in v2:
- Lowercase hex in MHI region definitions for pcie0 and pcie1 nodes +
vertical alignment
- Change pcie0 and pcie1 reg-names for one entry per line
- Ensured pcie port labels + changes to sm8550-hdk.dts and sm8550-qrd.dts
are done in a single commit
- Moved IPA gsi-loader and memory-region to sm8550.dtsi since they are common
properties. Reflect changes in sm8550-hdk.dts and sm8550-qrd.dts
- Removed usbhub_reset since this is not required
- Added swctrl-gpios property to wcn7850-pmu
- Split sw_ctrl_default gpio from bt_default grouping and referenced the
pinctrl separately
- Replaced upd_reset regulator-fixed with pinctrl and vddpe-3v3-supply
on pcie0
- Aligned firmware-name values vertically on the quote mark
- Changed cdsp, adsp and modem remoteprocs to .mbn file type instead of
.mdt
- Added remark in rb5gen2 dts commit explaining the rationale for
deleting msi-map in pcie0 and pcie1 nodes
- Link to v1: https://lore.kernel.org/r/20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com
---
Joe Sandom (5):
arm64: dts: qcom: sm8550: add PCIe MHI register regions
arm64: dts: qcom: sm8550: add PCIe port labels
arm64: dts: qcom: sm8550: move IPA properties to SoC device tree
dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board
arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1573 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 +-
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +-
6 files changed, 1602 insertions(+), 12 deletions(-)
---
base-commit: af241225893ac4933bb8f0615f2dfda8ea2326ce
change-id: 20260404-rb5gen2-dts-180cde0b716c
Best regards,
--
Joe Sandom <jsandom@axon.com>
^ permalink raw reply
* Re: [PATCH 2/4] ASoC: dt-bindings: Add support for the GPIOs driven amplifier
From: Mark Brown @ 2026-04-09 15:26 UTC (permalink / raw)
To: Rob Herring
Cc: Herve Codina, Liam Girdwood, Krzysztof Kozlowski, Conor Dooley,
Saravana Kannan, Jaroslav Kysela, Takashi Iwai, linux-sound,
devicetree, linux-kernel, Christophe Leroy, Thomas Petazzoni
In-Reply-To: <CAL_JsqK4SHQS6MciQpLSrGWo2knqs7-eB3yoAv2J54bSfW-Lxg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1330 bytes --]
On Thu, Apr 09, 2026 at 10:00:55AM -0500, Rob Herring wrote:
> On Wed, Apr 8, 2026 at 12:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
> > Mark suggested to merge this gpio-audio-amp with simple-amplifier.
> Merging driver and merging binding are separate questions.
Yes, my comments were purely about the driver.
> > I didn't want to set a particular limit related to the number of GPIOs
> > used for thje gain value. Of course 2^32 is obviously a lot.
> > What do you think about 16 for maxItems?
> What is the most you are aware of? Take that and double it.
> Seems to me 256 levels would be way more than a human ear could distinguish.
There's plenty of gain controls with way more than 256 bits of
resolution, though I'm not aware of any that are configured via GPIO.
The step size and absolute values you want can vary dramatically
depending on application, possibly in the same system (eg, a DAC that
can be connected to both headphones or speakers) so you often end up
making practical adjustments in a small subset of the available range
but that subset can vary a lot for the same part.
> I guess my point was that really we could deprecate simple-amplifier
> binding because this one can handle it and more. But I'm not
> suggesting we do that yet.
That's my thinking.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH 2/3] nvmem: Add the Raspberry Pi OTP driver
From: Stefan Wahren @ 2026-04-09 15:21 UTC (permalink / raw)
To: Gregor Herburger
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Florian Fainelli,
Ray Jui, Scott Branden, Broadcom internal kernel review list,
Srinivas Kandagatla, devicetree, linux-rpi-kernel,
linux-arm-kernel, linux-kernel
In-Reply-To: <addd5ZpuUdKBV7Bn@gregor-framework>
Am 09.04.26 um 10:05 schrieb Gregor Herburger:
> On Wed, Apr 08, 2026 at 10:03:47PM +0200, Stefan Wahren wrote:
>> Am 08.04.26 um 21:47 schrieb Gregor Herburger:
>>> Hi Stefan,
>>>
>>> thanks for the review.
>>>> Is there any reason, why we cannot register this driver in
>>>> rpi_firmware_probe() like hwmon and clk driver?
>>>>
>>>> I like to avoid the complete dt-binding from patch 1.
>>> The private OTP registers are not available on all Raspberries. Afaik
>>> only on 4 and 5. So I think these registers must be described through
>>> the device tree. Therefore the bindings are needed.
>> This binding doesn't represent some kind of hardware, it's just some
>> firmware interface. A proper DT binding would describe the MMIO address
>> range for OTP access.
> I think it does represent real hardware. Although it is hidden through the
> firmware. Not all hardware must be MMIO addresses.
>
> The only driver that does not have a DT node is the hwmon driver. All
> other drivers (clock, gpio, touchscreeen, reset, pwm) do have a DT
> binding. Looking at the comment in rpi_register_clk_driver this
> seems to be some legacy behaviour for older DTs for the clock driver.
There is a long history of different approaches how to implement the
VideoCore firmware interface for the Raspberry Pi and not all of them
are good from today's perspective.
One big problem with DT binding is that the kernel must be compatible
with all mainline DTS versions. This sounds trivial, but it's not. Since
we cannot assume that kernel & DTB are updated at the same time. So we
need to keep these bad solutions from the past.
>> If you need some distinction between the Raspberry Pi generations there are
>> firmware tags to do this.
> So what is your suggestion? What tags do you mean?
Your driver already use firmware tags to access the OTPs via firmware.
You can ask the Raspberry Pi guys, how to do the distinction in a
efficient/maintainable way.
My suggestion would be to look at
https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface#get-board-model
and
https://github.com/u-boot/u-boot/blob/master/board/raspberrypi/rpi/rpi.c#L95
The compatible "raspberrypi,bcm2712-firmware" approach is more straight
forward, but requires a newer DTB. See above.
Best regards
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: sdm845-oneplus: Update compatible to include model
From: David Heidelberg @ 2026-04-09 15:19 UTC (permalink / raw)
To: Konrad Dybcio, Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jason A. Donenfeld, Matthias Schiffer,
Vincent Huang, Bjorn Andersson, Konrad Dybcio
Cc: linux-input, devicetree, linux-kernel, linux-arm-msm, phone-devel,
Krzysztof Kozlowski
In-Reply-To: <80067706-1857-46a0-a281-7f4ff3937468@oss.qualcomm.com>
On 09/04/2026 14:41, Konrad Dybcio wrote:
> On 4/8/26 7:34 PM, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> We know the driver is reporting s3706b, introduce the compatible so we
>
> via Google search AI summary:
> "Bon Chef S3706B is a black dinner fork (Roman Euro Dinner Fork)" - the
> more you know!
Oh no, that's definitely not compatible hardware! Maybe it's some fork... :P
^ permalink raw reply
* Re: [PATCH] dt-bindings: i2c: nxp,pca9564: convert to DT schema
From: Akhila YS @ 2026-04-09 15:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Rosin, linux-i2c, devicetree, linux-kernel
In-Reply-To: <20260409-rampant-swinging-wolf-51ab4e@quoll>
On 09-04-2026 13:56, Krzysztof Kozlowski wrote:
> On Wed, Apr 08, 2026 at 08:23:31AM +0000, Akhila YS wrote:
>> Convert NXP PCA PCA9564/PCA9665 I2C controller to YAML format.
> DT schema, not YAML format. Look at your subject.
Okay, i will change it.
>
> ...
>
>> + reg:
>> + maxItems: 1
>> +
>> + "#address-cells":
>> + const: 1
>> +
>> + "#size-cells":
>> + const: 0
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + reset-gpios:
>> + maxItems: 1
>> +
>> + clock-frequency:
>> + default: 100000
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
> And if you tested any DTS with this, you would see this cannot work.
> Look at other bindings - you miss ref to i2c-controller and
> unevaluatedProps. But the problem is that you are doing something which
> would never work, so I have doubts that you know what you are doing. One
> thing is to make a mistake, other thing is to post something can never
> work thus putting quite noticeable requirements on review.
You are right, i missed referencing the common i2c controller schema and
did not handle unevaluated properties correctly,which makes binding invalid.
>
> Please first learn how DTS and DT bindings work, before you post new
> patches.
Thank you for the review, i will work on it.
> Best regards,
> Krzysztof
>
--
Best Regards,
Akhila.
^ permalink raw reply
* Re: [PATCH 2/4] ASoC: dt-bindings: Add support for the GPIOs driven amplifier
From: Rob Herring @ 2026-04-09 15:00 UTC (permalink / raw)
To: Herve Codina
Cc: Liam Girdwood, Mark Brown, Krzysztof Kozlowski, Conor Dooley,
Saravana Kannan, Jaroslav Kysela, Takashi Iwai, linux-sound,
devicetree, linux-kernel, Christophe Leroy, Thomas Petazzoni
In-Reply-To: <20260408190932.0ab936b0@bootlin.com>
On Wed, Apr 8, 2026 at 12:09 PM Herve Codina <herve.codina@bootlin.com> wrote:
>
> Hi Rob, Mark,
>
> On Wed, 8 Apr 2026 07:29:01 -0500
> Rob Herring <robh@kernel.org> wrote:
>
> ...
>
> > > +properties:
> > > + compatible:
> > > + const: audio-gpio-amp
> >
> > To be consistent with other GPIO controlled devices: gpio-audio-amp
>
> Ok.
>
> Mark suggested to merge this gpio-audio-amp with simple-amplifier.
Merging driver and merging binding are separate questions.
> This leads to the following question:
>
> Should I keep the 'gpio-audio-amp' compatible string ?
Yes. 'cause this binding isn't simple...
And I don't care for any compatible with 'simple' (or generic) in it.
Not sure why I agreed to that one. But I'm all for generic/common
drivers.
> Should I keep two bindings (this one and the simple-audio-amplifier.yaml) or
> should I merge bindings?
2 bindings. There's no overlap in property names.
> ...
> > > + gain-gpios:
> > > + description: |
> > > + GPIOs to control the amplifier gain
> > > +
> > > + The gain value is computed from GPIOs value from 0 to 2^N-1 with N the
> > > + number of GPIO described. The first GPIO described is the lsb of the gain
> > > + value.
> > > +
> > > + For instance assuming 2 gpios
> > > + gain-gpios = <&gpio1 GPIO_ACTIVE_HIGH> <&gpio2 GPIO_ACTIVE_HIGH>;
> > > + The gain value will be the following:
> > > +
> > > + gpio1 | gpio2 | gain
> > > + ------+-------+-----
> > > + 0 | 0 | 0b00 -> 0
> > > + 1 | 0 | 0b01 -> 1
> > > + 0 | 1 | 0b10 -> 2
> > > + 1 | 1 | 0b11 -> 3
> > > + ------+-------+-----
> > > +
> > > + Note: The gain value, bits set to 1 or 0, indicate the state active (bit
> > > + set) or the state inactive (bit unset) of the related GPIO. The
> > > + physical voltage corresponding to this active/inactive state is
> > > + given by the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags.
> > > +
> > > + minItems: 1
> > > + maxItems: 32
> >
> > 2^32 levels? Seems like a bit much. Also, unless you can change the
> > values of all the GPIOs atomically, aren't you going to get some
> > artifacts while the gain is being changed? Unless you mute I guess.
>
> I didn't want to set a particular limit related to the number of GPIOs
> used for thje gain value. Of course 2^32 is obviously a lot.
>
> What do you think about 16 for maxItems?
What is the most you are aware of? Take that and double it.
Seems to me 256 levels would be way more than a human ear could distinguish.
> Related to Artifacts, yes they can probably be there. Also the mute feature
> is not required. Some hardware use only one GPIO and doesn't implement mute
> feature. In that case no artifacts can be present.
>
> If mute is implemented, it is the application responsibility to handle
> mute / unmute while changing the gain value. I don't think we can do anything
> at driver level to avoid those artifacts if any.
>
> >
> > > +
> > > + gain-points:
> > > + $ref: /schemas/types.yaml#/definitions/int32-matrix
> > > + items:
> > > + items:
> > > + - description: The GPIOs value
> >
> > Can't this just be the index?
>
> Some GPIOs value can be skipped if they don't make any sense in the hardware
> design. With the index, this is not possible.
>
> gpios:
> 0b00 -3dB
> 0b01 0dB
> 0b10 Reserved, should not be used
> 0b11 +3dB
>
> With just the index, the reserved 0b10 value cannot be skipped. I would like
> to handle this kind of cases.
Okay.
> > If not, then gain-range could be expressed using gain-points instead.
>
> Do you have in mind something like the following?
> gain-range = <0 (-300)>, <3 600>;
>
> defining the range from -3dB to +6dB with GPIOs value 0 for -3dB and 3 for +6dB.
Yes, but since you can have reserved values, that won't work.
> > > + - description: The related amplifier gain in 0.01 dB unit
> > > + minItems: 2
> > > + description: |
> > > + List of the GPIOs value / Gain value in dB pair defining the gain
> > > + set on each GPIOs value.
> > > +
> > > + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3.
> > > + Assuming that GPIOs values set the hardware gains according to the
> > > + following table:
> > > +
> > > + GPIOs | Hardware
> > > + value | amplification
> > > + ------+--------------
> > > + 0 | -10.0 dB
> > > + 1 | +3.0 dB
> > > + 2 | 0 dB
> > > + 3 | +6.0 dB
> > > + ------+--------------
> > > +
> > > + The description using gain points can be:
> > > + gain-points = <0 (-1000)>, <1 300>, <2 0>, <3 600>;
> > > +
> > > + gain-range:
> > > + $ref: /schemas/types.yaml#/definitions/int32-array
> > > + items:
> > > + - description: Gain in 0.01 dB unit when all GPIOs are inactive
> > > + - description: Gain in 0.01 dB unit when all GPIOs are active
> > > + description: |
> > > + Gains (in 0.01 dB unit) set by the extremum (minimal and maximum) value
> > > + of GPIOs. The following formula must be satisfied.
> > > +
> > > + gain-range[1] - gain-range[0]
> > > + Gain = ------------------------------- x GPIO_value + gain-range[0]
> > > + 2^N - 1
> > > +
> > > + With N, the number of GPIOs used to control the gain and Gain computed in
> > > + 0.01 dB unit.
> > > +
> > > + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3.
> > > + Assuming that gain value set the hardware according to the following
> > > + table:
> > > +
> > > + GPIOs | Hardware 1 | Hardware 2
> > > + value | amplification | amplification
> > > + ------+---------------+---------------
> > > + 0 | -3.0 dB | +10.0 dB
> > > + 1 | 0 dB | +5.0 dB
> > > + 2 | +3.0 dB | 0 dB
> > > + 3 | +6.0 dB | -5.0 dB
> > > + ------+---------------+---------------
> > > +
> > > + The description for hardware 1 using a gain range can be:
> > > + gain-range = <(-300) 600>;
> > > +
> > > + The description for hardware 2 using a gain range can be:
> > > + gain-range = <1000 (-500)>;
> > > +
> > > + gain-labels:
> > > + $ref: /schemas/types.yaml#/definitions/string-array
> >
> > minItems: 2
> > maxItems: 0x100000000
>
> Ok, I will adjust maxItems according to the max number of GPIO supported.
>
> For my curiosity, is there a way to express maxItems with a computation
> based on some other properties value ?
No, there isn't.
>
> What could be relevant here is
> maxitems: 2^(number of items available in the gpio-gain properties)
>
> >
> > > + description: |
> > > + List of the gain labels attached to the combination of GPIOs controlling
> > > + the gain. The first label is related to the gain value 0, the second label
> > > + is related to the gain value 1 and so on.
> > > +
> > > + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3.
> > > + Assuming that gain value set the hardware according to the following
> > > + table:
> > > +
> > > + GPIOs | Hardware
> > > + value | amplification
> > > + ------+--------------
> > > + 0 | Low
> > > + 1 | Middle
> > > + 2 | High
> > > + 3 | Max
> > > + ------+--------------
> > > +
> > > + The description using gain labels can be:
> > > + gain-labels = "Low", "Middle", "High", "Max";
> >
> > Do we need to allow these to be anything? It's going to get hard to come
> > up with 2^32 names.
>
> Well, "Normal" / "Boost" can make sense on some hardware.
>
> I don't think we need to restrict labels to a list of known label here.
As long as the names are meaningless to software.
>
> Of course 2^32 names is obviously a lot. What could be the limit?
I would guess at 8 or more, it's just going to be gain1, gain2, etc.
or something similar constructed from the gain values.
> ...
>
> > > +
> > > + /* A mutable amplifier without any gain control */
> > > + amplifier4 {
> > > + compatible = "audio-gpio-amp";
> > > + vdd-supply = <®ulator>;
> > > + mute-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
> >
> > This case is just simple-amplifier...
>
> No, simple-amplifier uses 'enable' and not 'mute'.
Yes, I know...
> We can have the amplifier enabled ('enable' GPIO active) as it is
> used and a switch driven by an other GPIO to mute / un-mute the
> amplifier output.
But you have no 'enable' GPIO here. To me, enable just looks like
inverted mute. If there's some electrical difference, I can't tell
what that is from either binding.
I guess my point was that really we could deprecate simple-amplifier
binding because this one can handle it and more. But I'm not
suggesting we do that yet.
Rob
^ permalink raw reply
* Re: [PATCH] of: fdt: skip KHO when booting as crash kernel
From: Mike Rapoport @ 2026-04-09 14:22 UTC (permalink / raw)
To: Evangelos Petrongonas
Cc: Rob Herring, Saravana Kannan, Changyuan Lyu, Alexander Graf,
Pasha Tatashin, Pratyush Yadav, Andrew Morton, devicetree, kexec,
linux-kernel, nh-open-source
In-Reply-To: <20260407150639.69923-1-epetron@amazon.de>
Hi Evangelos,
On Tue, Apr 07, 2026 at 03:06:33PM +0000, Evangelos Petrongonas wrote:
> KHO preserves state across kexec by passing a KHO-specific FDT pointer
> and scratch memory region to the incoming kernel. These point to
> physical addresses in the outgoing kernel's memory that the incoming
> kernel is expected to access and restore from. This falls apart when
> the incoming kernel is a crash kernel as the crash kernel can run in a
> small reserved memory region. The scratch regions can sit outside this
> reservation, so the end result is quite unpleasant.
>
> kho_add_chosen() unconditionally propagates KHO properties into
> the device tree for all kexec image types, including crash images. The
> crash kernel then discovers these properties during
> early_init_dt_check_kho(), records the stale physical addresses via
> kho_populate(), and later faults in kho_memory_init() when it tries
> phys_to_virt() on the KHO FDT address:
>
> Unable to handle kernel paging request at virtual address xxxxxxxx
> ...
> fdt_offset_ptr+...
> fdt_check_node_offset_+...
> fdt_first_property_offset+...
> fdt_get_property_namelen_+...
> fdt_getprop+...
> kho_memory_init+...
> mm_core_init+...
> start_kernel+...
>
> kho_locate_mem_hole() already skips KHO logic for KEXEC_TYPE_CRASH
> images, but the DT property propagation and the consumer side were both
> missing the same guard.
>
> Fix this at both ends. Have kho_add_chosen() skip writing KHO properties
> for crash images so the stale pointers never reach the crash kernel's
> device tree. Also have early_init_dt_check_kho() bail out when
> is_kdump_kernel() is true. This way even if KHO properties end up in
> the DT through some other path, the crash kernel will not act on them.
>
> Fixes: 274cdcb1c004 ("arm64: add KHO support")
> Signed-off-by: Evangelos Petrongonas <epetron@amazon.de>
> ---
>
> I think we should backport the fix on KHO compatible versions (6.16+),
> hence the "Fixes:" tag. Tested on an arm64 system.
>
> drivers/of/fdt.c | 3 +++
> drivers/of/kexec.c | 3 ++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
What about x86? ;-)
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 43a0944ca462..77018ec99fc8 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -926,6 +926,9 @@ static void __init early_init_dt_check_kho(void)
> if (!IS_ENABLED(CONFIG_KEXEC_HANDOVER) || (long)node < 0)
> return;
>
> + if (is_kdump_kernel())
> + return;
> +
This seems redundant if don't add KHO nodes at the first place.
> if (!of_flat_dt_get_addr_size(node, "linux,kho-fdt",
> &fdt_start, &fdt_size))
> return;
> diff --git a/drivers/of/kexec.c b/drivers/of/kexec.c
> index c4cf3552c018..b95f0b386684 100644
> --- a/drivers/of/kexec.c
> +++ b/drivers/of/kexec.c
> @@ -271,7 +271,8 @@ static int kho_add_chosen(const struct kimage *image, void *fdt, int chosen_node
> if (ret && ret != -FDT_ERR_NOTFOUND)
> return ret;
>
> - if (!image->kho.fdt || !image->kho.scratch)
> + if (!image->kho.fdt || !image->kho.scratch ||
> + image->type == KEXEC_TYPE_CRASH)
> return 0;
>
> fdt_mem = image->kho.fdt;
kho_add_chosen() bails out if there's no KHO buffer in kimage, so if
kho_fill_kimage won't add KHO buffer to kexec_crash_image it should be
enough.
> --
> 2.43.0
>
>
>
>
> Amazon Web Services Development Center Germany GmbH
> Tamara-Danz-Str. 13
> 10243 Berlin
> Geschaeftsfuehrung: Christof Hellmis, Andreas Stieger
> Eingetragen am Amtsgericht Charlottenburg unter HRB 257764 B
> Sitz: Berlin
> Ust-ID: DE 365 538 597
>
--
Sincerely yours,
Mike.
^ permalink raw reply
* Re: [PATCH v4 2/2] mfd: arizona: Convert GPIO IRQ handling to descriptors
From: Lee Jones @ 2026-04-09 14:21 UTC (permalink / raw)
To: Linus Walleij
Cc: Bartosz Golaszewski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Charles Keepax, patches, linux-kernel, linux-gpio,
devicetree
In-Reply-To: <20260326-mfd-arizona-irq-v4-2-50c47ed0a18e@kernel.org>
On Thu, 26 Mar 2026, Linus Walleij wrote:
> Convert the arizona polling GPIO handling to use a GPIO descriptor
> instead of passing a global GPIO number as platform data.
>
> This mechanism is not used in the kernel, but let's preserve
> the mechanism to be nice.
>
> Users can define "irq-gpios" in the devicetree or software node
> for the Arizona chip to provide the GPIO line corresponding to
> the IRQ.
>
> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
> drivers/mfd/arizona-irq.c | 46 +++++++++++++++++++--------------------
> include/linux/mfd/arizona/core.h | 2 ++
> include/linux/mfd/arizona/pdata.h | 5 -----
> 3 files changed, 24 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/mfd/arizona-irq.c b/drivers/mfd/arizona-irq.c
> index 544016d420fe..8b752a1257b1 100644
> --- a/drivers/mfd/arizona-irq.c
> +++ b/drivers/mfd/arizona-irq.c
> @@ -136,21 +136,19 @@ static irqreturn_t arizona_irq_thread(int irq, void *data)
> dev_err(arizona->dev,
> "Failed to read main IRQ status: %d\n", ret);
> }
> -#ifdef CONFIG_GPIOLIB_LEGACY
> /*
> * Poll the IRQ pin status to see if we're really done
> * if the interrupt controller can't do it for us.
> */
> - if (!arizona->pdata.irq_gpio) {
> + if (!arizona->irq_gpiod) {
> break;
> } else if (arizona->pdata.irq_flags & IRQF_TRIGGER_RISING &&
> - gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
> + gpiod_get_value_cansleep(arizona->irq_gpiod)) {
> poll = true;
> } else if (arizona->pdata.irq_flags & IRQF_TRIGGER_FALLING &&
> - !gpio_get_value_cansleep(arizona->pdata.irq_gpio)) {
> + !gpiod_get_value_cansleep(arizona->irq_gpiod)) {
> poll = true;
> }
> -#endif
> } while (poll);
>
> pm_runtime_put_autosuspend(arizona->dev);
> @@ -350,27 +348,26 @@ int arizona_irq_init(struct arizona *arizona)
> goto err_map_main_irq;
> }
>
> -#ifdef CONFIG_GPIOLIB_LEGACY
> - /* Used to emulate edge trigger and to work around broken pinmux */
> - if (arizona->pdata.irq_gpio) {
> - if (gpio_to_irq(arizona->pdata.irq_gpio) != arizona->irq) {
> - dev_warn(arizona->dev, "IRQ %d is not GPIO %d (%d)\n",
> - arizona->irq, arizona->pdata.irq_gpio,
> - gpio_to_irq(arizona->pdata.irq_gpio));
> - arizona->irq = gpio_to_irq(arizona->pdata.irq_gpio);
> - }
> -
> - ret = devm_gpio_request_one(arizona->dev,
> - arizona->pdata.irq_gpio,
> - GPIOF_IN, "arizona IRQ");
> - if (ret != 0) {
> - dev_err(arizona->dev,
> - "Failed to request IRQ GPIO %d:: %d\n",
> - arizona->pdata.irq_gpio, ret);
> - arizona->pdata.irq_gpio = 0;
> + /*
> + * Used to emulate edge trigger and to work around broken pinmux
> + * define "irq-gpios" in device tree or software node.
> + */
Nit: Device Tree (not sure about software node).
> + arizona->irq_gpiod = devm_gpiod_get_optional(arizona->dev, "irq",
> + GPIOD_IN);
> + if (IS_ERR(arizona->irq_gpiod)) {
> + ret = dev_err_probe(arizona->dev,
> + PTR_ERR(arizona->irq_gpiod),
> + "error getting IRQ GPIO\n");
Nit: All other prints in this file are capitalised.
> + goto err_irq_gpiod;
> + }
> + if (arizona->irq_gpiod) {
> + if (gpiod_to_irq(arizona->irq_gpiod) != arizona->irq) {
> + dev_warn(arizona->dev, "IRQ %d does not match GPIO's IRQ %d\n",
> + arizona->irq, gpiod_to_irq(arizona->irq_gpiod));
> + arizona->irq = gpiod_to_irq(arizona->irq_gpiod);
Could we cache the result of 'gpiod_to_irq()' into a local variable rather than
calling it multiple times?
Does it make sense to check the value's for errors?
> }
> + gpiod_set_consumer_name(arizona->irq_gpiod, "arizona IRQ");
> }
> -#endif
>
> ret = request_threaded_irq(arizona->irq, NULL, arizona_irq_thread,
> flags, "arizona", arizona);
> @@ -409,6 +406,7 @@ int arizona_irq_init(struct arizona *arizona)
> arizona_free_irq(arizona, ARIZONA_IRQ_BOOT_DONE, arizona);
> err_boot_done:
> free_irq(arizona->irq, arizona);
> +err_irq_gpiod:
> err_main_irq:
Do we really need another goto label that jumps to the same place?
> regmap_del_irq_chip(irq_find_mapping(arizona->virq,
> ARIZONA_MAIN_IRQ_INDEX),
> diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
> index 6d6f96b2b29f..7129651c9af6 100644
> --- a/include/linux/mfd/arizona/core.h
> +++ b/include/linux/mfd/arizona/core.h
> @@ -11,6 +11,7 @@
> #define _WM_ARIZONA_CORE_H
>
> #include <linux/clk.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/interrupt.h>
> #include <linux/notifier.h>
> #include <linux/regmap.h>
> @@ -136,6 +137,7 @@ struct arizona {
> struct irq_domain *virq;
> struct regmap_irq_chip_data *aod_irq_chip;
> struct regmap_irq_chip_data *irq_chip;
> + struct gpio_desc *irq_gpiod;
>
> bool hpdet_clamp;
> unsigned int hp_ena;
> diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
> index f72e6d4b14a7..20118bad869a 100644
> --- a/include/linux/mfd/arizona/pdata.h
> +++ b/include/linux/mfd/arizona/pdata.h
> @@ -188,11 +188,6 @@ struct arizona_pdata {
> /** Haptic actuator type */
> unsigned int hap_act;
>
> -#ifdef CONFIG_GPIOLIB_LEGACY
> - /** GPIO for primary IRQ (used for edge triggered emulation) */
> - int irq_gpio;
> -#endif
> -
> /** General purpose switch control */
> unsigned int gpsw;
> };
>
> --
> 2.53.0
>
--
Lee Jones [李琼斯]
^ permalink raw reply
* Re: [PATCH v2 12/13] hwmon: spd5118: Add I3C support
From: Guenter Roeck @ 2026-04-09 14:19 UTC (permalink / raw)
To: Akhil R, Alexandre Belloni, Frank Li, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rafael J . Wysocki,
Robert Moore, Len Brown, Philipp Zabel, Eric Biggers,
Sakari Ailus, Wolfram Sang, Miquel Raynal, linux-i3c, devicetree,
linux-kernel, linux-acpi, acpica-devel, linux-hwmon
In-Reply-To: <20260409105747.48158-13-akhilrajeev@nvidia.com>
On 4/9/26 03:57, Akhil R wrote:
> Add a regmap config and a probe function to support for I3C based
> communication to SPD5118 devices.
>
> On an I3C bus, SPD5118 are enumerated via SETAASA and always require an
> ACPI or device tree entry. The device matching is hence through the OF
> match tables only and do not need an I3C class match table. The device
> identity is verified in the type registers before proceeding to the
> common probe function.
>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
^ permalink raw reply
* Re: [PATCH v2 11/13] hwmon: spd5118: Remove 16-bit addressing
From: Guenter Roeck @ 2026-04-09 14:11 UTC (permalink / raw)
To: Akhil R, Alexandre Belloni, Frank Li, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Rafael J . Wysocki,
Robert Moore, Len Brown, Philipp Zabel, Eric Biggers,
Sakari Ailus, Wolfram Sang, Miquel Raynal, linux-i3c, devicetree,
linux-kernel, linux-acpi, acpica-devel, linux-hwmon
In-Reply-To: <20260409105747.48158-12-akhilrajeev@nvidia.com>
On 4/9/26 03:57, Akhil R wrote:
> The intent of introducing 16-bit addressing was to support I3C, but it
> turns out to be that I3C do not require to read the Legacy Mode register
> nor any specific encoding for page translation. The testing of 16-bit
> code was limited and there are no known users for this feature. Remove
> the sections which are there to support 16-bit addressing and prepare the
> driver to support I3C appropriately.
>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Suggested-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Guenter Roeck <linux@roeck-us.net>
^ permalink raw reply
* Re: (subset) [PATCH 4/7] dt-bindings: leds: irled: ir-spi-led: Add new duty-cycle value
From: Lee Jones @ 2026-04-09 13:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Pavel Machek, Sean Young,
Michael Turquette, Stephen Boyd, Martin Botka, Biswapriyo Nath
Cc: linux-arm-msm, devicetree, linux-kernel, linux-leds, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <20260325-ginkgo-add-usb-ir-vib-v1-4-446c6e865ad6@gmail.com>
On Wed, 25 Mar 2026 18:07:27 +0000, Biswapriyo Nath wrote:
> 30 duty cycle for IR transmitter is used in Xiaomi Redmi Note 8 (ginkgo).
Applied, thanks!
[4/7] dt-bindings: leds: irled: ir-spi-led: Add new duty-cycle value
commit: 2bbd36622df51f22e6902b0a0743d9354bc8f6d4
--
Lee Jones [李琼斯]
^ permalink raw reply
* Re: [PATCH v1 2/3] arm64: dts: mediatek: mt7988a-bpi-r4pro: update gpio-leds
From: Daniel Golle @ 2026-04-09 13:35 UTC (permalink / raw)
To: Frank Wunderlich
Cc: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Wunderlich, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree, Andrew LaMarche
In-Reply-To: <20260409131754.121737-3-linux@fw-web.de>
On Thu, Apr 09, 2026 at 03:17:50PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> On the official case the red LED is named ERR, the blue LED is named ACT.
> Reflect these labels in function and set them default off.
>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
> index 759f608d1081..7f770a76775a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
> @@ -61,14 +61,16 @@ gpio-leds {
>
> led_red: sys-led-red {
> color = <LED_COLOR_ID_RED>;
> + function = LED_FUNCTION_FAULT;
> gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>;
> - default-state = "on";
> + default-state = "off";
Just drop 'default-state' entirely from both nodes.
> };
>
> led_blue: sys-led-blue {
> color = <LED_COLOR_ID_BLUE>;
> + function = LED_FUNCTION_ACTIVITY;
> gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>;
> - default-state = "on";
> + default-state = "off";
> };
> };
>
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8750-mtp: Set sufficient voltage for panel nt37801
From: Bjorn Andersson @ 2026-04-09 13:35 UTC (permalink / raw)
To: Ayushi Makhija
Cc: konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt,
dmitry.baryshkov, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel, quic_rajeevny, quic_vproddut
In-Reply-To: <75d22f54-eb55-4e55-9582-5b407f41ee81@quicinc.com>
On Thu, Apr 09, 2026 at 11:14:10AM +0530, Ayushi Makhija wrote:
> On 3/26/2026 9:28 PM, Bjorn Andersson wrote:
> > On Thu, Mar 26, 2026 at 03:06:52PM +0530, Ayushi Makhija wrote:
> >> On 3/24/2026 7:34 AM, Bjorn Andersson wrote:
> >>> On Mon, Mar 23, 2026 at 03:52:29PM +0530, Ayushi Makhija wrote:
> >>>> The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
> >>>> VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801.
> >>>>
> >>>
> >>> Please add Fixes: tag.
> >>>
> >>
> >> Hi Bjorn,
> >>
> >> Sure, will add in new patchset.
> >>
> >>>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> >>>
> >>> Please start using your oss.qualcomm.com address.
> >>>
> >>>> ---
> >>>> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
> >>>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> >>>> index 3837f6785320..6ba4e69bf377 100644
> >>>> --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> >>>> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> >>>> @@ -462,7 +462,7 @@ vreg_l11b_1p0: ldo11 {
> >>>>
> >>>> vreg_l12b_1p8: ldo12 {
> >>>> regulator-name = "vreg_l12b_1p8";
> >>>> - regulator-min-microvolt = <1200000>;
> >>>> + regulator-min-microvolt = <1650000>;
> >>>
> >>> Are you sure it's not supposed to be 1.8V, given the name of the rail?
> >>>
> >>> Regards,
> >>> Bjorn
> >>
> >> There was already discussion regarding the minimum voltage for this regulator on sm8550 target
> >> on other upstream patch.
> >>
> >> Link: https://lore.kernel.org/all/aQQdQoCLeKhYtY7W@yuanjiey.ap.qualcomm.com/
> >>
> >> This values is according to the NT37801 panel sec
> >> "The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
> >> VDDI=1.65V~1.95V."
> >>
> >
> > Yes, so the panel requires 1.65V, so regulator-min-microvolt needs to be
> > at least that. But regulator-min-microvolt should account for all the
> > consumers of the rail, are there any others?
> >
> > Which leads me to my question, the people designing the board named the
> > rail VREG_L12B_1P8 in the schematics, why didn't they name it
> > VREG_L12B_1P65?
> >
> > Please check all the consumers and make the regulator-min-microvolt work
> > for all of them - if that's 1.65V, then your change is good.
> >
> > Regards,
> > Bjorn
>
> Hi Bjorn,
>
> There is only one consumer of VREG_L12B_1P8 rail, i.e. NT37801 panel.
> So regulator-min-microvolt as 1.65V should be fine for VREG_L12B_1P8 rail.
>
Had to look it up myself. MTP power grid says it should be 1.8V.
Thank you,
Bjorn
> Thanks,
> Ayushi
>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: rtc: nct3018y: add nuvoton,ctrl-reg-val property
From: Alexandre Belloni @ 2026-04-09 13:30 UTC (permalink / raw)
To: David Wang
Cc: Krzysztof Kozlowski, a.zummo, robh, krzk+dt, conor+dt, andrew,
avi.fishman, tmaimon77, tali.perry1, venture, yuenn, benjaminfair,
ctcchien, mimi05633, openbmc, linux-rtc, devicetree, linux-kernel,
davidwang
In-Reply-To: <CADSQSY1rAnZ69JAjosV_AWBw9OL77dyzHkewW5YGvpCZRwXq5A@mail.gmail.com>
On 09/04/2026 15:44:43+0800, David Wang wrote:
> On Apr 9, 2026, at 15:23, Krzysztof Kozlowski wrote:
> >
> > On 09/04/2026 09:21, David Wang wrote:
> > > Add "nuvoton,ctrl-reg-val" vendor property to allow optional
> > > initialization of the RTC control register (0x0A).
> > >
> > > This allows platform-specific configurations like 24h mode and
> > > write ownership to be defined via Device Tree.
> > >
> > > Signed-off-by: David Wang <tomato1220@gmail.com>
> > > ---
> > > Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml | 5 +++++
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml b/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml
> > > index 4f9b5604acd9..0984dfb77170 100644
> > > --- a/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml
> > > +++ b/Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml
> > > @@ -24,6 +24,10 @@ properties:
> > >
> > > reset-source: true
> > >
> > > + nuvoton,ctrl-reg-val:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description: Initial value for the control register (0x0A).
> >
> > 24h mode is not a property of a board. I don't know what "write
> > ownership" is.
> >
> > Best regards,
> > Krzysztof
>
> Hi Krzysztof,
>
> Thanks for your feedback. Let me clarify these two points based on the
> NCT3018Y datasheet:
> 1. Regarding "write ownership": The NCT3018Y features two I2C
> interfaces (Primary and Secondary). The TWO (Time Write Ownership) bit
> in the control register determines which interface has the authority
> to write to the RTC. We need to ensure the interface connected to our
> SoC is granted this ownership during probe—especially for factory-new
> chips—to ensure the RTC is writable.
You need a write-access property. For NXP, we settled with
nxp,write-access.
> 2. Regarding "24h mode": This bit determines the internal data format
> in which time is stored within the RTC hardware. Setting this ensures
> the hardware's internal storage layout matches the driver's
> expectation from the start.
The driver needs to always write 24h mode but can support reading both.
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v1 0/3] some BPI-R4Pro dts updates
From: Frank Wunderlich @ 2026-04-09 13:17 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Frank Wunderlich, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, Daniel Golle, Andrew LaMarche
From: Frank Wunderlich <frank-w@public-files.de>
There are some parts of BPI-R4Pro DTS that need to be changed. Currently
there should be not much users of the mainline-dts and we noticed some
things while openwrt integration.
Frank Wunderlich (3):
arm64: dts: mediatek: mt7988a-bpi-r4pro: drop duplicate fan properties
arm64: dts: mediatek: mt7988a-bpi-r4pro: update gpio-leds
arm64: dts: mediatek: mt7988a-bpi-r4pro: rework pcie gpio-hog handling
arch/arm64/boot/dts/mediatek/Makefile | 8 ++++++++
.../mt7988a-bananapi-bpi-r4-pro-cn13.dtso | 20 +++++++++++++++++++
.../mt7988a-bananapi-bpi-r4-pro-cn14.dtso | 20 +++++++++++++++++++
.../mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 15 ++++----------
4 files changed, 52 insertions(+), 11 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso
create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso
--
2.43.0
^ permalink raw reply
* [PATCH v1 3/3] arm64: dts: mediatek: mt7988a-bpi-r4pro: rework pcie gpio-hog handling
From: Frank Wunderlich @ 2026-04-09 13:17 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Frank Wunderlich, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, Daniel Golle, Andrew LaMarche
In-Reply-To: <20260409131754.121737-1-linux@fw-web.de>
From: Frank Wunderlich <frank-w@public-files.de>
The active-high property in base-dt cannot be overwritten and must be
set in separate overlay.
Fixes: f397471a6a8c ("arm64: dts: mediatek: mt7988: Add devicetree for BananaPi R4 Pro")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/Makefile | 8 ++++++++
.../mt7988a-bananapi-bpi-r4-pro-cn13.dtso | 20 +++++++++++++++++++
.../mt7988a-bananapi-bpi-r4-pro-cn14.dtso | 20 +++++++++++++++++++
.../mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 2 --
4 files changed, 48 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso
create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 387faa9c2a09..a86fb313b1a9 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -47,6 +47,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-4e.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn13.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn14.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn15.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo
@@ -70,18 +72,24 @@ mt7988a-bananapi-bpi-r4-2g5-sd-dtbs := \
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-sd.dtb
mt7988a-bananapi-bpi-r4-pro-8x-emmc-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x.dtb \
+ mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \
+ mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \
mt7988a-bananapi-bpi-r4-pro-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-emmc.dtb
mt7988a-bananapi-bpi-r4-pro-8x-sd-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x.dtb \
+ mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \
+ mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \
mt7988a-bananapi-bpi-r4-pro-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb
mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \
+ mt7988a-bananapi-bpi-r4-pro-cn14.dtbo \
mt7988a-bananapi-bpi-r4-pro-cn15.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15.dtb
mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \
mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \
+ mt7988a-bananapi-bpi-r4-pro-cn13.dtbo \
mt7988a-bananapi-bpi-r4-pro-cn18.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso
new file mode 100644
index 000000000000..973b76ba0cbf
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn13.dtso
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/* This enables key-m slot CN13 on pcie2(11280000 1L0) on BPI-R4-Pro */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
+};
+
+&{/soc/pinctrl@1001f000/pcie-2-hog} {
+ output-high;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso
new file mode 100644
index 000000000000..90b2a64459c3
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-cn14.dtso
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/* This enables key-m slot CN14 on pcie3(11290000 1L1) on BPI-R4-Pro */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "bananapi,bpi-r4-pro", "mediatek,mt7988a";
+};
+
+&{/soc/pinctrl@1001f000/pcie-3-hog} {
+ output-high;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
index 7f770a76775a..5c5d4e26aa56 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
@@ -432,14 +432,12 @@ mux {
pcie-2-hog {
gpio-hog;
gpios = <79 GPIO_ACTIVE_HIGH>;
- output-high;
};
/* 1L1 0=key-b (CN18), 1=key-m (CN14) */
pcie-3-hog {
gpio-hog;
gpios = <63 GPIO_ACTIVE_HIGH>;
- output-high;
};
pwm0_pins: pwm0-pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v1 2/3] arm64: dts: mediatek: mt7988a-bpi-r4pro: update gpio-leds
From: Frank Wunderlich @ 2026-04-09 13:17 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Frank Wunderlich, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, Daniel Golle, Andrew LaMarche
In-Reply-To: <20260409131754.121737-1-linux@fw-web.de>
From: Frank Wunderlich <frank-w@public-files.de>
On the official case the red LED is named ERR, the blue LED is named ACT.
Reflect these labels in function and set them default off.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
.../boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
index 759f608d1081..7f770a76775a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
@@ -61,14 +61,16 @@ gpio-leds {
led_red: sys-led-red {
color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
gpios = <&pca9555 15 GPIO_ACTIVE_HIGH>;
- default-state = "on";
+ default-state = "off";
};
led_blue: sys-led-blue {
color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_ACTIVITY;
gpios = <&pca9555 14 GPIO_ACTIVE_HIGH>;
- default-state = "on";
+ default-state = "off";
};
};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v6 10/21] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC
From: Laurent Pinchart @ 2026-04-09 13:24 UTC (permalink / raw)
To: Tommaso Merciai
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <61f294e8-f9ae-4868-8dba-60250279ef21@bp.renesas.com>
On Thu, Apr 09, 2026 at 01:15:18PM +0200, Tommaso Merciai wrote:
> On 4/8/26 17:00, Laurent Pinchart wrote:
> > On Wed, Apr 08, 2026 at 04:44:48PM +0200, Tommaso Merciai wrote:
> >> On 4/8/26 16:16, Laurent Pinchart wrote:
> >>> On Wed, Apr 08, 2026 at 04:02:14PM +0200, Tommaso Merciai wrote:
> >>>> On 4/8/26 14:24, Laurent Pinchart wrote:
> >>>>> On Wed, Apr 08, 2026 at 12:36:55PM +0200, Tommaso Merciai wrote:
> >>>>>> The RZ/G3E SoC has 2 LCD controllers (LCDC), each containing a Frame
> >>>>>> Compression Processor (FCPVD), a Video Signal Processor (VSPD), and a
> >>>>>> Display Unit (DU).
> >>>>>>
> >>>>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >>>>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >>>>>>
> >>>>>> Add a new SoC-specific compatible string 'renesas,r9a09g047-du'.
> >>>>>>
> >>>>>> Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" to
> >>>>>> allow up to four output ports, and explicitly disable port@2 and port@3
> >>>>>> for existing SoCs that do not expose them.
> >>>>>>
> >>>>>> Describe the four output ports of the RZ/G3E DU:
> >>>>>>
> >>>>>> - port@0: DSI (available on both LCDC instances)
> >>>>>> - port@1: DPAD / parallel RGB (LCDC1 only)
> >>>>>> - port@2: LVDS channel 0 (LCDC0 only)
> >>>>>> - port@3: LVDS channel 1 (available on both LCDC instances)
> >>>>>>
> >>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >>>>>> ---
> >>>>>> v5->v6:
> >>>>>> - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
> >>>>>> explicitly disable port@2 and port@3 for existing SoCs that do not expose
> >>>>>> them.
> >>>>>> - Reworked ports numbering + improved/fixed ports descriptions in the
> >>>>>> bindings documentation.
> >>>>>> - Improved commit body.
> >>>>>>
> >>>>>> v4->v5:
> >>>>>> - Dropped renesas,id property and updated bindings
> >>>>>> accordingly.
> >>>>>>
> >>>>>> v2->v3:
> >>>>>> - No changes.
> >>>>>>
> >>>>>> v2->v3:
> >>>>>> - No changes.
> >>>>>>
> >>>>>> v1->v2:
> >>>>>> - Use single compatible string instead of multiple compatible strings
> >>>>>> for the two DU instances, leveraging a 'renesas,id' property to
> >>>>>> differentiate between DU0 and DU1.
> >>>>>> - Updated commit message accordingly.
> >>>>>>
> >>>>>> .../bindings/display/renesas,rzg2l-du.yaml | 30 ++++++++++++++++++-
> >>>>>> 1 file changed, 29 insertions(+), 1 deletion(-)
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>>>> index 5add3b832eab..32da0b5ec88c 100644
> >>>>>> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>>>> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> >>>>>> @@ -20,6 +20,7 @@ properties:
> >>>>>> - enum:
> >>>>>> - renesas,r9a07g043u-du # RZ/G2UL
> >>>>>> - renesas,r9a07g044-du # RZ/G2{L,LC}
> >>>>>> + - renesas,r9a09g047-du # RZ/G3E
> >>>>>> - renesas,r9a09g057-du # RZ/V2H(P)
> >>>>>> - items:
> >>>>>> - enum:
> >>>>>> @@ -61,7 +62,7 @@ properties:
> >>>>>> model-dependent. Each port shall have a single endpoint.
> >>>>>>
> >>>>>> patternProperties:
> >>>>>> - "^port@[0-1]$":
> >>>>>> + "^port@[0-3]$":
> >>>>>> $ref: /schemas/graph.yaml#/properties/port
> >>>>>> unevaluatedProperties: false
> >>>>>>
> >>>>>> @@ -103,6 +104,8 @@ allOf:
> >>>>>> port@0:
> >>>>>> description: DPI
> >>>>>> port@1: false
> >>>>>> + port@2: false
> >>>>>> + port@3: false
> >>>>>>
> >>>>>> required:
> >>>>>> - port@0
> >>>>>> @@ -119,6 +122,8 @@ allOf:
> >>>>>> description: DSI
> >>>>>> port@1:
> >>>>>> description: DPI
> >>>>>> + port@2: false
> >>>>>> + port@3: false
> >>>>>>
> >>>>>> required:
> >>>>>> - port@0
> >>>>>> @@ -135,9 +140,32 @@ allOf:
> >>>>>> port@0:
> >>>>>> description: DSI
> >>>>>> port@1: false
> >>>>>> + port@2: false
> >>>>>> + port@3: false
> >>>>>>
> >>>>>> required:
> >>>>>> - port@0
> >>>>>> + - if:
> >>>>>> + properties:
> >>>>>> + compatible:
> >>>>>> + contains:
> >>>>>> + const: renesas,r9a09g047-du
> >>>>>> + then:
> >>>>>> + properties:
> >>>>>> + ports:
> >>>>>> + properties:
> >>>>>> + port@0:
> >>>>>> + description: DSI
> >>>>>> + port@1:
> >>>>>> + description: DPAD
> >>>>>> + port@2:
> >>>>>> + description: LVDS, Channel 0
> >>>>>> + port@3:
> >>>>>> + description: LVDS, Channel 1
> >>>>>> +
> >>>>>> + required:
> >>>>>> + - port@0
> >>>>>> + - port@3
> >>>>>
> >>>>> Why are ports 1 and 2 not required ?
> >>>>
> >>>> About this we had a similar discussion on v5[0]
> >>>> We are using the same compatible and:
> >>>>
> >>>> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >>>> |
> >>>> --> then has:
> >>>> port@0
> >>>> port@2
> >>>> port@3
> >>>>
> >>>>
> >>>> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> >>>> |
> >>>> --> then has:
> >>>> port@0
> >>>> port@1
> >>>> port@3
> >>>
> >>> Ah yes, I forget there are two LCDC instances with different output
> >>> configurations.
> >>>
> >>> Something still looks a bit weird to me though. For LCDC1, which
> >>> supports a single LVDS channel, you use the port described as the second
> >>> LVDS channel. Is there a reason not to use port@2 ?
> >>
> >> 9.11 Low Voltage Differential Signaling (LVDS)
> >> 9.11.1.2 Block Diagram
> >> Figure 9.11-1 shows a block diagram of LVDS.
> >>
> >> LCDC1 is connected to LVDS, Channel 1
> >> For this reason I'm using port@3.
> >
> > Re-reading that, I think I've misinterpreted the hardware architecture.
> > Doesn't the DU have a single output, that is connected the multiple
> > encoders (LVDS and DSI for LCDC0 and LVDS, DSI and DPI for LCDC1) ? It
> > seems modelling it with a single port and multiple endpoints would
> > better match the device.
> >
> > For LVDS in particular, I see a single LVDS encoder with two channels,
> > so there should not be two LVDS output ports in the DU. The two ports
> > should be on the output of the LVDS device.
>
> You are suggesting the following dt architecture:
>
> du0: display@16460000 {
> compatible = "renesas,r9a09g047-du";
> reg = <0 0x16460000 0 0x10000>;
> interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 0xed>,
> <&cpg CPG_MOD 0xee>,
> <&cpg CPG_MOD 0xef>;
> clock-names = "aclk", "pclk", "vclk";
> power-domains = <&cpg>;
> resets = <&cpg 0xdc>;
> renesas,vsps = <&vspd0 0>;
> status = "disabled";
>
> port {
> du0_out_dsi: endpoint@0 {
> reg = <0>;
> };
>
> du0_out_lvds0: endpoint@2 {
> reg = <2>;
> };
>
> du0_out_lvds1: endpoint@3 {
> reg = <3>;
> };
> }
> };
>
> du1: display@16490000 {
> compatible = "renesas,r9a09g047-du";
> reg = <0 0x16490000 0 0x10000>;
> interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 0x1a8>,
> <&cpg CPG_MOD 0x1a9>,
> <&cpg CPG_MOD 0x1aa>;
> clock-names = "aclk", "pclk", "vclk";
> power-domains = <&cpg>;
> resets = <&cpg 0x11e>;
> renesas,vsps = <&vspd1 0>;
> status = "disabled";
>
> port {
> du1_out_dsi: endpoint@0 {
> reg = <0>;
> };
>
> du1_out_rgb: endpoint@1 {
> reg = <1>;
> };
>
> du1_out_lvds1: endpoint@3 {
> reg = <3>;
> };
> }
> };
>
>
> Please correct me if I'm wrong.
That's right. It would match the hardware, or at least my understanding
of the hardware based on the documentation. As far as I can tell, each
DU has a single 24-bit output port connected to multiple encoders.
> >>>> Then port@1 is required for DU1 but not for DU0.
> >>>> Same port@2 is required for DU0 but not for DU1.
> >>>>
> >>>> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/ca022fdbba5236c36e0cb3095db4c31e8e0cb1b8.1770996493.git.tommaso.merciai.xr@bp.renesas.com/
> >>>>
> >>>>>>
> >>>>>> examples:
> >>>>>> # RZ/G2L DU
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v1 1/3] arm64: dts: mediatek: mt7988a-bpi-r4pro: drop duplicate fan properties
From: Frank Wunderlich @ 2026-04-09 13:17 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Frank Wunderlich, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, Daniel Golle, Andrew LaMarche
In-Reply-To: <20260409131754.121737-1-linux@fw-web.de>
From: Frank Wunderlich <frank-w@public-files.de>
These properties are already set in the original node and do not need
to be defined again.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
.../boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
index 1175ee156cb3..759f608d1081 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro.dtsi
@@ -185,13 +185,6 @@ ð {
status = "okay";
};
-&fan {
- pinctrl-0 = <&pwm0_pins>;
- pinctrl-names = "default";
- pwms = <&pwm 0 50000>;
- status = "okay";
-};
-
&gmac0 {
status = "okay";
};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v6 13/21] drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature
From: Laurent Pinchart @ 2026-04-09 13:22 UTC (permalink / raw)
To: Tommaso Merciai
Cc: tomm.merciai, geert, linux-renesas-soc, biju.das.jz,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Magnus Damm,
Tomi Valkeinen, dri-devel, devicetree, linux-kernel, linux-clk
In-Reply-To: <81165cf9-b1cc-4e75-b586-0e1ef7675b9d@bp.renesas.com>
On Thu, Apr 09, 2026 at 01:14:51PM +0200, Tommaso Merciai wrote:
> On 4/8/26 17:08, Laurent Pinchart wrote:
> > On Wed, Apr 08, 2026 at 04:58:01PM +0200, Tommaso Merciai wrote:
> >> On 4/8/26 16:17, Laurent Pinchart wrote:
> >>> On Wed, Apr 08, 2026 at 04:12:22PM +0200, Tommaso Merciai wrote:
> >>>> On 4/8/26 14:31, Laurent Pinchart wrote:
> >>>>> On Wed, Apr 08, 2026 at 12:36:58PM +0200, Tommaso Merciai wrote:
> >>>>>> The MIPI DSI ip found in the RZ/G3E SoC select the video input clock
> >>>>>> based on the DU instance actually connected using the GPO0R register.
> >>>>>>
> >>>>>> Add this feature to the driver using `RZ_MIPI_DSI_FEATURE_GPO0R`, update
> >>>>>> the code accordingly to manage the vclk selection with the introduction
> >>>>>> of `rzg2l_mipi_dsi_get_input_port()`.
> >>>>>>
> >>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >>>>>> ---
> >>>>>> v5->v6:
> >>>>>> - Moved rzg2l_mipi_dsi_link_write() into rzv2h_mipi_dsi_dphy_init()
> >>>>>> + comments from HW Manual.
> >>>>>>
> >>>>>> v4->v5:
> >>>>>> - No changes.
> >>>>>>
> >>>>>> v3->v4:
> >>>>>> - No changes.
> >>>>>>
> >>>>>> v2->v3:
> >>>>>> - No changes.
> >>>>>>
> >>>>>> v1->v2:
> >>>>>> - No changes.
> >>>>>>
> >>>>>> .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 71 +++++++++++++++++--
> >>>>>> .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 3 +
> >>>>>> 2 files changed, 68 insertions(+), 6 deletions(-)
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> >>>>>> index be6dbf19a24e..947c8e15fc4b 100644
> >>>>>> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> >>>>>> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> >>>>>> @@ -37,7 +37,9 @@ MODULE_IMPORT_NS("RZV2H_CPG");
> >>>>>>
> >>>>>> #define RZG2L_DCS_BUF_SIZE 128 /* Maximum DCS buffer size in external memory. */
> >>>>>>
> >>>>>> +#define RZ_MIPI_DSI_MAX_INPUT 2
> >>>>>> #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0)
> >>>>>> +#define RZ_MIPI_DSI_FEATURE_GPO0R BIT(1)
> >>>>>>
> >>>>>> struct rzg2l_mipi_dsi;
> >>>>>>
> >>>>>> @@ -81,13 +83,14 @@ struct rzg2l_mipi_dsi {
> >>>>>> struct drm_bridge bridge;
> >>>>>> struct drm_bridge *next_bridge;
> >>>>>>
> >>>>>> - struct clk *vclk;
> >>>>>> + struct clk *vclk[RZ_MIPI_DSI_MAX_INPUT];
> >>>>>> struct clk *lpclk;
> >>>>>>
> >>>>>> enum mipi_dsi_pixel_format format;
> >>>>>> unsigned int num_data_lanes;
> >>>>>> unsigned int lanes;
> >>>>>> unsigned long mode_flags;
> >>>>>> + u8 vclk_idx;
> >>>>>>
> >>>>>> struct rzv2h_dsi_mode_calc mode_calc;
> >>>>>>
> >>>>>> @@ -543,8 +546,8 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_f
> >>>>>> unsigned long vclk_rate;
> >>>>>> unsigned int bpp;
> >>>>>>
> >>>>>> - clk_set_rate(dsi->vclk, mode_freq * KILO);
> >>>>>> - vclk_rate = clk_get_rate(dsi->vclk);
> >>>>>> + clk_set_rate(dsi->vclk[dsi->vclk_idx], mode_freq * KILO);
> >>>>>> + vclk_rate = clk_get_rate(dsi->vclk[dsi->vclk_idx]);
> >>>>>> if (vclk_rate != mode_freq * KILO)
> >>>>>> dev_dbg(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
> >>>>>> mode_freq * KILO, vclk_rate);
> >>>>>> @@ -687,6 +690,19 @@ static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> >>>>>> rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R,
> >>>>>> FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k));
> >>>>>>
> >>>>>> + /*
> >>>>>> + * From RZ/G3E HW manual (Rev.1.15) section 9.5.3 Operation,
> >>>>>> + * 9.5.3.1 Power on Reset and Initial Settings for All Operations.
> >>>>>> + * Figure 9.5-4 Power On/Off Sequence show that after writing to
> >>>>>> + * GPO0R.VICH register we need to wait for more than 1 x tp before
> >>>>>> + * writing to PLLENR.PLLEN.
> >>>>>> + *
> >>>>>> + * Note: GPO0R is a link register, not a PHY register. This setting
> >>>>>> + * is specific to RZ/G3E.
> >>>>>> + */
> >>>>>> + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_GPO0R)
> >>>>>> + rzg2l_mipi_dsi_link_write(dsi, GPO0R, dsi->vclk_idx);
> >>>>>> +
> >>>>>> /*
> >>>>>> * From RZ/V2H HW manual (Rev.1.20) section 9.5.3 Operation,
> >>>>>> * (C) After write to D-PHY registers we need to wait for more than 1 x tp
> >>>>>> @@ -1005,6 +1021,37 @@ static int rzg2l_mipi_dsi_stop_video(struct rzg2l_mipi_dsi *dsi)
> >>>>>> return ret;
> >>>>>> }
> >>>>>>
> >>>>>> +static int rzg2l_mipi_dsi_get_input_port(struct rzg2l_mipi_dsi *dsi)
> >>>>>> +{
> >>>>>> + struct device_node *np = dsi->dev->of_node;
> >>>>>> + struct device_node *remote_ep, *ep_node;
> >>>>>> + struct of_endpoint ep;
> >>>>>> + bool ep_enabled;
> >>>>>> + int in_port;
> >>>>>> +
> >>>>>> + /* DSI can have only one port enabled */
> >>>>>
> >>>>> Why is that ? The hardware supports dynamic input selection, why can't
> >>>>> it be supported at runtime ?
> >>>>
> >>>> For runtime/dynamic you mean using DT overlay??
> >>>> like, remove:
> >>>>
> >>>> Removing - DU0 --> DSI (input 0 | port@0 ) overlay and
> >>>> install - DU1 --> DSI (input 1 | port@1 ) overlay and
> >>>> viceversa?
> >>>
> >>> No, I mean configurable by userspace, with two CRTCs sharing one DSI
> >>> encoder.
> >>
> >> Sorry, question:
> >> - Is it possible to create CRTC from user space?
> >
> > No, the CRTCs are created by the driver, but you can have one DRM device
> > that covers two LCDCs, with one CRTC each, both connected to the same
> > DSI encoder (and apparently this applies to the LVDS encoder too).
> > Userspace then selects which CRTC drives which connector.
>
> Which user space tool would you suggest I use for testing this?
I usually use kmstest, part of https://github.com/tomba/kmsxx/. The
modetest application from libdrm should work fine too. This is standard
KMS API.
> And also, which user space tool is the user supposed to use at
> runtime on his final/production system to perform that selection?
Any compositor should support this. Multiple CRTCs with configurable
routing towards connectors is very standard.
> >> From hardware point only one DSI input is selectable out of 2 LCDC's at
> >> a time.
> >>
> >> References:
> >> - 9.5.2.2.3 9.5 MIPI DSI Interface (DSI)
> >> General Purpose Output 0 Register (DSI_LINK_GPO0R)
> >>
> >> - 9.5 MIPI DSI Interface (DSI)
> >> 9.5.1.2 Block Diagram
> >> Figure 9.5-1 Video Input Interface
> >>
> >>>>>> + for_each_endpoint_of_node(np, ep_node) {
> >>>>>> + of_graph_parse_endpoint(ep_node, &ep);
> >>>>>> + if (ep.port >= RZ_MIPI_DSI_MAX_INPUT)
> >>>>>> + break;
> >>>>>> +
> >>>>>> + remote_ep = of_graph_get_remote_endpoint(ep_node);
> >>>>>> + ep_enabled = of_device_is_available(remote_ep);
> >>>>>> + of_node_put(remote_ep);
> >>>>>> +
> >>>>>> + if (ep_enabled) {
> >>>>>> + in_port = ep.port;
> >>>>>> + break;
> >>>>>> + }
> >>>>>> + }
> >>>>>> +
> >>>>>> + if (!ep_enabled)
> >>>>>> + return -EINVAL;
> >>>>>> +
> >>>>>> + dev_dbg(dsi->dev, "input port@%d\n", in_port);
> >>>>>> + return in_port;
> >>>>>> +}
> >>>>>> +
> >>>>>> /* -----------------------------------------------------------------------------
> >>>>>> * Bridge
> >>>>>> */
> >>>>>> @@ -1425,9 +1472,21 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> >>>>>> if (IS_ERR(dsi->mmio))
> >>>>>> return PTR_ERR(dsi->mmio);
> >>>>>>
> >>>>>> - dsi->vclk = devm_clk_get(dsi->dev, "vclk");
> >>>>>> - if (IS_ERR(dsi->vclk))
> >>>>>> - return PTR_ERR(dsi->vclk);
> >>>>>> + dsi->vclk[0] = devm_clk_get(dsi->dev, "vclk");
> >>>>>> + if (IS_ERR(dsi->vclk[0]))
> >>>>>> + return PTR_ERR(dsi->vclk[0]);
> >>>>>> +
> >>>>>> + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_GPO0R) {
> >>>>>> + dsi->vclk[1] = devm_clk_get(dsi->dev, "vclk2");
> >>>>>> + if (IS_ERR(dsi->vclk[1]))
> >>>>>> + return PTR_ERR(dsi->vclk[1]);
> >>>>>> +
> >>>>>> + ret = rzg2l_mipi_dsi_get_input_port(dsi);
> >>>>>> + if (ret < 0)
> >>>>>> + return dev_err_probe(dsi->dev, -EINVAL,
> >>>>>> + "No available input port\n");
> >>>>>> + dsi->vclk_idx = ret;
> >>>>>> + }
> >>>>>>
> >>>>>> dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
> >>>>>> if (IS_ERR(dsi->lpclk))
> >>>>>> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> >>>>>> index 2bef20566648..cee2e0bc5dc5 100644
> >>>>>> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> >>>>>> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h
> >>>>>> @@ -83,6 +83,9 @@
> >>>>>> #define LINKSR_SQCHRUN1 BIT(4)
> >>>>>> #define LINKSR_SQCHRUN0 BIT(0)
> >>>>>>
> >>>>>> +/* RZ/G3E General Purpose Output 0 Register */
> >>>>>> +#define GPO0R 0xc0
> >>>>>> +
> >>>>>> /* Tx Set Register */
> >>>>>> #define TXSETR 0x100
> >>>>>> #define TXSETR_NUMLANECAP (0x3 << 16)
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH RFC 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper
From: Bjorn Andersson @ 2026-04-09 13:19 UTC (permalink / raw)
To: Qiang Yu
Cc: Taniya Das, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, johan,
linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <ac306hTHe3qVORk2@hu-qianyu-lv.qualcomm.com>
On Wed, Apr 01, 2026 at 09:47:38PM -0700, Qiang Yu wrote:
> On Wed, Apr 01, 2026 at 10:05:12PM +0530, Taniya Das wrote:
> > On 4/1/2026 12:05 PM, Qiang Yu wrote:
> > > diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
[..]
> > > +static const char * const tcsr_pcie_4_regulators[] = {
> > > + "vdda-refgen-0p9",
> > > + "vdda-refgen-1p2",
> > > + "vdda-qreftx1-0p9",
> > > + "vdda-qrefrpt0-0p9",
> > > + "vdda-qrefrpt1-0p9",
> > > + "vdda-qrefrpt2-0p9",
> > > + "vdda-qrefrx2-0p9",
> > > +};
> > > +
> >
> > TCSR clock refs are just not for PCIe alone, they would have supplies
> > for all the ref clocks. These supplies can also be shared across other
> > clock refs. I think it is not the correct way to handle the supplies, as
> > TCSR does not have the complete supplies map.
> >
> We have complete supplies map. You can get it on ipcatlog. Here is example
> for other instances eg USB and EDP:
> - Glymur (eDP): CXO PAD -> TX0 -> RPT0 -> RX0 -> eDP
> - Glymur (USB4_2): CXO PAD -> TX0 -> RPT0 -> RPT1 -> RX1 -> USB4_2
> - Glymur (USB3): CXO PAD -> TX0 -> RPT3 -> RPT4 -> RX4 -> USB3_SS3
>
> I only add supplies for PCIe in this series because USB and EDP vote these
> LDO in their PHY driver. They can remove them in PHY dts node and add same
> regulator list here.
>
The regulators are reference counted. Can't we add the USB and eDP
handling here as well now, and then after they are voted here we remove
them from the PHY?
Regards,
Bjorn
> - Qiang Yu
> >
> > > +static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] = {
> > > + [TCSR_EDP_CLKREF_EN] = {
> > > + .name = "tcsr_edp_clkref_en",
> > > + .offset = 0x60,
> > > },
> > > -};
> > >
> >
> >
> > --
> > Thanks,
> > Taniya Das
> >
^ permalink raw reply
* Re: [PATCH v3] ASoC: dt-bindings: hisilicon: Convert hi6210 I2S to dt-schema
From: Mark Brown @ 2026-04-08 18:06 UTC (permalink / raw)
To: lgirdwood, robh, krzk+dt, conor+dt, Chaitanya Sabnis
Cc: john.stultz, linux-sound, devicetree, linux-kernel
In-Reply-To: <20260327092106.4233-1-chaitanya.msabnis@gmail.com>
On Fri, 27 Mar 2026 14:51:06 +0530, Chaitanya Sabnis wrote:
> ASoC: dt-bindings: hisilicon: Convert hi6210 I2S to dt-schema
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.1
Thanks!
[1/1] ASoC: dt-bindings: hisilicon: Convert hi6210 I2S to dt-schema
https://git.kernel.org/broonie/sound/c/f4ee8a882a56
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* [PATCH 5/6] pinctrl: tegra: Add Tegra264 pinmux driver
From: pshete @ 2026-04-09 13:13 UTC (permalink / raw)
To: linux-gpio, devicetree, linux-tegra, linux-kernel, arnd,
bjorn.andersson, conor+dt, dmitry.baryshkov, ebiggers, geert,
jonathanh, krzk+dt, kuninori.morimoto.gx, linusw, luca.weiss,
michal.simek, prabhakar.mahadev-lad.rj, robh, rosenp, sven,
thierry.reding, webgeek1234
Cc: pshete
In-Reply-To: <20260409131340.168556-1-pshete@nvidia.com>
From: Prathamesh Shete <pshete@nvidia.com>
Add support for the three pin controllers
(MAIN, UPHY and AON) found on Tegra264.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
drivers/pinctrl/tegra/Kconfig | 9 +
drivers/pinctrl/tegra/Makefile | 1 +
drivers/pinctrl/tegra/pinctrl-tegra264.c | 2216 ++++++++++++++++++++++
3 files changed, 2226 insertions(+)
create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra264.c
diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig
index ccb8c337b4ee..d26202895997 100644
--- a/drivers/pinctrl/tegra/Kconfig
+++ b/drivers/pinctrl/tegra/Kconfig
@@ -45,6 +45,15 @@ config PINCTRL_TEGRA238
and configuration for the MAIN and AON pin controllers found
on Tegra238.
+config PINCTRL_TEGRA264
+ tristate "NVIDIA Tegra264 pinctrl driver"
+ select PINCTRL_TEGRA
+ help
+ Say Y or M here to enable support for the pinctrl driver for
+ NVIDIA Tegra264 SoC. This driver controls the pin multiplexing
+ and configuration for the MAIN, AON and UPHY pin controllers found
+ on Tegra264.
+
config PINCTRL_TEGRA_XUSB
def_bool y if ARCH_TEGRA
select GENERIC_PHY
diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile
index ce700bbcbf6e..71ade768bf9c 100644
--- a/drivers/pinctrl/tegra/Makefile
+++ b/drivers/pinctrl/tegra/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_TEGRA186) += pinctrl-tegra186.o
obj-$(CONFIG_PINCTRL_TEGRA194) += pinctrl-tegra194.o
obj-$(CONFIG_PINCTRL_TEGRA234) += pinctrl-tegra234.o
obj-$(CONFIG_PINCTRL_TEGRA238) += pinctrl-tegra238.o
+obj-$(CONFIG_PINCTRL_TEGRA264) += pinctrl-tegra264.o
obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra264.c b/drivers/pinctrl/tegra/pinctrl-tegra264.c
new file mode 100644
index 000000000000..5a0c91aaba3a
--- /dev/null
+++ b/drivers/pinctrl/tegra/pinctrl-tegra264.c
@@ -0,0 +1,2216 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Pinctrl data for the NVIDIA Tegra264 pinmux
+ *
+ * Copyright (c) 2024-2026, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-tegra.h"
+
+/* Define unique ID for each pins */
+enum {
+ TEGRA_PIN_PEX_L4_CLKREQ_N_PD0,
+ TEGRA_PIN_PEX_L4_RST_N_PD1,
+ TEGRA_PIN_PEX_L5_CLKREQ_N_PD2,
+ TEGRA_PIN_PEX_L5_RST_N_PD3,
+ TEGRA_PIN_ETH0_MDIO_PD4,
+ TEGRA_PIN_ETH0_MDC_PD5,
+ TEGRA_PIN_ETH3_MDIO_PD6,
+ TEGRA_PIN_ETH3_MDC_PD7,
+ TEGRA_PIN_ETH1_MDIO_PE0,
+ TEGRA_PIN_ETH1_MDC_PE1,
+ TEGRA_PIN_ETH2_MDIO_PE2,
+ TEGRA_PIN_ETH2_MDC_PE3,
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PB0,
+ TEGRA_PIN_PEX_L1_RST_N_PB1,
+ TEGRA_PIN_PEX_L2_CLKREQ_N_PB2,
+ TEGRA_PIN_PEX_L2_RST_N_PB3,
+ TEGRA_PIN_PEX_L3_CLKREQ_N_PB4,
+ TEGRA_PIN_PEX_L3_RST_N_PB5,
+ TEGRA_PIN_SOC_GPIO113_PB6,
+ TEGRA_PIN_SOC_GPIO114_PB7,
+ TEGRA_PIN_SGMII0_SMA_MDIO_PC0,
+ TEGRA_PIN_SGMII0_SMA_MDC_PC1,
+ TEGRA_PIN_PEX_WAKE_N_PC2,
+ TEGRA_PIN_PWM1_PA0,
+ TEGRA_PIN_PWM6_PA1,
+ TEGRA_PIN_PWM7_PA2,
+ TEGRA_PIN_PWM8_PA3,
+ TEGRA_PIN_UFS0_REF_CLK_PA4,
+ TEGRA_PIN_UFS0_RST_N_PA5,
+};
+
+enum {
+ TEGRA_PIN_SOC_GPIO250_PF0,
+ TEGRA_PIN_SOC_GPIO251_PF1,
+ TEGRA_PIN_SOC_GPIO252_PF2,
+ TEGRA_PIN_DP_AUX_CH0_HPD_PF3,
+ TEGRA_PIN_DP_AUX_CH1_HPD_PF4,
+ TEGRA_PIN_DP_AUX_CH2_HPD_PF5,
+ TEGRA_PIN_DP_AUX_CH3_HPD_PF6,
+ TEGRA_PIN_PWM2_PF7,
+ TEGRA_PIN_PWM3_PG0,
+ TEGRA_PIN_GEN7_I2C_SCL_PG1,
+ TEGRA_PIN_GEN7_I2C_SDA_PG2,
+ TEGRA_PIN_GEN9_I2C_SCL_PG3,
+ TEGRA_PIN_GEN9_I2C_SDA_PG4,
+ TEGRA_PIN_SDMMC1_CLK_PX0,
+ TEGRA_PIN_SDMMC1_CMD_PX1,
+ TEGRA_PIN_SDMMC1_DAT0_PX2,
+ TEGRA_PIN_SDMMC1_DAT1_PX3,
+ TEGRA_PIN_SDMMC1_DAT2_PX4,
+ TEGRA_PIN_SDMMC1_DAT3_PX5,
+ TEGRA_PIN_SDMMC1_COMP,
+ TEGRA_PIN_SOC_GPIO124_PL0,
+ TEGRA_PIN_SOC_GPIO125_PL1,
+ TEGRA_PIN_FAN_TACH0_PL2,
+ TEGRA_PIN_SOC_GPIO127_PL3,
+ TEGRA_PIN_SOC_GPIO128_PL4,
+ TEGRA_PIN_SOC_GPIO129_PL5,
+ TEGRA_PIN_SOC_GPIO130_PL6,
+ TEGRA_PIN_SOC_GPIO131_PL7,
+ TEGRA_PIN_GP_PWM9_PM0,
+ TEGRA_PIN_SOC_GPIO133_PM1,
+ TEGRA_PIN_UART9_TX_PM2,
+ TEGRA_PIN_UART9_RX_PM3,
+ TEGRA_PIN_UART9_RTS_N_PM4,
+ TEGRA_PIN_UART9_CTS_N_PM5,
+ TEGRA_PIN_SOC_GPIO170_PU0,
+ TEGRA_PIN_SOC_GPIO171_PU1,
+ TEGRA_PIN_SOC_GPIO172_PU2,
+ TEGRA_PIN_SOC_GPIO173_PU3,
+ TEGRA_PIN_SOC_GPIO174_PU4,
+ TEGRA_PIN_SOC_GPIO175_PU5,
+ TEGRA_PIN_SOC_GPIO176_PU6,
+ TEGRA_PIN_SOC_GPIO177_PU7,
+ TEGRA_PIN_SOC_GPIO178_PV0,
+ TEGRA_PIN_PWM10_PV1,
+ TEGRA_PIN_UART4_TX_PV2,
+ TEGRA_PIN_UART4_RX_PV3,
+ TEGRA_PIN_UART4_RTS_N_PV4,
+ TEGRA_PIN_UART4_CTS_N_PV5,
+ TEGRA_PIN_DAP2_CLK_PV6,
+ TEGRA_PIN_DAP2_DIN_PV7,
+ TEGRA_PIN_DAP2_DOUT_PW0,
+ TEGRA_PIN_DAP2_FS_PW1,
+ TEGRA_PIN_GEN1_I2C_SCL_PW2,
+ TEGRA_PIN_GEN1_I2C_SDA_PW3,
+ TEGRA_PIN_GEN0_I2C_SCL_PW4,
+ TEGRA_PIN_GEN0_I2C_SDA_PW5,
+ TEGRA_PIN_PWR_I2C_SCL_PW6,
+ TEGRA_PIN_PWR_I2C_SDA_PW7,
+ TEGRA_PIN_SOC_GPIO138_PP0,
+ TEGRA_PIN_SOC_GPIO139_PP1,
+ TEGRA_PIN_DAP6_SCLK_PP2,
+ TEGRA_PIN_DAP6_DOUT_PP3,
+ TEGRA_PIN_DAP6_DIN_PP4,
+ TEGRA_PIN_DAP6_FS_PP5,
+ TEGRA_PIN_DAP4_SCLK_PP6,
+ TEGRA_PIN_DAP4_DOUT_PP7,
+ TEGRA_PIN_DAP4_DIN_PQ0,
+ TEGRA_PIN_DAP4_FS_PQ1,
+ TEGRA_PIN_SPI5_SCK_PQ2,
+ TEGRA_PIN_SPI5_MISO_PQ3,
+ TEGRA_PIN_SPI5_MOSI_PQ4,
+ TEGRA_PIN_SPI5_CS0_PQ5,
+ TEGRA_PIN_SOC_GPIO152_PQ6,
+ TEGRA_PIN_SOC_GPIO153_PQ7,
+ TEGRA_PIN_AUD_MCLK_PR0,
+ TEGRA_PIN_SOC_GPIO155_PR1,
+ TEGRA_PIN_DAP1_SCLK_PR2,
+ TEGRA_PIN_DAP1_OUT_PR3,
+ TEGRA_PIN_DAP1_IN_PR4,
+ TEGRA_PIN_DAP1_FS_PR5,
+ TEGRA_PIN_GEN11_I2C_SCL_PR6,
+ TEGRA_PIN_GEN11_I2C_SDA_PR7,
+ TEGRA_PIN_SOC_GPIO350_PS0,
+ TEGRA_PIN_SOC_GPIO351_PS1,
+ TEGRA_PIN_QSPI0_SCK_PT0,
+ TEGRA_PIN_QSPI0_CS_N_PT1,
+ TEGRA_PIN_QSPI0_IO0_PT2,
+ TEGRA_PIN_QSPI0_IO1_PT3,
+ TEGRA_PIN_QSPI0_IO2_PT4,
+ TEGRA_PIN_QSPI0_IO3_PT5,
+ TEGRA_PIN_SOC_GPIO192_PT6,
+ TEGRA_PIN_SOC_GPIO270_PY0,
+ TEGRA_PIN_SOC_GPIO271_PY1,
+ TEGRA_PIN_SOC_GPIO272_PY2,
+ TEGRA_PIN_SOC_GPIO273_PY3,
+ TEGRA_PIN_SOC_GPIO274_PY4,
+ TEGRA_PIN_SOC_GPIO275_PY5,
+ TEGRA_PIN_SOC_GPIO276_PY6,
+ TEGRA_PIN_SOC_GPIO277_PY7,
+ TEGRA_PIN_SOC_GPIO278_PZ0,
+ TEGRA_PIN_SOC_GPIO279_PZ1,
+ TEGRA_PIN_XHALT_TRIG_PZ2,
+ TEGRA_PIN_SOC_GPIO281_PZ3,
+ TEGRA_PIN_SOC_GPIO282_PZ4,
+ TEGRA_PIN_SOC_GPIO283_PZ5,
+ TEGRA_PIN_SOC_GPIO284_PZ6,
+ TEGRA_PIN_SOC_GPIO285_PZ7,
+ TEGRA_PIN_SOC_GPIO286_PAL0,
+ TEGRA_PIN_SOC_GPIO287_PAL1,
+ TEGRA_PIN_SOC_GPIO288_PAL2,
+ TEGRA_PIN_CPU_PWR_REQ_PH0,
+ TEGRA_PIN_GPU_PWR_REQ_PH1,
+ TEGRA_PIN_UART10_TX_PH2,
+ TEGRA_PIN_UART10_RX_PH3,
+ TEGRA_PIN_UART10_RTS_N_PH4,
+ TEGRA_PIN_UART10_CTS_N_PH5,
+ TEGRA_PIN_SPI3_SCK_PH6,
+ TEGRA_PIN_SPI3_MISO_PH7,
+ TEGRA_PIN_SPI3_MOSI_PJ0,
+ TEGRA_PIN_SPI3_CS0_PJ1,
+ TEGRA_PIN_SPI3_CS3_PJ2,
+ TEGRA_PIN_UART5_TX_PJ3,
+ TEGRA_PIN_UART5_RX_PJ4,
+ TEGRA_PIN_UART5_RTS_N_PJ5,
+ TEGRA_PIN_UART5_CTS_N_PJ6,
+ TEGRA_PIN_SPI1_SCK_PJ7,
+ TEGRA_PIN_SPI1_MISO_PK0,
+ TEGRA_PIN_SPI1_MOSI_PK1,
+ TEGRA_PIN_SPI1_CS0_PK2,
+ TEGRA_PIN_SPI1_CS1_PK3,
+ TEGRA_PIN_EXTPERIPH1_CLK_PK4,
+ TEGRA_PIN_EXTPERIPH2_CLK_PK5,
+ TEGRA_PIN_GEN12_I2C_SCL_PK6,
+ TEGRA_PIN_GEN12_I2C_SDA_PK7,
+};
+
+enum {
+ TEGRA_PIN_SOC_GPIO00_PAA0,
+ TEGRA_PIN_VCOMP_ALERT_PAA1,
+ TEGRA_PIN_AO_RETENTION_N_PAA2,
+ TEGRA_PIN_BATT_OC_PAA3,
+ TEGRA_PIN_BOOTV_CTL_N_PAA4,
+ TEGRA_PIN_POWER_ON_PAA5,
+ TEGRA_PIN_HDMI_CEC_PAA6,
+ TEGRA_PIN_SOC_GPIO07_PAA7,
+ TEGRA_PIN_SOC_GPIO08_PBB0,
+ TEGRA_PIN_SOC_GPIO09_PBB1,
+ TEGRA_PIN_GEN2_I2C_SCL_PCC0,
+ TEGRA_PIN_GEN2_I2C_SDA_PCC1,
+ TEGRA_PIN_GEN3_I2C_SCL_PCC2,
+ TEGRA_PIN_GEN3_I2C_SDA_PCC3,
+ TEGRA_PIN_GP_PWM4_PCC4,
+ TEGRA_PIN_UART0_TX_PCC5,
+ TEGRA_PIN_UART0_RX_PCC6,
+ TEGRA_PIN_SPI2_SCK_PCC7,
+ TEGRA_PIN_SPI2_MISO_PDD0,
+ TEGRA_PIN_SPI2_MOSI_PDD1,
+ TEGRA_PIN_SPI2_CS0_N_PDD2,
+ TEGRA_PIN_SOC_GPIO21_PDD3,
+ TEGRA_PIN_SOC_GPIO22_PDD4,
+ TEGRA_PIN_SOC_GPIO23_PDD5,
+ TEGRA_PIN_SOC_GPIO24_PDD6,
+ TEGRA_PIN_SOC_GPIO25_PDD7,
+ TEGRA_PIN_SOC_GPIO26_PEE0,
+ TEGRA_PIN_SOC_GPIO27_PEE1,
+ TEGRA_PIN_SOC_GPIO28_PEE2,
+ TEGRA_PIN_SOC_GPIO29_PEE3,
+};
+
+static const struct pinctrl_pin_desc tegra264_uphy_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, "PEX_L4_CLKREQ_N_PD0"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PD1, "PEX_L4_RST_N_PD1"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, "PEX_L5_CLKREQ_N_PD2"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PD3, "PEX_L5_RST_N_PD3"),
+ PINCTRL_PIN(TEGRA_PIN_ETH0_MDIO_PD4, "ETH0_MDIO_PD4"),
+ PINCTRL_PIN(TEGRA_PIN_ETH0_MDC_PD5, "ETH0_MDC_PD5"),
+ PINCTRL_PIN(TEGRA_PIN_ETH3_MDIO_PD6, "ETH3_MDIO_PD6"),
+ PINCTRL_PIN(TEGRA_PIN_ETH3_MDC_PD7, "ETH3_MDC_PD7"),
+ PINCTRL_PIN(TEGRA_PIN_ETH1_MDIO_PE0, "ETH1_MDIO_PE0"),
+ PINCTRL_PIN(TEGRA_PIN_ETH1_MDC_PE1, "ETH1_MDC_PE1"),
+ PINCTRL_PIN(TEGRA_PIN_ETH2_MDIO_PE2, "ETH2_MDIO_PE2"),
+ PINCTRL_PIN(TEGRA_PIN_ETH2_MDC_PE3, "ETH2_MDC_PE3"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, "PEX_L1_CLKREQ_N_PB0"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PB1, "PEX_L1_RST_N_PB1"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, "PEX_L2_CLKREQ_N_PB2"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PB3, "PEX_L2_RST_N_PB3"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, "PEX_L3_CLKREQ_N_PB4"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PB5, "PEX_L3_RST_N_PB5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO113_PB6, "SOC_GPIO113_PB6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO114_PB7, "SOC_GPIO114_PB7"),
+ PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDIO_PC0, "SGMII0_SMA_MDIO_PC0"),
+ PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDC_PC1, "SGMII0_SMA_MDC_PC1"),
+ PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PC2, "PEX_WAKE_N_PC2"),
+ PINCTRL_PIN(TEGRA_PIN_PWM1_PA0, "PWM1_PA0"),
+ PINCTRL_PIN(TEGRA_PIN_PWM6_PA1, "PWM6_PA1"),
+ PINCTRL_PIN(TEGRA_PIN_PWM7_PA2, "PWM7_PA2"),
+ PINCTRL_PIN(TEGRA_PIN_PWM8_PA3, "PWM8_PA3"),
+ PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PA4, "UFS0_REF_CLK_PA4"),
+ PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PA5, "UFS0_RST_N_PA5"),
+};
+
+static const struct pinctrl_pin_desc tegra264_main_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO250_PF0, "SOC_GPIO250_PF0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO251_PF1, "SOC_GPIO251_PF1"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO252_PF2, "SOC_GPIO252_PF2"),
+ PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PF3, "DP_AUX_CH0_HPD_PF3"),
+ PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PF4, "DP_AUX_CH1_HPD_PF4"),
+ PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PF5, "DP_AUX_CH2_HPD_PF5"),
+ PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PF6, "DP_AUX_CH3_HPD_PF6"),
+ PINCTRL_PIN(TEGRA_PIN_PWM2_PF7, "PWM2_PF7"),
+ PINCTRL_PIN(TEGRA_PIN_PWM3_PG0, "PWM3_PG0"),
+ PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PG1, "GEN7_I2C_SCL_PG1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PG2, "GEN7_I2C_SDA_PG2"),
+ PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PG3, "GEN9_I2C_SCL_PG3"),
+ PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PG4, "GEN9_I2C_SDA_PG4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PX0, "SDMMC1_CLK_PX0"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PX1, "SDMMC1_CMD_PX1"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PX2, "SDMMC1_DAT0_PX2"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PX3, "SDMMC1_DAT1_PX3"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PX4, "SDMMC1_DAT2_PX4"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PX5, "SDMMC1_DAT3_PX5"),
+ PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
+ PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH0, "CPU_PWR_REQ_PH0"),
+ PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH1, "GPU_PWR_REQ_PH1"),
+ PINCTRL_PIN(TEGRA_PIN_UART10_TX_PH2, "UART10_TX_PH2"),
+ PINCTRL_PIN(TEGRA_PIN_UART10_RX_PH3, "UART10_RX_PH3"),
+ PINCTRL_PIN(TEGRA_PIN_UART10_RTS_N_PH4, "UART10_RTS_N_PH4"),
+ PINCTRL_PIN(TEGRA_PIN_UART10_CTS_N_PH5, "UART10_CTS_N_PH5"),
+ PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PH6, "SPI3_SCK_PH6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PH7, "SPI3_MISO_PH7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PJ0, "SPI3_MOSI_PJ0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PJ1, "SPI3_CS0_PJ1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI3_CS3_PJ2, "SPI3_CS3_PJ2"),
+ PINCTRL_PIN(TEGRA_PIN_UART5_TX_PJ3, "UART5_TX_PJ3"),
+ PINCTRL_PIN(TEGRA_PIN_UART5_RX_PJ4, "UART5_RX_PJ4"),
+ PINCTRL_PIN(TEGRA_PIN_UART5_RTS_N_PJ5, "UART5_RTS_N_PJ5"),
+ PINCTRL_PIN(TEGRA_PIN_UART5_CTS_N_PJ6, "UART5_CTS_N_PJ6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PJ7, "SPI1_SCK_PJ7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PK0, "SPI1_MISO_PK0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PK1, "SPI1_MOSI_PK1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PK2, "SPI1_CS0_PK2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PK3, "SPI1_CS1_PK3"),
+ PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PK4, "EXTPERIPH1_CLK_PK4"),
+ PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PK5, "EXTPERIPH2_CLK_PK5"),
+ PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SCL_PK6, "GEN12_I2C_SCL_PK6"),
+ PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SDA_PK7, "GEN12_I2C_SDA_PK7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO124_PL0, "SOC_GPIO124_PL0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO125_PL1, "SOC_GPIO125_PL1"),
+ PINCTRL_PIN(TEGRA_PIN_FAN_TACH0_PL2, "FAN_TACH0_PL2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO127_PL3, "SOC_GPIO127_PL3"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO128_PL4, "SOC_GPIO128_PL4"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO129_PL5, "SOC_GPIO129_PL5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO130_PL6, "SOC_GPIO130_PL6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO131_PL7, "SOC_GPIO131_PL7"),
+ PINCTRL_PIN(TEGRA_PIN_GP_PWM9_PM0, "GP_PWM9_PM0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO133_PM1, "SOC_GPIO133_PM1"),
+ PINCTRL_PIN(TEGRA_PIN_UART9_TX_PM2, "UART9_TX_PM2"),
+ PINCTRL_PIN(TEGRA_PIN_UART9_RX_PM3, "UART9_RX_PM3"),
+ PINCTRL_PIN(TEGRA_PIN_UART9_RTS_N_PM4, "UART9_RTS_N_PM4"),
+ PINCTRL_PIN(TEGRA_PIN_UART9_CTS_N_PM5, "UART9_CTS_N_PM5"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PT0, "QSPI0_SCK_PT0"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PT1, "QSPI0_CS_N_PT1"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PT2, "QSPI0_IO0_PT2"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PT3, "QSPI0_IO1_PT3"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PT4, "QSPI0_IO2_PT4"),
+ PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PT5, "QSPI0_IO3_PT5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO192_PT6, "SOC_GPIO192_PT6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PU0, "SOC_GPIO170_PU0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PU1, "SOC_GPIO171_PU1"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PU2, "SOC_GPIO172_PU2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PU3, "SOC_GPIO173_PU3"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO174_PU4, "SOC_GPIO174_PU4"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO175_PU5, "SOC_GPIO175_PU5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO176_PU6, "SOC_GPIO176_PU6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO177_PU7, "SOC_GPIO177_PU7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO178_PV0, "SOC_GPIO178_PV0"),
+ PINCTRL_PIN(TEGRA_PIN_PWM10_PV1, "PWM10_PV1"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_TX_PV2, "UART4_TX_PV2"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_RX_PV3, "UART4_RX_PV3"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"),
+ PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, "DAP2_DIN_PV7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, "DAP2_DOUT_PW0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"),
+ PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"),
+ PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SCL_PW4, "GEN0_I2C_SCL_PW4"),
+ PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SDA_PW5, "GEN0_I2C_SDA_PW5"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PW6, "PWR_I2C_SCL_PW6"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PW7, "PWR_I2C_SDA_PW7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO270_PY0, "SOC_GPIO270_PY0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO271_PY1, "SOC_GPIO271_PY1"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO272_PY2, "SOC_GPIO272_PY2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO273_PY3, "SOC_GPIO273_PY3"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO274_PY4, "SOC_GPIO274_PY4"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO275_PY5, "SOC_GPIO275_PY5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO276_PY6, "SOC_GPIO276_PY6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO277_PY7, "SOC_GPIO277_PY7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO278_PZ0, "SOC_GPIO278_PZ0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO279_PZ1, "SOC_GPIO279_PZ1"),
+ PINCTRL_PIN(TEGRA_PIN_XHALT_TRIG_PZ2, "XHALT_TRIG_PZ2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO281_PZ3, "SOC_GPIO281_PZ3"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO282_PZ4, "SOC_GPIO282_PZ4"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO283_PZ5, "SOC_GPIO283_PZ5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO284_PZ6, "SOC_GPIO284_PZ6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO285_PZ7, "SOC_GPIO285_PZ7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO286_PAL0, "SOC_GPIO286_PAL0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO287_PAL1, "SOC_GPIO287_PAL1"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO288_PAL2, "SOC_GPIO288_PAL2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO138_PP0, "SOC_GPIO138_PP0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO139_PP1, "SOC_GPIO139_PP1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PP2, "DAP6_SCLK_PP2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PP3, "DAP6_DOUT_PP3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PP4, "DAP6_DIN_PP4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PP5, "DAP6_FS_PP5"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP6, "DAP4_SCLK_PP6"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP7, "DAP4_DOUT_PP7"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PQ0, "DAP4_DIN_PQ0"),
+ PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PQ1, "DAP4_FS_PQ1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PQ2, "SPI5_SCK_PQ2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PQ3, "SPI5_MISO_PQ3"),
+ PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PQ4, "SPI5_MOSI_PQ4"),
+ PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PQ5, "SPI5_CS0_PQ5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PQ6, "SOC_GPIO152_PQ6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PQ7, "SOC_GPIO153_PQ7"),
+ PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PR0, "AUD_MCLK_PR0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PR1, "SOC_GPIO155_PR1"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PR2, "DAP1_SCLK_PR2"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_OUT_PR3, "DAP1_OUT_PR3"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_IN_PR4, "DAP1_IN_PR4"),
+ PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PR5, "DAP1_FS_PR5"),
+ PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SCL_PR6, "GEN11_I2C_SCL_PR6"),
+ PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SDA_PR7, "GEN11_I2C_SDA_PR7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO350_PS0, "SOC_GPIO350_PS0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO351_PS1, "SOC_GPIO351_PS1"),
+
+};
+
+static const struct pinctrl_pin_desc tegra264_aon_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA0, "SOC_GPIO00_PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA1, "VCOMP_ALERT_PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PAA2, "AO_RETENTION_N_PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA3, "BATT_OC_PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA4, "BOOTV_CTL_N_PAA4"),
+ PINCTRL_PIN(TEGRA_PIN_POWER_ON_PAA5, "POWER_ON_PAA5"),
+ PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PAA6, "HDMI_CEC_PAA6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PAA7, "SOC_GPIO07_PAA7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PBB0, "SOC_GPIO08_PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PBB1, "SOC_GPIO09_PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC0, "GEN2_I2C_SCL_PCC0"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PCC1, "GEN2_I2C_SDA_PCC1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PCC2, "GEN3_I2C_SCL_PCC2"),
+ PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PCC3, "GEN3_I2C_SDA_PCC3"),
+ PINCTRL_PIN(TEGRA_PIN_GP_PWM4_PCC4, "GP_PWM4_PCC4"),
+ PINCTRL_PIN(TEGRA_PIN_UART0_TX_PCC5, "UART0_TX_PCC5"),
+ PINCTRL_PIN(TEGRA_PIN_UART0_RX_PCC6, "UART0_RX_PCC6"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC7, "SPI2_SCK_PCC7"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PDD0, "SPI2_MISO_PDD0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PDD1, "SPI2_MOSI_PDD1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PDD2, "SPI2_CS0_N_PDD2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PDD3, "SOC_GPIO21_PDD3"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PDD4, "SOC_GPIO22_PDD4"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PDD5, "SOC_GPIO23_PDD5"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PDD6, "SOC_GPIO24_PDD6"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PDD7, "SOC_GPIO25_PDD7"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE0, "SOC_GPIO26_PEE0"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE1, "SOC_GPIO27_PEE1"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PEE2, "SOC_GPIO28_PEE2"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PEE3, "SOC_GPIO29_PEE3"),
+};
+
+static const unsigned int soc_gpio250_pf0_pins[] = {
+ TEGRA_PIN_SOC_GPIO250_PF0,
+};
+
+static const unsigned int soc_gpio251_pf1_pins[] = {
+ TEGRA_PIN_SOC_GPIO251_PF1,
+};
+
+static const unsigned int soc_gpio252_pf2_pins[] = {
+ TEGRA_PIN_SOC_GPIO252_PF2,
+};
+
+static const unsigned int dp_aux_ch0_hpd_pf3_pins[] = {
+ TEGRA_PIN_DP_AUX_CH0_HPD_PF3,
+};
+
+static const unsigned int dp_aux_ch1_hpd_pf4_pins[] = {
+ TEGRA_PIN_DP_AUX_CH1_HPD_PF4,
+};
+
+static const unsigned int dp_aux_ch2_hpd_pf5_pins[] = {
+ TEGRA_PIN_DP_AUX_CH2_HPD_PF5,
+};
+
+static const unsigned int dp_aux_ch3_hpd_pf6_pins[] = {
+ TEGRA_PIN_DP_AUX_CH3_HPD_PF6,
+};
+
+static const unsigned int pwm2_pf7_pins[] = {
+ TEGRA_PIN_PWM2_PF7,
+};
+
+static const unsigned int pwm3_pg0_pins[] = {
+ TEGRA_PIN_PWM3_PG0,
+};
+
+static const unsigned int gen7_i2c_scl_pg1_pins[] = {
+ TEGRA_PIN_GEN7_I2C_SCL_PG1,
+};
+
+static const unsigned int gen7_i2c_sda_pg2_pins[] = {
+ TEGRA_PIN_GEN7_I2C_SDA_PG2,
+};
+
+static const unsigned int gen9_i2c_scl_pg3_pins[] = {
+ TEGRA_PIN_GEN9_I2C_SCL_PG3,
+};
+
+static const unsigned int gen9_i2c_sda_pg4_pins[] = {
+ TEGRA_PIN_GEN9_I2C_SDA_PG4,
+};
+
+static const unsigned int pwm1_pa0_pins[] = {
+ TEGRA_PIN_PWM1_PA0,
+};
+
+static const unsigned int pwm6_pa1_pins[] = {
+ TEGRA_PIN_PWM6_PA1,
+};
+
+static const unsigned int pwm7_pa2_pins[] = {
+ TEGRA_PIN_PWM7_PA2,
+};
+
+static const unsigned int pwm8_pa3_pins[] = {
+ TEGRA_PIN_PWM8_PA3,
+};
+
+static const unsigned int ufs0_ref_clk_pa4_pins[] = {
+ TEGRA_PIN_UFS0_REF_CLK_PA4,
+};
+
+static const unsigned int ufs0_rst_n_pa5_pins[] = {
+ TEGRA_PIN_UFS0_RST_N_PA5,
+};
+
+static const unsigned int pex_l1_clkreq_n_pb0_pins[] = {
+ TEGRA_PIN_PEX_L1_CLKREQ_N_PB0,
+};
+
+static const unsigned int pex_l1_rst_n_pb1_pins[] = {
+ TEGRA_PIN_PEX_L1_RST_N_PB1,
+};
+
+static const unsigned int pex_l2_clkreq_n_pb2_pins[] = {
+ TEGRA_PIN_PEX_L2_CLKREQ_N_PB2,
+};
+
+static const unsigned int pex_l2_rst_n_pb3_pins[] = {
+ TEGRA_PIN_PEX_L2_RST_N_PB3,
+};
+
+static const unsigned int pex_l3_clkreq_n_pb4_pins[] = {
+ TEGRA_PIN_PEX_L3_CLKREQ_N_PB4,
+};
+
+static const unsigned int pex_l3_rst_n_pb5_pins[] = {
+ TEGRA_PIN_PEX_L3_RST_N_PB5,
+};
+
+static const unsigned int soc_gpio113_pb6_pins[] = {
+ TEGRA_PIN_SOC_GPIO113_PB6,
+};
+
+static const unsigned int soc_gpio114_pb7_pins[] = {
+ TEGRA_PIN_SOC_GPIO114_PB7,
+};
+
+static const unsigned int sgmii0_sma_mdio_pc0_pins[] = {
+ TEGRA_PIN_SGMII0_SMA_MDIO_PC0,
+};
+
+static const unsigned int sgmii0_sma_mdc_pc1_pins[] = {
+ TEGRA_PIN_SGMII0_SMA_MDC_PC1,
+};
+
+static const unsigned int pex_wake_n_pc2_pins[] = {
+ TEGRA_PIN_PEX_WAKE_N_PC2,
+};
+
+static const unsigned int pex_l4_clkreq_n_pd0_pins[] = {
+ TEGRA_PIN_PEX_L4_CLKREQ_N_PD0,
+};
+
+static const unsigned int pex_l4_rst_n_pd1_pins[] = {
+ TEGRA_PIN_PEX_L4_RST_N_PD1,
+};
+
+static const unsigned int pex_l5_clkreq_n_pd2_pins[] = {
+ TEGRA_PIN_PEX_L5_CLKREQ_N_PD2,
+};
+
+static const unsigned int pex_l5_rst_n_pd3_pins[] = {
+ TEGRA_PIN_PEX_L5_RST_N_PD3,
+};
+
+static const unsigned int eth0_mdio_pd4_pins[] = {
+ TEGRA_PIN_ETH0_MDIO_PD4,
+};
+
+static const unsigned int eth0_mdc_pd5_pins[] = {
+ TEGRA_PIN_ETH0_MDC_PD5,
+};
+
+static const unsigned int eth3_mdio_pd6_pins[] = {
+ TEGRA_PIN_ETH3_MDIO_PD6,
+};
+
+static const unsigned int eth3_mdc_pd7_pins[] = {
+ TEGRA_PIN_ETH3_MDC_PD7,
+};
+
+static const unsigned int eth1_mdio_pe0_pins[] = {
+ TEGRA_PIN_ETH1_MDIO_PE0,
+};
+
+static const unsigned int eth1_mdc_pe1_pins[] = {
+ TEGRA_PIN_ETH1_MDC_PE1,
+};
+
+static const unsigned int eth2_mdio_pe2_pins[] = {
+ TEGRA_PIN_ETH2_MDIO_PE2,
+};
+
+static const unsigned int eth2_mdc_pe3_pins[] = {
+ TEGRA_PIN_ETH2_MDC_PE3,
+};
+
+static const unsigned int sdmmc1_clk_px0_pins[] = {
+ TEGRA_PIN_SDMMC1_CLK_PX0,
+};
+
+static const unsigned int sdmmc1_cmd_px1_pins[] = {
+ TEGRA_PIN_SDMMC1_CMD_PX1,
+};
+
+static const unsigned int sdmmc1_dat0_px2_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT0_PX2,
+};
+
+static const unsigned int sdmmc1_dat1_px3_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT1_PX3,
+};
+
+static const unsigned int sdmmc1_dat2_px4_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT2_PX4,
+};
+
+static const unsigned int sdmmc1_dat3_px5_pins[] = {
+ TEGRA_PIN_SDMMC1_DAT3_PX5,
+};
+
+static const unsigned int sdmmc1_comp_pins[] = {
+ TEGRA_PIN_SDMMC1_COMP,
+};
+
+static const unsigned int cpu_pwr_req_ph0_pins[] = {
+ TEGRA_PIN_CPU_PWR_REQ_PH0,
+};
+
+static const unsigned int gpu_pwr_req_ph1_pins[] = {
+ TEGRA_PIN_GPU_PWR_REQ_PH1,
+};
+
+static const unsigned int uart10_tx_ph2_pins[] = {
+ TEGRA_PIN_UART10_TX_PH2,
+};
+
+static const unsigned int uart10_rx_ph3_pins[] = {
+ TEGRA_PIN_UART10_RX_PH3,
+};
+
+static const unsigned int uart10_rts_n_ph4_pins[] = {
+ TEGRA_PIN_UART10_RTS_N_PH4,
+};
+
+static const unsigned int uart10_cts_n_ph5_pins[] = {
+ TEGRA_PIN_UART10_CTS_N_PH5,
+};
+
+static const unsigned int spi3_sck_ph6_pins[] = {
+ TEGRA_PIN_SPI3_SCK_PH6,
+};
+
+static const unsigned int spi3_miso_ph7_pins[] = {
+ TEGRA_PIN_SPI3_MISO_PH7,
+};
+
+static const unsigned int spi3_mosi_pj0_pins[] = {
+ TEGRA_PIN_SPI3_MOSI_PJ0,
+};
+
+static const unsigned int spi3_cs0_pj1_pins[] = {
+ TEGRA_PIN_SPI3_CS0_PJ1,
+};
+
+static const unsigned int spi3_cs3_pj2_pins[] = {
+ TEGRA_PIN_SPI3_CS3_PJ2,
+};
+
+static const unsigned int uart5_tx_pj3_pins[] = {
+ TEGRA_PIN_UART5_TX_PJ3,
+};
+
+static const unsigned int uart5_rx_pj4_pins[] = {
+ TEGRA_PIN_UART5_RX_PJ4,
+};
+
+static const unsigned int uart5_rts_n_pj5_pins[] = {
+ TEGRA_PIN_UART5_RTS_N_PJ5,
+};
+
+static const unsigned int uart5_cts_n_pj6_pins[] = {
+ TEGRA_PIN_UART5_CTS_N_PJ6,
+};
+
+static const unsigned int spi1_sck_pj7_pins[] = {
+ TEGRA_PIN_SPI1_SCK_PJ7,
+};
+
+static const unsigned int spi1_miso_pk0_pins[] = {
+ TEGRA_PIN_SPI1_MISO_PK0,
+};
+
+static const unsigned int spi1_mosi_pk1_pins[] = {
+ TEGRA_PIN_SPI1_MOSI_PK1,
+};
+
+static const unsigned int spi1_cs0_pk2_pins[] = {
+ TEGRA_PIN_SPI1_CS0_PK2,
+};
+
+static const unsigned int spi1_cs1_pk3_pins[] = {
+ TEGRA_PIN_SPI1_CS1_PK3,
+};
+
+static const unsigned int extperiph1_clk_pk4_pins[] = {
+ TEGRA_PIN_EXTPERIPH1_CLK_PK4,
+};
+
+static const unsigned int extperiph2_clk_pk5_pins[] = {
+ TEGRA_PIN_EXTPERIPH2_CLK_PK5,
+};
+
+static const unsigned int gen12_i2c_scl_pk6_pins[] = {
+ TEGRA_PIN_GEN12_I2C_SCL_PK6,
+};
+
+static const unsigned int gen12_i2c_sda_pk7_pins[] = {
+ TEGRA_PIN_GEN12_I2C_SDA_PK7,
+};
+
+static const unsigned int soc_gpio124_pl0_pins[] = {
+ TEGRA_PIN_SOC_GPIO124_PL0,
+};
+
+static const unsigned int soc_gpio125_pl1_pins[] = {
+ TEGRA_PIN_SOC_GPIO125_PL1,
+};
+
+static const unsigned int fan_tach0_pl2_pins[] = {
+ TEGRA_PIN_FAN_TACH0_PL2,
+};
+
+static const unsigned int soc_gpio127_pl3_pins[] = {
+ TEGRA_PIN_SOC_GPIO127_PL3,
+};
+
+static const unsigned int soc_gpio128_pl4_pins[] = {
+ TEGRA_PIN_SOC_GPIO128_PL4,
+};
+
+static const unsigned int soc_gpio129_pl5_pins[] = {
+ TEGRA_PIN_SOC_GPIO129_PL5,
+};
+
+static const unsigned int soc_gpio130_pl6_pins[] = {
+ TEGRA_PIN_SOC_GPIO130_PL6,
+};
+
+static const unsigned int soc_gpio131_pl7_pins[] = {
+ TEGRA_PIN_SOC_GPIO131_PL7,
+};
+
+static const unsigned int gp_pwm9_pm0_pins[] = {
+ TEGRA_PIN_GP_PWM9_PM0,
+};
+
+static const unsigned int soc_gpio133_pm1_pins[] = {
+ TEGRA_PIN_SOC_GPIO133_PM1,
+};
+
+static const unsigned int uart9_tx_pm2_pins[] = {
+ TEGRA_PIN_UART9_TX_PM2,
+};
+
+static const unsigned int uart9_rx_pm3_pins[] = {
+ TEGRA_PIN_UART9_RX_PM3,
+};
+
+static const unsigned int uart9_rts_n_pm4_pins[] = {
+ TEGRA_PIN_UART9_RTS_N_PM4,
+};
+
+static const unsigned int uart9_cts_n_pm5_pins[] = {
+ TEGRA_PIN_UART9_CTS_N_PM5,
+};
+
+static const unsigned int soc_gpio170_pu0_pins[] = {
+ TEGRA_PIN_SOC_GPIO170_PU0,
+};
+
+static const unsigned int soc_gpio171_pu1_pins[] = {
+ TEGRA_PIN_SOC_GPIO171_PU1,
+};
+
+static const unsigned int soc_gpio172_pu2_pins[] = {
+ TEGRA_PIN_SOC_GPIO172_PU2,
+};
+
+static const unsigned int soc_gpio173_pu3_pins[] = {
+ TEGRA_PIN_SOC_GPIO173_PU3,
+};
+
+static const unsigned int soc_gpio174_pu4_pins[] = {
+ TEGRA_PIN_SOC_GPIO174_PU4,
+};
+
+static const unsigned int soc_gpio175_pu5_pins[] = {
+ TEGRA_PIN_SOC_GPIO175_PU5,
+};
+
+static const unsigned int soc_gpio176_pu6_pins[] = {
+ TEGRA_PIN_SOC_GPIO176_PU6,
+};
+
+static const unsigned int soc_gpio177_pu7_pins[] = {
+ TEGRA_PIN_SOC_GPIO177_PU7,
+};
+
+static const unsigned int soc_gpio178_pv0_pins[] = {
+ TEGRA_PIN_SOC_GPIO178_PV0,
+};
+
+static const unsigned int pwm10_pv1_pins[] = {
+ TEGRA_PIN_PWM10_PV1,
+};
+
+static const unsigned int uart4_tx_pv2_pins[] = {
+ TEGRA_PIN_UART4_TX_PV2,
+};
+
+static const unsigned int uart4_rx_pv3_pins[] = {
+ TEGRA_PIN_UART4_RX_PV3,
+};
+
+static const unsigned int uart4_rts_n_pv4_pins[] = {
+ TEGRA_PIN_UART4_RTS_N_PV4,
+};
+
+static const unsigned int uart4_cts_n_pv5_pins[] = {
+ TEGRA_PIN_UART4_CTS_N_PV5,
+};
+
+static const unsigned int dap2_clk_pv6_pins[] = {
+ TEGRA_PIN_DAP2_CLK_PV6,
+};
+
+static const unsigned int dap2_din_pv7_pins[] = {
+ TEGRA_PIN_DAP2_DIN_PV7,
+};
+
+static const unsigned int dap2_dout_pw0_pins[] = {
+ TEGRA_PIN_DAP2_DOUT_PW0,
+};
+
+static const unsigned int dap2_fs_pw1_pins[] = {
+ TEGRA_PIN_DAP2_FS_PW1,
+};
+
+static const unsigned int gen1_i2c_scl_pw2_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SCL_PW2,
+};
+
+static const unsigned int gen1_i2c_sda_pw3_pins[] = {
+ TEGRA_PIN_GEN1_I2C_SDA_PW3,
+};
+
+static const unsigned int gen0_i2c_scl_pw4_pins[] = {
+ TEGRA_PIN_GEN0_I2C_SCL_PW4,
+};
+
+static const unsigned int gen0_i2c_sda_pw5_pins[] = {
+ TEGRA_PIN_GEN0_I2C_SDA_PW5,
+};
+
+static const unsigned int pwr_i2c_scl_pw6_pins[] = {
+ TEGRA_PIN_PWR_I2C_SCL_PW6,
+};
+
+static const unsigned int pwr_i2c_sda_pw7_pins[] = {
+ TEGRA_PIN_PWR_I2C_SDA_PW7,
+};
+
+static const unsigned int qspi0_sck_pt0_pins[] = {
+ TEGRA_PIN_QSPI0_SCK_PT0,
+};
+
+static const unsigned int qspi0_cs_n_pt1_pins[] = {
+ TEGRA_PIN_QSPI0_CS_N_PT1,
+};
+
+static const unsigned int qspi0_io0_pt2_pins[] = {
+ TEGRA_PIN_QSPI0_IO0_PT2,
+};
+
+static const unsigned int qspi0_io1_pt3_pins[] = {
+ TEGRA_PIN_QSPI0_IO1_PT3,
+};
+
+static const unsigned int qspi0_io2_pt4_pins[] = {
+ TEGRA_PIN_QSPI0_IO2_PT4,
+};
+
+static const unsigned int qspi0_io3_pt5_pins[] = {
+ TEGRA_PIN_QSPI0_IO3_PT5,
+};
+
+static const unsigned int soc_gpio192_pt6_pins[] = {
+ TEGRA_PIN_SOC_GPIO192_PT6,
+};
+
+static const unsigned int soc_gpio138_pp0_pins[] = {
+ TEGRA_PIN_SOC_GPIO138_PP0,
+};
+
+static const unsigned int soc_gpio139_pp1_pins[] = {
+ TEGRA_PIN_SOC_GPIO139_PP1,
+};
+
+static const unsigned int dap6_sclk_pp2_pins[] = {
+ TEGRA_PIN_DAP6_SCLK_PP2,
+};
+
+static const unsigned int dap6_dout_pp3_pins[] = {
+ TEGRA_PIN_DAP6_DOUT_PP3,
+};
+
+static const unsigned int dap6_din_pp4_pins[] = {
+ TEGRA_PIN_DAP6_DIN_PP4,
+};
+
+static const unsigned int dap6_fs_pp5_pins[] = {
+ TEGRA_PIN_DAP6_FS_PP5,
+};
+
+static const unsigned int dap4_sclk_pp6_pins[] = {
+ TEGRA_PIN_DAP4_SCLK_PP6,
+};
+
+static const unsigned int dap4_dout_pp7_pins[] = {
+ TEGRA_PIN_DAP4_DOUT_PP7,
+};
+
+static const unsigned int dap4_din_pq0_pins[] = {
+ TEGRA_PIN_DAP4_DIN_PQ0,
+};
+
+static const unsigned int dap4_fs_pq1_pins[] = {
+ TEGRA_PIN_DAP4_FS_PQ1,
+};
+
+static const unsigned int spi5_sck_pq2_pins[] = {
+ TEGRA_PIN_SPI5_SCK_PQ2,
+};
+
+static const unsigned int spi5_miso_pq3_pins[] = {
+ TEGRA_PIN_SPI5_MISO_PQ3,
+};
+
+static const unsigned int spi5_mosi_pq4_pins[] = {
+ TEGRA_PIN_SPI5_MOSI_PQ4,
+};
+
+static const unsigned int spi5_cs0_pq5_pins[] = {
+ TEGRA_PIN_SPI5_CS0_PQ5,
+};
+
+static const unsigned int soc_gpio152_pq6_pins[] = {
+ TEGRA_PIN_SOC_GPIO152_PQ6,
+};
+
+static const unsigned int soc_gpio153_pq7_pins[] = {
+ TEGRA_PIN_SOC_GPIO153_PQ7,
+};
+
+static const unsigned int aud_mclk_pr0_pins[] = {
+ TEGRA_PIN_AUD_MCLK_PR0,
+};
+
+static const unsigned int soc_gpio155_pr1_pins[] = {
+ TEGRA_PIN_SOC_GPIO155_PR1,
+};
+
+static const unsigned int dap1_sclk_pr2_pins[] = {
+ TEGRA_PIN_DAP1_SCLK_PR2,
+};
+
+static const unsigned int dap1_out_pr3_pins[] = {
+ TEGRA_PIN_DAP1_OUT_PR3,
+};
+
+static const unsigned int dap1_in_pr4_pins[] = {
+ TEGRA_PIN_DAP1_IN_PR4,
+};
+
+static const unsigned int dap1_fs_pr5_pins[] = {
+ TEGRA_PIN_DAP1_FS_PR5,
+};
+
+static const unsigned int gen11_i2c_scl_pr6_pins[] = {
+ TEGRA_PIN_GEN11_I2C_SCL_PR6,
+};
+
+static const unsigned int gen11_i2c_sda_pr7_pins[] = {
+ TEGRA_PIN_GEN11_I2C_SDA_PR7,
+};
+
+static const unsigned int soc_gpio350_ps0_pins[] = {
+ TEGRA_PIN_SOC_GPIO350_PS0,
+};
+
+static const unsigned int soc_gpio351_ps1_pins[] = {
+ TEGRA_PIN_SOC_GPIO351_PS1,
+};
+
+static const unsigned int soc_gpio270_py0_pins[] = {
+ TEGRA_PIN_SOC_GPIO270_PY0,
+};
+
+static const unsigned int soc_gpio271_py1_pins[] = {
+ TEGRA_PIN_SOC_GPIO271_PY1,
+};
+
+static const unsigned int soc_gpio272_py2_pins[] = {
+ TEGRA_PIN_SOC_GPIO272_PY2,
+};
+
+static const unsigned int soc_gpio273_py3_pins[] = {
+ TEGRA_PIN_SOC_GPIO273_PY3,
+};
+
+static const unsigned int soc_gpio274_py4_pins[] = {
+ TEGRA_PIN_SOC_GPIO274_PY4,
+};
+
+static const unsigned int soc_gpio275_py5_pins[] = {
+ TEGRA_PIN_SOC_GPIO275_PY5,
+};
+
+static const unsigned int soc_gpio276_py6_pins[] = {
+ TEGRA_PIN_SOC_GPIO276_PY6,
+};
+
+static const unsigned int soc_gpio277_py7_pins[] = {
+ TEGRA_PIN_SOC_GPIO277_PY7,
+};
+
+static const unsigned int soc_gpio278_pz0_pins[] = {
+ TEGRA_PIN_SOC_GPIO278_PZ0,
+};
+
+static const unsigned int soc_gpio279_pz1_pins[] = {
+ TEGRA_PIN_SOC_GPIO279_PZ1,
+};
+
+static const unsigned int xhalt_trig_pz2_pins[] = {
+ TEGRA_PIN_XHALT_TRIG_PZ2,
+};
+
+static const unsigned int soc_gpio281_pz3_pins[] = {
+ TEGRA_PIN_SOC_GPIO281_PZ3,
+};
+
+static const unsigned int soc_gpio282_pz4_pins[] = {
+ TEGRA_PIN_SOC_GPIO282_PZ4,
+};
+
+static const unsigned int soc_gpio283_pz5_pins[] = {
+ TEGRA_PIN_SOC_GPIO283_PZ5,
+};
+
+static const unsigned int soc_gpio284_pz6_pins[] = {
+ TEGRA_PIN_SOC_GPIO284_PZ6,
+};
+
+static const unsigned int soc_gpio285_pz7_pins[] = {
+ TEGRA_PIN_SOC_GPIO285_PZ7,
+};
+
+static const unsigned int soc_gpio286_pal0_pins[] = {
+ TEGRA_PIN_SOC_GPIO286_PAL0,
+};
+
+static const unsigned int soc_gpio287_pal1_pins[] = {
+ TEGRA_PIN_SOC_GPIO287_PAL1,
+};
+
+static const unsigned int soc_gpio288_pal2_pins[] = {
+ TEGRA_PIN_SOC_GPIO288_PAL2,
+};
+
+static const unsigned int soc_gpio00_paa0_pins[] = {
+ TEGRA_PIN_SOC_GPIO00_PAA0,
+};
+
+static const unsigned int vcomp_alert_paa1_pins[] = {
+ TEGRA_PIN_VCOMP_ALERT_PAA1,
+};
+
+static const unsigned int ao_retention_n_paa2_pins[] = {
+ TEGRA_PIN_AO_RETENTION_N_PAA2,
+};
+
+static const unsigned int batt_oc_paa3_pins[] = {
+ TEGRA_PIN_BATT_OC_PAA3,
+};
+
+static const unsigned int bootv_ctl_n_paa4_pins[] = {
+ TEGRA_PIN_BOOTV_CTL_N_PAA4,
+};
+
+static const unsigned int power_on_paa5_pins[] = {
+ TEGRA_PIN_POWER_ON_PAA5,
+};
+
+static const unsigned int hdmi_cec_paa6_pins[] = {
+ TEGRA_PIN_HDMI_CEC_PAA6,
+};
+
+static const unsigned int soc_gpio07_paa7_pins[] = {
+ TEGRA_PIN_SOC_GPIO07_PAA7,
+};
+
+static const unsigned int soc_gpio08_pbb0_pins[] = {
+ TEGRA_PIN_SOC_GPIO08_PBB0,
+};
+
+static const unsigned int soc_gpio09_pbb1_pins[] = {
+ TEGRA_PIN_SOC_GPIO09_PBB1,
+};
+
+static const unsigned int gen2_i2c_scl_pcc0_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SCL_PCC0,
+};
+
+static const unsigned int gen2_i2c_sda_pcc1_pins[] = {
+ TEGRA_PIN_GEN2_I2C_SDA_PCC1,
+};
+
+static const unsigned int gen3_i2c_scl_pcc2_pins[] = {
+ TEGRA_PIN_GEN3_I2C_SCL_PCC2,
+};
+
+static const unsigned int gen3_i2c_sda_pcc3_pins[] = {
+ TEGRA_PIN_GEN3_I2C_SDA_PCC3,
+};
+
+static const unsigned int gp_pwm4_pcc4_pins[] = {
+ TEGRA_PIN_GP_PWM4_PCC4,
+};
+
+static const unsigned int uart0_tx_pcc5_pins[] = {
+ TEGRA_PIN_UART0_TX_PCC5,
+};
+
+static const unsigned int uart0_rx_pcc6_pins[] = {
+ TEGRA_PIN_UART0_RX_PCC6,
+};
+
+static const unsigned int spi2_sck_pcc7_pins[] = {
+ TEGRA_PIN_SPI2_SCK_PCC7,
+};
+
+static const unsigned int spi2_miso_pdd0_pins[] = {
+ TEGRA_PIN_SPI2_MISO_PDD0,
+};
+
+static const unsigned int spi2_mosi_pdd1_pins[] = {
+ TEGRA_PIN_SPI2_MOSI_PDD1,
+};
+
+static const unsigned int spi2_cs0_n_pdd2_pins[] = {
+ TEGRA_PIN_SPI2_CS0_N_PDD2,
+};
+
+static const unsigned int soc_gpio21_pdd3_pins[] = {
+ TEGRA_PIN_SOC_GPIO21_PDD3,
+};
+
+static const unsigned int soc_gpio22_pdd4_pins[] = {
+ TEGRA_PIN_SOC_GPIO22_PDD4,
+};
+
+static const unsigned int soc_gpio23_pdd5_pins[] = {
+ TEGRA_PIN_SOC_GPIO23_PDD5,
+};
+
+static const unsigned int soc_gpio24_pdd6_pins[] = {
+ TEGRA_PIN_SOC_GPIO24_PDD6,
+};
+
+static const unsigned int soc_gpio25_pdd7_pins[] = {
+ TEGRA_PIN_SOC_GPIO25_PDD7,
+};
+
+static const unsigned int soc_gpio26_pee0_pins[] = {
+ TEGRA_PIN_SOC_GPIO26_PEE0,
+};
+
+static const unsigned int soc_gpio27_pee1_pins[] = {
+ TEGRA_PIN_SOC_GPIO27_PEE1,
+};
+
+static const unsigned int soc_gpio28_pee2_pins[] = {
+ TEGRA_PIN_SOC_GPIO28_PEE2,
+};
+
+static const unsigned int soc_gpio29_pee3_pins[] = {
+ TEGRA_PIN_SOC_GPIO29_PEE3,
+};
+
+enum tegra_mux_dt {
+ TEGRA_MUX_DCA_VSYNC,
+ TEGRA_MUX_DCA_HSYNC,
+ TEGRA_MUX_RSVD0,
+ TEGRA_MUX_DP_AUX_CH0_HPD,
+ TEGRA_MUX_DP_AUX_CH1_HPD,
+ TEGRA_MUX_DP_AUX_CH2_HPD,
+ TEGRA_MUX_DP_AUX_CH3_HPD,
+ TEGRA_MUX_GP_PWM2,
+ TEGRA_MUX_GP_PWM3,
+ TEGRA_MUX_I2C7_CLK,
+ TEGRA_MUX_I2C7_DAT,
+ TEGRA_MUX_I2C9_CLK,
+ TEGRA_MUX_I2C9_DAT,
+ TEGRA_MUX_UARTK_CTS,
+ TEGRA_MUX_UARTK_RTS,
+ TEGRA_MUX_UARTK_RXD,
+ TEGRA_MUX_UARTK_TXD,
+ TEGRA_MUX_SPI3_CS0,
+ TEGRA_MUX_SPI3_CS3,
+ TEGRA_MUX_SPI3_DIN,
+ TEGRA_MUX_SPI3_DOUT,
+ TEGRA_MUX_SPI3_SCK,
+ TEGRA_MUX_UARTF_CTS,
+ TEGRA_MUX_UARTF_RTS,
+ TEGRA_MUX_UARTF_RXD,
+ TEGRA_MUX_UARTF_TXD,
+ TEGRA_MUX_SPI1_CS0,
+ TEGRA_MUX_SPI1_CS1,
+ TEGRA_MUX_SPI1_DIN,
+ TEGRA_MUX_SPI1_DOUT,
+ TEGRA_MUX_SPI1_SCK,
+ TEGRA_MUX_EXTPERIPH2_CLK,
+ TEGRA_MUX_EXTPERIPH1_CLK,
+ TEGRA_MUX_I2C12_CLK,
+ TEGRA_MUX_I2C12_DAT,
+ TEGRA_MUX_NV_THERM_FAN_TACH0,
+ TEGRA_MUX_GP_PWM9,
+ TEGRA_MUX_UARTJ_CTS,
+ TEGRA_MUX_UARTJ_RTS,
+ TEGRA_MUX_UARTJ_RXD,
+ TEGRA_MUX_UARTJ_TXD,
+ TEGRA_MUX_I2C0_CLK,
+ TEGRA_MUX_I2C0_DAT,
+ TEGRA_MUX_I2C1_CLK,
+ TEGRA_MUX_I2C1_DAT,
+ TEGRA_MUX_I2S2_LRCK,
+ TEGRA_MUX_I2S2_SCLK,
+ TEGRA_MUX_I2S2_SDATA_OUT,
+ TEGRA_MUX_I2S2_SDATA_IN,
+ TEGRA_MUX_GP_PWM10,
+ TEGRA_MUX_UARTE_CTS,
+ TEGRA_MUX_UARTE_RTS,
+ TEGRA_MUX_UARTE_RXD,
+ TEGRA_MUX_UARTE_TXD,
+ TEGRA_MUX_I2C5_DAT,
+ TEGRA_MUX_I2C5_CLK,
+ TEGRA_MUX_I2S6_SDATA_IN,
+ TEGRA_MUX_I2S6_SDATA_OUT,
+ TEGRA_MUX_I2S6_LRCK,
+ TEGRA_MUX_I2S6_SCLK,
+ TEGRA_MUX_I2S4_SDATA_OUT,
+ TEGRA_MUX_I2S4_SCLK,
+ TEGRA_MUX_I2S4_SDATA_IN,
+ TEGRA_MUX_I2S4_LRCK,
+ TEGRA_MUX_SPI5_CS0,
+ TEGRA_MUX_SPI5_DIN,
+ TEGRA_MUX_SPI5_DOUT,
+ TEGRA_MUX_SPI5_SCK,
+ TEGRA_MUX_AUD_MCLK,
+ TEGRA_MUX_I2S1_SCLK,
+ TEGRA_MUX_I2S1_SDATA_IN,
+ TEGRA_MUX_I2S1_SDATA_OUT,
+ TEGRA_MUX_I2S1_LRCK,
+ TEGRA_MUX_I2C11_CLK,
+ TEGRA_MUX_I2C11_DAT,
+ TEGRA_MUX_XHALT_TRIG,
+ TEGRA_MUX_GP_PWM1,
+ TEGRA_MUX_GP_PWM6,
+ TEGRA_MUX_GP_PWM7,
+ TEGRA_MUX_GP_PWM8,
+ TEGRA_MUX_UFS0,
+ TEGRA_MUX_PE1_CLKREQ_L,
+ TEGRA_MUX_PE1_RST_L,
+ TEGRA_MUX_PE2_RST_L,
+ TEGRA_MUX_PE2_CLKREQ_L,
+ TEGRA_MUX_PE3_CLKREQ_L,
+ TEGRA_MUX_PE3_RST_L,
+ TEGRA_MUX_SGMII0_SMA_MDIO,
+ TEGRA_MUX_SGMII0_SMA_MDC,
+ TEGRA_MUX_USB_VBUS_EN0,
+ TEGRA_MUX_USB_VBUS_EN1,
+ TEGRA_MUX_ETH1_MDIO,
+ TEGRA_MUX_PE4_CLKREQ_L,
+ TEGRA_MUX_PE4_RST_L,
+ TEGRA_MUX_PE5_CLKREQ_L,
+ TEGRA_MUX_PE5_RST_L,
+ TEGRA_MUX_ETH0_MDIO,
+ TEGRA_MUX_ETH0_MDC,
+ TEGRA_MUX_ETH1_MDC,
+ TEGRA_MUX_ETH2_MDIO,
+ TEGRA_MUX_ETH2_MDC,
+ TEGRA_MUX_ETH3_MDIO,
+ TEGRA_MUX_ETH3_MDC,
+ TEGRA_MUX_QSPI0_CS_N,
+ TEGRA_MUX_QSPI0_IO0,
+ TEGRA_MUX_QSPI0_IO1,
+ TEGRA_MUX_QSPI0_IO2,
+ TEGRA_MUX_QSPI0_IO3,
+ TEGRA_MUX_QSPI0_SCK,
+ TEGRA_MUX_SDMMC1_CLK,
+ TEGRA_MUX_SDMMC1_CMD,
+ TEGRA_MUX_SDMMC1_COMP,
+ TEGRA_MUX_SDMMC1_DAT3,
+ TEGRA_MUX_SDMMC1_DAT2,
+ TEGRA_MUX_SDMMC1_DAT1,
+ TEGRA_MUX_SDMMC1_DAT0,
+ TEGRA_MUX_QSPI3_SCK,
+ TEGRA_MUX_QSPI3_CS0,
+ TEGRA_MUX_QSPI3_IO0,
+ TEGRA_MUX_QSPI3_IO1,
+ TEGRA_MUX_DCB_VSYNC,
+ TEGRA_MUX_DCB_HSYNC,
+ TEGRA_MUX_DSA_LSPII,
+ TEGRA_MUX_DCE_VSYNC,
+ TEGRA_MUX_DCE_HSYNC,
+ TEGRA_MUX_DCH_VSYNC,
+ TEGRA_MUX_DCH_HSYNC,
+ TEGRA_MUX_BL_EN,
+ TEGRA_MUX_BL_PWM_DIM0,
+ TEGRA_MUX_RSVD1,
+ TEGRA_MUX_SOC_THERM_OC3,
+ TEGRA_MUX_I2S5_SCLK,
+ TEGRA_MUX_I2S5_SDATA_IN,
+ TEGRA_MUX_EXTPERIPH3_CLK,
+ TEGRA_MUX_EXTPERIPH4_CLK,
+ TEGRA_MUX_I2S5_SDATA_OUT,
+ TEGRA_MUX_I2S5_LRCK,
+ TEGRA_MUX_SDMMC1_CD,
+ TEGRA_MUX_I2S7_SDATA_IN,
+ TEGRA_MUX_SPI4_SCK,
+ TEGRA_MUX_SPI4_DIN,
+ TEGRA_MUX_SPI4_DOUT,
+ TEGRA_MUX_SPI4_CS0,
+ TEGRA_MUX_SPI4_CS1,
+ TEGRA_MUX_GP_PWM5,
+ TEGRA_MUX_I2C14_CLK,
+ TEGRA_MUX_I2C14_DAT,
+ TEGRA_MUX_I2S8_SCLK,
+ TEGRA_MUX_I2S8_SDATA_OUT,
+ TEGRA_MUX_I2S8_LRCK,
+ TEGRA_MUX_I2S8_SDATA_IN,
+ TEGRA_MUX_I2C16_CLK,
+ TEGRA_MUX_I2C16_DAT,
+ TEGRA_MUX_I2S3_SCLK,
+ TEGRA_MUX_I2S3_SDATA_OUT,
+ TEGRA_MUX_I2S3_SDATA_IN,
+ TEGRA_MUX_I2S3_LRCK,
+ TEGRA_MUX_PM_TRIG1,
+ TEGRA_MUX_PM_TRIG0,
+ TEGRA_MUX_QSPI2_SCK,
+ TEGRA_MUX_QSPI2_CS0,
+ TEGRA_MUX_QSPI2_IO0,
+ TEGRA_MUX_QSPI2_IO1,
+ TEGRA_MUX_DCC_VSYNC,
+ TEGRA_MUX_DCC_HSYNC,
+ TEGRA_MUX_RSVD2,
+ TEGRA_MUX_DCF_VSYNC,
+ TEGRA_MUX_DCF_HSYNC,
+ TEGRA_MUX_SOUNDWIRE1_CLK,
+ TEGRA_MUX_SOUNDWIRE1_DAT0,
+ TEGRA_MUX_SOUNDWIRE1_DAT1,
+ TEGRA_MUX_SOUNDWIRE1_DAT2,
+ TEGRA_MUX_DMIC2_CLK,
+ TEGRA_MUX_DMIC2_DAT,
+ TEGRA_MUX_NV_THERM_FAN_TACH1,
+ TEGRA_MUX_I2C15_CLK,
+ TEGRA_MUX_I2C15_DAT,
+ TEGRA_MUX_I2S7_LRCK,
+ TEGRA_MUX_CCLA_LA_TRIGGER_MUX,
+ TEGRA_MUX_I2S7_SCLK,
+ TEGRA_MUX_I2S7_SDATA_OUT,
+ TEGRA_MUX_DMIC1_DAT,
+ TEGRA_MUX_DMIC1_CLK,
+ TEGRA_MUX_DCD_VSYNC,
+ TEGRA_MUX_DCD_HSYNC,
+ TEGRA_MUX_RSVD3,
+ TEGRA_MUX_DCG_VSYNC,
+ TEGRA_MUX_DCG_HSYNC,
+ TEGRA_MUX_DSPK1_CLK,
+ TEGRA_MUX_DSPK1_DAT,
+ TEGRA_MUX_SOC_THERM_OC2,
+ TEGRA_MUX_ISTCTRL_IST_DONE_N,
+ TEGRA_MUX_SOC_THERM_OC1,
+ TEGRA_MUX_TSC_EDGE_OUT0C,
+ TEGRA_MUX_TSC_EDGE_OUT0D,
+ TEGRA_MUX_TSC_EDGE_OUT0A,
+ TEGRA_MUX_TSC_EDGE_OUT0B,
+ TEGRA_MUX_TOUCH_CLK,
+ TEGRA_MUX_HDMI_CEC,
+ TEGRA_MUX_I2C2_CLK,
+ TEGRA_MUX_I2C2_DAT,
+ TEGRA_MUX_I2C3_CLK,
+ TEGRA_MUX_I2C3_DAT,
+ TEGRA_MUX_GP_PWM4,
+ TEGRA_MUX_UARTA_TXD,
+ TEGRA_MUX_UARTA_RXD,
+ TEGRA_MUX_SPI2_SCK,
+ TEGRA_MUX_SPI2_DIN,
+ TEGRA_MUX_SPI2_DOUT,
+ TEGRA_MUX_SPI2_CS0,
+ TEGRA_MUX_TSC_SYNC1,
+ TEGRA_MUX_TSC_EDGE_OUT3,
+ TEGRA_MUX_TSC_EDGE_OUT0,
+ TEGRA_MUX_TSC_EDGE_OUT1,
+ TEGRA_MUX_TSC_SYNC0,
+ TEGRA_MUX_SOUNDWIRE0_CLK,
+ TEGRA_MUX_SOUNDWIRE0_DAT0,
+ TEGRA_MUX_L0L1_RST_OUT_N,
+ TEGRA_MUX_L2_RST_OUT_N,
+ TEGRA_MUX_UARTL_TXD,
+ TEGRA_MUX_UARTL_RXD,
+ TEGRA_MUX_I2S9_SCLK,
+ TEGRA_MUX_I2S9_SDATA_OUT,
+ TEGRA_MUX_I2S9_SDATA_IN,
+ TEGRA_MUX_I2S9_LRCK,
+ TEGRA_MUX_DMIC5_DAT,
+ TEGRA_MUX_DMIC5_CLK,
+ TEGRA_MUX_TSC_EDGE_OUT2,
+};
+
+/* Make list of each function name */
+#define TEGRA_PIN_FUNCTION(lid) #lid
+
+static const char * const tegra264_functions[] = {
+ TEGRA_PIN_FUNCTION(dca_vsync),
+ TEGRA_PIN_FUNCTION(dca_hsync),
+ TEGRA_PIN_FUNCTION(rsvd0),
+ TEGRA_PIN_FUNCTION(dp_aux_ch0_hpd),
+ TEGRA_PIN_FUNCTION(dp_aux_ch1_hpd),
+ TEGRA_PIN_FUNCTION(dp_aux_ch2_hpd),
+ TEGRA_PIN_FUNCTION(dp_aux_ch3_hpd),
+ TEGRA_PIN_FUNCTION(gp_pwm2),
+ TEGRA_PIN_FUNCTION(gp_pwm3),
+ TEGRA_PIN_FUNCTION(i2c7_clk),
+ TEGRA_PIN_FUNCTION(i2c7_dat),
+ TEGRA_PIN_FUNCTION(i2c9_clk),
+ TEGRA_PIN_FUNCTION(i2c9_dat),
+ TEGRA_PIN_FUNCTION(uartk_cts),
+ TEGRA_PIN_FUNCTION(uartk_rts),
+ TEGRA_PIN_FUNCTION(uartk_rxd),
+ TEGRA_PIN_FUNCTION(uartk_txd),
+ TEGRA_PIN_FUNCTION(spi3_cs0),
+ TEGRA_PIN_FUNCTION(spi3_cs3),
+ TEGRA_PIN_FUNCTION(spi3_din),
+ TEGRA_PIN_FUNCTION(spi3_dout),
+ TEGRA_PIN_FUNCTION(spi3_sck),
+ TEGRA_PIN_FUNCTION(uartf_cts),
+ TEGRA_PIN_FUNCTION(uartf_rts),
+ TEGRA_PIN_FUNCTION(uartf_rxd),
+ TEGRA_PIN_FUNCTION(uartf_txd),
+ TEGRA_PIN_FUNCTION(spi1_cs0),
+ TEGRA_PIN_FUNCTION(spi1_cs1),
+ TEGRA_PIN_FUNCTION(spi1_din),
+ TEGRA_PIN_FUNCTION(spi1_dout),
+ TEGRA_PIN_FUNCTION(spi1_sck),
+ TEGRA_PIN_FUNCTION(extperiph2_clk),
+ TEGRA_PIN_FUNCTION(extperiph1_clk),
+ TEGRA_PIN_FUNCTION(i2c12_clk),
+ TEGRA_PIN_FUNCTION(i2c12_dat),
+ TEGRA_PIN_FUNCTION(nv_therm_fan_tach0),
+ TEGRA_PIN_FUNCTION(gp_pwm9),
+ TEGRA_PIN_FUNCTION(uartj_cts),
+ TEGRA_PIN_FUNCTION(uartj_rts),
+ TEGRA_PIN_FUNCTION(uartj_rxd),
+ TEGRA_PIN_FUNCTION(uartj_txd),
+ TEGRA_PIN_FUNCTION(i2c0_clk),
+ TEGRA_PIN_FUNCTION(i2c0_dat),
+ TEGRA_PIN_FUNCTION(i2c1_clk),
+ TEGRA_PIN_FUNCTION(i2c1_dat),
+ TEGRA_PIN_FUNCTION(i2s2_lrck),
+ TEGRA_PIN_FUNCTION(i2s2_sclk),
+ TEGRA_PIN_FUNCTION(i2s2_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s2_sdata_in),
+ TEGRA_PIN_FUNCTION(gp_pwm10),
+ TEGRA_PIN_FUNCTION(uarte_cts),
+ TEGRA_PIN_FUNCTION(uarte_rts),
+ TEGRA_PIN_FUNCTION(uarte_rxd),
+ TEGRA_PIN_FUNCTION(uarte_txd),
+ TEGRA_PIN_FUNCTION(i2c5_dat),
+ TEGRA_PIN_FUNCTION(i2c5_clk),
+ TEGRA_PIN_FUNCTION(i2s6_sdata_in),
+ TEGRA_PIN_FUNCTION(i2s6_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s6_lrck),
+ TEGRA_PIN_FUNCTION(i2s6_sclk),
+ TEGRA_PIN_FUNCTION(i2s4_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s4_sclk),
+ TEGRA_PIN_FUNCTION(i2s4_sdata_in),
+ TEGRA_PIN_FUNCTION(i2s4_lrck),
+ TEGRA_PIN_FUNCTION(spi5_cs0),
+ TEGRA_PIN_FUNCTION(spi5_din),
+ TEGRA_PIN_FUNCTION(spi5_dout),
+ TEGRA_PIN_FUNCTION(spi5_sck),
+ TEGRA_PIN_FUNCTION(aud_mclk),
+ TEGRA_PIN_FUNCTION(i2s1_sclk),
+ TEGRA_PIN_FUNCTION(i2s1_sdata_in),
+ TEGRA_PIN_FUNCTION(i2s1_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s1_lrck),
+ TEGRA_PIN_FUNCTION(i2c11_clk),
+ TEGRA_PIN_FUNCTION(i2c11_dat),
+ TEGRA_PIN_FUNCTION(xhalt_trig),
+ TEGRA_PIN_FUNCTION(gp_pwm1),
+ TEGRA_PIN_FUNCTION(gp_pwm6),
+ TEGRA_PIN_FUNCTION(gp_pwm7),
+ TEGRA_PIN_FUNCTION(gp_pwm8),
+ TEGRA_PIN_FUNCTION(ufs0),
+ TEGRA_PIN_FUNCTION(pe1_clkreq_l),
+ TEGRA_PIN_FUNCTION(pe1_rst_l),
+ TEGRA_PIN_FUNCTION(pe2_rst_l),
+ TEGRA_PIN_FUNCTION(pe2_clkreq_l),
+ TEGRA_PIN_FUNCTION(pe3_clkreq_l),
+ TEGRA_PIN_FUNCTION(pe3_rst_l),
+ TEGRA_PIN_FUNCTION(sgmii0_sma_mdio),
+ TEGRA_PIN_FUNCTION(sgmii0_sma_mdc),
+ TEGRA_PIN_FUNCTION(usb_vbus_en0),
+ TEGRA_PIN_FUNCTION(usb_vbus_en1),
+ TEGRA_PIN_FUNCTION(eth1_mdio),
+ TEGRA_PIN_FUNCTION(pe4_clkreq_l),
+ TEGRA_PIN_FUNCTION(pe4_rst_l),
+ TEGRA_PIN_FUNCTION(pe5_clkreq_l),
+ TEGRA_PIN_FUNCTION(pe5_rst_l),
+ TEGRA_PIN_FUNCTION(eth0_mdio),
+ TEGRA_PIN_FUNCTION(eth0_mdc),
+ TEGRA_PIN_FUNCTION(eth1_mdc),
+ TEGRA_PIN_FUNCTION(eth2_mdio),
+ TEGRA_PIN_FUNCTION(eth2_mdc),
+ TEGRA_PIN_FUNCTION(eth3_mdio),
+ TEGRA_PIN_FUNCTION(eth3_mdc),
+ TEGRA_PIN_FUNCTION(qspi0_cs_n),
+ TEGRA_PIN_FUNCTION(qspi0_io0),
+ TEGRA_PIN_FUNCTION(qspi0_io1),
+ TEGRA_PIN_FUNCTION(qspi0_io2),
+ TEGRA_PIN_FUNCTION(qspi0_io3),
+ TEGRA_PIN_FUNCTION(qspi0_sck),
+ TEGRA_PIN_FUNCTION(sdmmc1_clk),
+ TEGRA_PIN_FUNCTION(sdmmc1_cmd),
+ TEGRA_PIN_FUNCTION(sdmmc1_comp),
+ TEGRA_PIN_FUNCTION(sdmmc1_dat3),
+ TEGRA_PIN_FUNCTION(sdmmc1_dat2),
+ TEGRA_PIN_FUNCTION(sdmmc1_dat1),
+ TEGRA_PIN_FUNCTION(sdmmc1_dat0),
+ TEGRA_PIN_FUNCTION(qspi3_sck),
+ TEGRA_PIN_FUNCTION(qspi3_cs0),
+ TEGRA_PIN_FUNCTION(qspi3_io0),
+ TEGRA_PIN_FUNCTION(qspi3_io1),
+ TEGRA_PIN_FUNCTION(dcb_vsync),
+ TEGRA_PIN_FUNCTION(dcb_hsync),
+ TEGRA_PIN_FUNCTION(dsa_lspii),
+ TEGRA_PIN_FUNCTION(dce_vsync),
+ TEGRA_PIN_FUNCTION(dce_hsync),
+ TEGRA_PIN_FUNCTION(dch_vsync),
+ TEGRA_PIN_FUNCTION(dch_hsync),
+ TEGRA_PIN_FUNCTION(bl_en),
+ TEGRA_PIN_FUNCTION(bl_pwm_dim0),
+ TEGRA_PIN_FUNCTION(rsvd1),
+ TEGRA_PIN_FUNCTION(soc_therm_oc3),
+ TEGRA_PIN_FUNCTION(i2s5_sclk),
+ TEGRA_PIN_FUNCTION(i2s5_sdata_in),
+ TEGRA_PIN_FUNCTION(extperiph3_clk),
+ TEGRA_PIN_FUNCTION(extperiph4_clk),
+ TEGRA_PIN_FUNCTION(i2s5_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s5_lrck),
+ TEGRA_PIN_FUNCTION(sdmmc1_cd),
+ TEGRA_PIN_FUNCTION(i2s7_sdata_in),
+ TEGRA_PIN_FUNCTION(spi4_sck),
+ TEGRA_PIN_FUNCTION(spi4_din),
+ TEGRA_PIN_FUNCTION(spi4_dout),
+ TEGRA_PIN_FUNCTION(spi4_cs0),
+ TEGRA_PIN_FUNCTION(spi4_cs1),
+ TEGRA_PIN_FUNCTION(gp_pwm5),
+ TEGRA_PIN_FUNCTION(i2c14_clk),
+ TEGRA_PIN_FUNCTION(i2c14_dat),
+ TEGRA_PIN_FUNCTION(i2s8_sclk),
+ TEGRA_PIN_FUNCTION(i2s8_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s8_lrck),
+ TEGRA_PIN_FUNCTION(i2s8_sdata_in),
+ TEGRA_PIN_FUNCTION(i2c16_clk),
+ TEGRA_PIN_FUNCTION(i2c16_dat),
+ TEGRA_PIN_FUNCTION(i2s3_sclk),
+ TEGRA_PIN_FUNCTION(i2s3_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s3_sdata_in),
+ TEGRA_PIN_FUNCTION(i2s3_lrck),
+ TEGRA_PIN_FUNCTION(pm_trig1),
+ TEGRA_PIN_FUNCTION(pm_trig0),
+ TEGRA_PIN_FUNCTION(qspi2_sck),
+ TEGRA_PIN_FUNCTION(qspi2_cs0),
+ TEGRA_PIN_FUNCTION(qspi2_io0),
+ TEGRA_PIN_FUNCTION(qspi2_io1),
+ TEGRA_PIN_FUNCTION(dcc_vsync),
+ TEGRA_PIN_FUNCTION(dcc_hsync),
+ TEGRA_PIN_FUNCTION(rsvd2),
+ TEGRA_PIN_FUNCTION(dcf_vsync),
+ TEGRA_PIN_FUNCTION(dcf_hsync),
+ TEGRA_PIN_FUNCTION(soundwire1_clk),
+ TEGRA_PIN_FUNCTION(soundwire1_dat0),
+ TEGRA_PIN_FUNCTION(soundwire1_dat1),
+ TEGRA_PIN_FUNCTION(soundwire1_dat2),
+ TEGRA_PIN_FUNCTION(dmic2_clk),
+ TEGRA_PIN_FUNCTION(dmic2_dat),
+ TEGRA_PIN_FUNCTION(nv_therm_fan_tach1),
+ TEGRA_PIN_FUNCTION(i2c15_clk),
+ TEGRA_PIN_FUNCTION(i2c15_dat),
+ TEGRA_PIN_FUNCTION(i2s7_lrck),
+ TEGRA_PIN_FUNCTION(ccla_la_trigger_mux),
+ TEGRA_PIN_FUNCTION(i2s7_sclk),
+ TEGRA_PIN_FUNCTION(i2s7_sdata_out),
+ TEGRA_PIN_FUNCTION(dmic1_dat),
+ TEGRA_PIN_FUNCTION(dmic1_clk),
+ TEGRA_PIN_FUNCTION(dcd_vsync),
+ TEGRA_PIN_FUNCTION(dcd_hsync),
+ TEGRA_PIN_FUNCTION(rsvd3),
+ TEGRA_PIN_FUNCTION(dcg_vsync),
+ TEGRA_PIN_FUNCTION(dcg_hsync),
+ TEGRA_PIN_FUNCTION(dspk1_clk),
+ TEGRA_PIN_FUNCTION(dspk1_dat),
+ TEGRA_PIN_FUNCTION(soc_therm_oc2),
+ TEGRA_PIN_FUNCTION(istctrl_ist_done_n),
+ TEGRA_PIN_FUNCTION(soc_therm_oc1),
+ TEGRA_PIN_FUNCTION(tsc_edge_out0c),
+ TEGRA_PIN_FUNCTION(tsc_edge_out0d),
+ TEGRA_PIN_FUNCTION(tsc_edge_out0a),
+ TEGRA_PIN_FUNCTION(tsc_edge_out0b),
+ TEGRA_PIN_FUNCTION(touch_clk),
+ TEGRA_PIN_FUNCTION(hdmi_cec),
+ TEGRA_PIN_FUNCTION(i2c2_clk),
+ TEGRA_PIN_FUNCTION(i2c2_dat),
+ TEGRA_PIN_FUNCTION(i2c3_clk),
+ TEGRA_PIN_FUNCTION(i2c3_dat),
+ TEGRA_PIN_FUNCTION(gp_pwm4),
+ TEGRA_PIN_FUNCTION(uarta_txd),
+ TEGRA_PIN_FUNCTION(uarta_rxd),
+ TEGRA_PIN_FUNCTION(spi2_sck),
+ TEGRA_PIN_FUNCTION(spi2_din),
+ TEGRA_PIN_FUNCTION(spi2_dout),
+ TEGRA_PIN_FUNCTION(spi2_cs0),
+ TEGRA_PIN_FUNCTION(tsc_sync1),
+ TEGRA_PIN_FUNCTION(tsc_edge_out3),
+ TEGRA_PIN_FUNCTION(tsc_edge_out0),
+ TEGRA_PIN_FUNCTION(tsc_edge_out1),
+ TEGRA_PIN_FUNCTION(tsc_sync0),
+ TEGRA_PIN_FUNCTION(soundwire0_clk),
+ TEGRA_PIN_FUNCTION(soundwire0_dat0),
+ TEGRA_PIN_FUNCTION(l0l1_rst_out_n),
+ TEGRA_PIN_FUNCTION(l2_rst_out_n),
+ TEGRA_PIN_FUNCTION(uartl_txd),
+ TEGRA_PIN_FUNCTION(uartl_rxd),
+ TEGRA_PIN_FUNCTION(i2s9_sclk),
+ TEGRA_PIN_FUNCTION(i2s9_sdata_out),
+ TEGRA_PIN_FUNCTION(i2s9_sdata_in),
+ TEGRA_PIN_FUNCTION(i2s9_lrck),
+ TEGRA_PIN_FUNCTION(dmic5_dat),
+ TEGRA_PIN_FUNCTION(dmic5_clk),
+ TEGRA_PIN_FUNCTION(tsc_edge_out2),
+};
+
+#define PINGROUP_REG_Y(r) ((r))
+#define PINGROUP_REG_N(r) -1
+
+#define DRV_PINGROUP_Y(r) ((r))
+
+#define DRV_PINGROUP_ENTRY_N \
+ .drv_reg = -1, \
+ .drv_bank = -1, \
+ .drvdn_bit = -1, \
+ .drvup_bit = -1, \
+ .slwr_bit = -1, \
+ .slwf_bit = -1
+
+#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
+ drvup_w, slwr_b, slwr_w, slwf_b, \
+ slwf_w, bank) \
+ .drv_reg = DRV_PINGROUP_Y(r), \
+ .drv_bank = bank, \
+ .drvdn_bit = drvdn_b, \
+ .drvdn_width = drvdn_w, \
+ .drvup_bit = drvup_b, \
+ .drvup_width = drvup_w, \
+ .slwr_bit = slwr_b, \
+ .slwr_width = slwr_w, \
+ .slwf_bit = slwf_b, \
+ .slwf_width = slwf_w
+
+#define PIN_PINGROUP_ENTRY_N \
+ .mux_reg = -1, \
+ .pupd_reg = -1, \
+ .tri_reg = -1, \
+ .einput_bit = -1, \
+ .e_io_hv_bit = -1, \
+ .odrain_bit = -1, \
+ .lock_bit = -1, \
+ .parked_bit = -1, \
+ .lpmd_bit = -1, \
+ .drvtype_bit = -1, \
+ .lpdr_bit = -1, \
+ .pbias_buf_bit = -1, \
+ .preemp_bit = -1, \
+ .rfu_in_bit = -1
+
+#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
+ e_lpdr, e_pbias_buf, gpio_sfio_sel, \
+ schmitt_b) \
+ .mux_reg = PINGROUP_REG_Y(r), \
+ .lpmd_bit = -1, \
+ .lock_bit = -1, \
+ .hsm_bit = -1, \
+ .mux_bank = bank, \
+ .mux_bit = 0, \
+ .pupd_reg = PINGROUP_REG_##pupd(r), \
+ .pupd_bank = bank, \
+ .pupd_bit = 2, \
+ .tri_reg = PINGROUP_REG_Y(r), \
+ .tri_bank = bank, \
+ .tri_bit = 4, \
+ .einput_bit = e_input, \
+ .sfsel_bit = gpio_sfio_sel, \
+ .schmitt_bit = schmitt_b, \
+ .drvtype_bit = 13, \
+ .lpdr_bit = e_lpdr,
+
+#define drive_eth1_mdio_pe0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l4_clkreq_n_pd0 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l4_rst_n_pd1 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l5_clkreq_n_pd2 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l5_rst_n_pd3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth0_mdio_pd4 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth0_mdc_pd5 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth1_mdc_pe1 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth2_mdio_pe2 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth2_mdc_pe3 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth3_mdio_pd6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_eth3_mdc_pd7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l1_clkreq_n_pb0 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l1_rst_n_pb1 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_wake_n_pc2 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l2_rst_n_pb3 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l2_clkreq_n_pb2 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l3_clkreq_n_pb4 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pex_l3_rst_n_pb5 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_sgmii0_sma_mdio_pc0 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_sgmii0_sma_mdc_pc1 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio113_pb6 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio114_pb7 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm1_pa0 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm6_pa1 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm7_pa2 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm8_pa3 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_ufs0_ref_clk_pa4 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_ufs0_rst_n_pa5 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+
+#define drive_cpu_pwr_req_ph0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gpu_pwr_req_ph1 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart10_cts_n_ph5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart10_rts_n_ph4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart10_rx_ph3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart10_tx_ph2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi3_cs0_pj1 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi3_cs3_pj2 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi3_miso_ph7 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi3_mosi_pj0 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi3_sck_ph6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart5_cts_n_pj6 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart5_rts_n_pj5 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart5_rx_pj4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart5_tx_pj3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi1_cs0_pk2 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi1_cs1_pk3 DRV_PINGROUP_ENTRY_Y(0x84, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi1_miso_pk0 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi1_mosi_pk1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi1_sck_pj7 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_extperiph2_clk_pk5 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_extperiph1_clk_pk4 DRV_PINGROUP_ENTRY_Y(0xac, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen12_i2c_scl_pk6 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen12_i2c_sda_pk7 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio124_pl0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio125_pl1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_fan_tach0_pl2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio127_pl3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio128_pl4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio129_pl5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio130_pl6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio131_pl7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gp_pwm9_pm0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio133_pm1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart9_cts_n_pm5 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart9_rts_n_pm4 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart9_rx_pm3 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart9_tx_pm2 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N
+#define drive_sdmmc1_clk_px0 DRV_PINGROUP_ENTRY_Y(0x2004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_sdmmc1_cmd_px1 DRV_PINGROUP_ENTRY_Y(0x200c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_sdmmc1_dat3_px5 DRV_PINGROUP_ENTRY_Y(0x201c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_sdmmc1_dat2_px4 DRV_PINGROUP_ENTRY_Y(0x2024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_sdmmc1_dat1_px3 DRV_PINGROUP_ENTRY_Y(0x202c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_sdmmc1_dat0_px2 DRV_PINGROUP_ENTRY_Y(0x2034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_qspi0_cs_n_pt1 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_qspi0_io0_pt2 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_qspi0_io1_pt3 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_qspi0_io2_pt4 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_qspi0_io3_pt5 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_qspi0_sck_pt0 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio192_pt6 DRV_PINGROUP_ENTRY_Y(0x3034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio138_pp0 DRV_PINGROUP_ENTRY_Y(0x5004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio139_pp1 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap6_din_pp4 DRV_PINGROUP_ENTRY_Y(0x5014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap6_dout_pp3 DRV_PINGROUP_ENTRY_Y(0x501c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap6_fs_pp5 DRV_PINGROUP_ENTRY_Y(0x5024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap6_sclk_pp2 DRV_PINGROUP_ENTRY_Y(0x502c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap4_dout_pp7 DRV_PINGROUP_ENTRY_Y(0x5034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap4_sclk_pp6 DRV_PINGROUP_ENTRY_Y(0x503c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap4_din_pq0 DRV_PINGROUP_ENTRY_Y(0x5044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap4_fs_pq1 DRV_PINGROUP_ENTRY_Y(0x504c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi5_cs0_pq5 DRV_PINGROUP_ENTRY_Y(0x5054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi5_miso_pq3 DRV_PINGROUP_ENTRY_Y(0x505c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi5_mosi_pq4 DRV_PINGROUP_ENTRY_Y(0x5064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi5_sck_pq2 DRV_PINGROUP_ENTRY_Y(0x506c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio152_pq6 DRV_PINGROUP_ENTRY_Y(0x5074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio153_pq7 DRV_PINGROUP_ENTRY_Y(0x507c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio155_pr1 DRV_PINGROUP_ENTRY_Y(0x5084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_aud_mclk_pr0 DRV_PINGROUP_ENTRY_Y(0x508c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap1_sclk_pr2 DRV_PINGROUP_ENTRY_Y(0x5094, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap1_in_pr4 DRV_PINGROUP_ENTRY_Y(0x509c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap1_out_pr3 DRV_PINGROUP_ENTRY_Y(0x50a4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap1_fs_pr5 DRV_PINGROUP_ENTRY_Y(0x50ac, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen11_i2c_scl_pr6 DRV_PINGROUP_ENTRY_Y(0x50b4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen11_i2c_sda_pr7 DRV_PINGROUP_ENTRY_Y(0x50bc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio350_ps0 DRV_PINGROUP_ENTRY_Y(0x50c4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio351_ps1 DRV_PINGROUP_ENTRY_Y(0x50cc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen0_i2c_scl_pw4 DRV_PINGROUP_ENTRY_Y(0x6004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen0_i2c_sda_pw5 DRV_PINGROUP_ENTRY_Y(0x600c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen1_i2c_scl_pw2 DRV_PINGROUP_ENTRY_Y(0x6014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_din_pv7 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_dout_pw0 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio172_pu2 DRV_PINGROUP_ENTRY_Y(0x607c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio173_pu3 DRV_PINGROUP_ENTRY_Y(0x6084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio174_pu4 DRV_PINGROUP_ENTRY_Y(0x608c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio175_pu5 DRV_PINGROUP_ENTRY_Y(0x6094, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio176_pu6 DRV_PINGROUP_ENTRY_Y(0x609c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio177_pu7 DRV_PINGROUP_ENTRY_Y(0x60a4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio178_pv0 DRV_PINGROUP_ENTRY_Y(0x60ac, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart4_cts_n_pv5 DRV_PINGROUP_ENTRY_Y(0x60b4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart4_rts_n_pv4 DRV_PINGROUP_ENTRY_Y(0x60bc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart4_rx_pv3 DRV_PINGROUP_ENTRY_Y(0x60c4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart4_tx_pv2 DRV_PINGROUP_ENTRY_Y(0x60cc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwr_i2c_sda_pw7 DRV_PINGROUP_ENTRY_Y(0x60d4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwr_i2c_scl_pw6 DRV_PINGROUP_ENTRY_Y(0x60dc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio250_pf0 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio251_pf1 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio252_pf2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dp_aux_ch0_hpd_pf3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dp_aux_ch1_hpd_pf4 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dp_aux_ch2_hpd_pf5 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dp_aux_ch3_hpd_pf6 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm2_pf7 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_pwm3_pg0 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen7_i2c_scl_pg1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen7_i2c_sda_pg2 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen9_i2c_scl_pg3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen9_i2c_sda_pg4 DRV_PINGROUP_ENTRY_Y(0x7064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio270_py0 DRV_PINGROUP_ENTRY_Y(0xa004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio271_py1 DRV_PINGROUP_ENTRY_Y(0xa00c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio272_py2 DRV_PINGROUP_ENTRY_Y(0xa014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio273_py3 DRV_PINGROUP_ENTRY_Y(0xa01c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio274_py4 DRV_PINGROUP_ENTRY_Y(0xa024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio275_py5 DRV_PINGROUP_ENTRY_Y(0xa02c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio276_py6 DRV_PINGROUP_ENTRY_Y(0xa034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio277_py7 DRV_PINGROUP_ENTRY_Y(0xa03c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio278_pz0 DRV_PINGROUP_ENTRY_Y(0xa044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio279_pz1 DRV_PINGROUP_ENTRY_Y(0xa04c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio282_pz4 DRV_PINGROUP_ENTRY_Y(0xa054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio283_pz5 DRV_PINGROUP_ENTRY_Y(0xa05c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio284_pz6 DRV_PINGROUP_ENTRY_Y(0xa064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio285_pz7 DRV_PINGROUP_ENTRY_Y(0xa06c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio286_pal0 DRV_PINGROUP_ENTRY_Y(0xa074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio287_pal1 DRV_PINGROUP_ENTRY_Y(0xa07c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio288_pal2 DRV_PINGROUP_ENTRY_Y(0xa084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_xhalt_trig_pz2 DRV_PINGROUP_ENTRY_Y(0xa08c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio281_pz3 DRV_PINGROUP_ENTRY_Y(0xa094, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+
+#define drive_ao_retention_n_paa2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_batt_oc_paa3 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_power_on_paa5 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_vcomp_alert_paa1 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_bootv_ctl_n_paa4 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio00_paa0 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio07_paa7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio08_pbb0 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio09_pbb1 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_hdmi_cec_paa6 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen2_i2c_scl_pcc0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen2_i2c_sda_pcc1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen3_i2c_scl_pcc2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gen3_i2c_sda_pcc3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_gp_pwm4_pcc4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart0_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_uart0_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi2_sck_pcc7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi2_miso_pdd0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi2_mosi_pdd1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_spi2_cs0_n_pdd2 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio21_pdd3 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio22_pdd4 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio23_pdd5 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio24_pdd6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio25_pdd7 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio26_pee0 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio27_pee1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_soc_gpio28_pee2 DRV_PINGROUP_ENTRY_N
+#define drive_soc_gpio29_pee3 DRV_PINGROUP_ENTRY_N
+
+#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
+ gpio_sfio_sel, schmitt_b) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = { \
+ TEGRA_MUX_##f0, \
+ TEGRA_MUX_##f1, \
+ TEGRA_MUX_##f2, \
+ TEGRA_MUX_##f3, \
+ }, \
+ PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
+ e_input, e_lpdr, e_pbias_buf, \
+ gpio_sfio_sel, schmitt_b) \
+ drive_##pg_name, \
+ }
+
+static const struct tegra_pingroup tegra264_uphy_groups[] = {
+ PINGROUP(eth1_mdio_pe0, ETH1_MDIO, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l4_clkreq_n_pd0, PE4_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l4_rst_n_pd1, PE4_RST_L, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l5_clkreq_n_pd2, PE5_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l5_rst_n_pd3, PE5_RST_L, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth0_mdio_pd4, ETH0_MDIO, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth0_mdc_pd5, ETH0_MDC, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth1_mdc_pe1, ETH1_MDC, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth2_mdio_pe2, ETH2_MDIO, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth2_mdc_pe3, ETH2_MDC, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth3_mdio_pd6, ETH3_MDIO, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(eth3_mdc_pd7, ETH3_MDC, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l1_clkreq_n_pb0, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l1_rst_n_pb1, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_wake_n_pc2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l2_rst_n_pb3, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l2_clkreq_n_pb2, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l3_clkreq_n_pb4, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pex_l3_rst_n_pb5, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(sgmii0_sma_mdio_pc0, SGMII0_SMA_MDIO, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(sgmii0_sma_mdc_pc1, SGMII0_SMA_MDC, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio113_pb6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio114_pb7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm1_pa0, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm6_pa1, GP_PWM6, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm7_pa2, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm8_pa3, GP_PWM8, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(ufs0_ref_clk_pa4, UFS0, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(ufs0_rst_n_pa5, UFS0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+};
+
+static const struct tegra_pingroup tegra264_main_groups[] = {
+ PINGROUP(cpu_pwr_req_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gpu_pwr_req_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart10_cts_n_ph5, UARTK_CTS, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart10_rts_n_ph4, UARTK_RTS, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart10_rx_ph3, UARTK_RXD, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart10_tx_ph2, UARTK_TXD, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi3_cs0_pj1, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi3_cs3_pj2, SPI3_CS3, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi3_miso_ph7, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi3_mosi_pj0, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi3_sck_ph6, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart5_cts_n_pj6, UARTF_CTS, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart5_rts_n_pj5, UARTF_RTS, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart5_rx_pj4, UARTF_RXD, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart5_tx_pj3, UARTF_TXD, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi1_cs0_pk2, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0x78, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi1_cs1_pk3, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0x80, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi1_miso_pk0, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0x88, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi1_mosi_pk1, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0x90, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi1_sck_pj7, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0x98, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(extperiph2_clk_pk5, EXTPERIPH2_CLK, RSVD1, DMIC2_CLK, DSPK1_CLK, 0xa0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(extperiph1_clk_pk4, EXTPERIPH1_CLK, RSVD1, DMIC2_DAT, DSPK1_DAT, 0xa8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen12_i2c_scl_pk6, I2C12_CLK, RSVD1, RSVD2, RSVD3, 0xb0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen12_i2c_sda_pk7, I2C12_DAT, RSVD1, RSVD2, RSVD3, 0xb8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio124_pl0, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio125_pl1, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(fan_tach0_pl2, NV_THERM_FAN_TACH0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio127_pl3, RSVD0, RSVD1, NV_THERM_FAN_TACH1, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio128_pl4, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio129_pl5, RSVD0, EXTPERIPH3_CLK, I2C15_CLK, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio130_pl6, RSVD0, EXTPERIPH4_CLK, I2C15_DAT, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio131_pl7, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gp_pwm9_pm0, GP_PWM9, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio133_pm1, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart9_cts_n_pm5, UARTJ_CTS, RSVD1, RSVD2, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart9_rts_n_pm4, UARTJ_RTS, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart9_rx_pm3, UARTJ_RXD, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart9_tx_pm2, UARTJ_TXD, RSVD1, RSVD2, RSVD3, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(sdmmc1_clk_px0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 5, 6, 13, -1, 10, -1),
+ PINGROUP(sdmmc1_cmd_px1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 5, 6, 13, -1, 10, -1),
+ PINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x2010, 0, N, -1, -1, -1, -1, -1, -1, -1),
+ PINGROUP(sdmmc1_dat3_px5, SDMMC1_DAT3, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 5, 6, 13, -1, 10, -1),
+ PINGROUP(sdmmc1_dat2_px4, SDMMC1_DAT2, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, 5, 6, 13, -1, 10, -1),
+ PINGROUP(sdmmc1_dat1_px3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, -1, 5, 6, 13, -1, 10, -1),
+ PINGROUP(sdmmc1_dat0_px2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, 5, 6, 13, -1, 10, -1),
+ PINGROUP(qspi0_cs_n_pt1, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(qspi0_io0_pt2, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(qspi0_io1_pt3, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(qspi0_io2_pt4, QSPI0_IO2, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(qspi0_io3_pt5, QSPI0_IO3, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(qspi0_sck_pt0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio192_pt6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio138_pp0, RSVD0, I2C14_CLK, DMIC1_DAT, RSVD3, 0x5000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio139_pp1, RSVD0, I2C14_DAT, DMIC1_CLK, RSVD3, 0x5008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap6_din_pp4, I2S6_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap6_dout_pp3, I2S6_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap6_fs_pp5, I2S6_LRCK, RSVD1, RSVD2, RSVD3, 0x5020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap6_sclk_pp2, I2S6_SCLK, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap4_dout_pp7, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap4_sclk_pp6, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap4_din_pq0, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap4_fs_pq1, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi5_cs0_pq5, SPI5_CS0, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi5_miso_pq3, SPI5_DIN, RSVD1, RSVD2, RSVD3, 0x5058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi5_mosi_pq4, SPI5_DOUT, RSVD1, RSVD2, RSVD3, 0x5060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi5_sck_pq2, SPI5_SCK, RSVD1, RSVD2, RSVD3, 0x5068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio152_pq6, RSVD0, I2S8_SCLK, RSVD2, RSVD3, 0x5070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio153_pq7, RSVD0, I2S8_SDATA_OUT, RSVD2, RSVD3, 0x5078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio155_pr1, RSVD0, I2S8_LRCK, RSVD2, RSVD3, 0x5080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(aud_mclk_pr0, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x5088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap1_sclk_pr2, I2S1_SCLK, RSVD1, RSVD2, RSVD3, 0x5090, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap1_in_pr4, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5098, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap1_out_pr3, I2S1_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x50a0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap1_fs_pr5, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x50a8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen11_i2c_scl_pr6, I2C11_CLK, RSVD1, RSVD2, RSVD3, 0x50b0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen11_i2c_sda_pr7, I2C11_DAT, RSVD1, RSVD2, RSVD3, 0x50b8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio350_ps0, RSVD0, I2S8_SDATA_IN, RSVD2, RSVD3, 0x50c0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio351_ps1, RSVD0, RSVD1, RSVD2, RSVD3, 0x50c8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen0_i2c_scl_pw4, I2C0_CLK, RSVD1, RSVD2, RSVD3, 0x6000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen0_i2c_sda_pw5, I2C0_DAT, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen1_i2c_scl_pw2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio172_pu2, RSVD0, SPI4_DIN, RSVD2, RSVD3, 0x6078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio173_pu3, RSVD0, SPI4_DOUT, RSVD2, RSVD3, 0x6080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio174_pu4, RSVD0, SPI4_CS0, RSVD2, RSVD3, 0x6088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio175_pu5, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x6090, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio176_pu6, RSVD0, RSVD1, I2S7_SCLK, RSVD3, 0x6098, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio177_pu7, RSVD0, GP_PWM5, RSVD2, RSVD3, 0x60a0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio178_pv0, RSVD0, RSVD1, I2S7_SDATA_OUT, RSVD3, 0x60a8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart4_cts_n_pv5, UARTE_CTS, RSVD1, RSVD2, RSVD3, 0x60b0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart4_rts_n_pv4, UARTE_RTS, RSVD1, RSVD2, RSVD3, 0x60b8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart4_rx_pv3, UARTE_RXD, RSVD1, RSVD2, RSVD3, 0x60c0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart4_tx_pv2, UARTE_TXD, RSVD1, RSVD2, RSVD3, 0x60c8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwr_i2c_sda_pw7, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x60d0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwr_i2c_scl_pw6, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x60d8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio250_pf0, DCA_VSYNC, DCB_VSYNC, DCC_VSYNC, DCD_VSYNC, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio251_pf1, DCA_HSYNC, DCB_HSYNC, DCC_HSYNC, DCD_HSYNC, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio252_pf2, RSVD0, DSA_LSPII, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dp_aux_ch0_hpd_pf3, DP_AUX_CH0_HPD, DCE_VSYNC, DCF_VSYNC, DCG_VSYNC, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dp_aux_ch1_hpd_pf4, DP_AUX_CH1_HPD, DCE_HSYNC, DCF_HSYNC, DCG_HSYNC, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dp_aux_ch2_hpd_pf5, DP_AUX_CH2_HPD, DCH_VSYNC, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(dp_aux_ch3_hpd_pf6, DP_AUX_CH3_HPD, DCH_HSYNC, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm2_pf7, GP_PWM2, BL_EN, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(pwm3_pg0, GP_PWM3, BL_PWM_DIM0, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen7_i2c_scl_pg1, I2C7_CLK, RSVD1, SOUNDWIRE1_CLK, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen7_i2c_sda_pg2, I2C7_DAT, RSVD1, SOUNDWIRE1_DAT0, RSVD3, 0x7050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen9_i2c_scl_pg3, I2C9_CLK, RSVD1, SOUNDWIRE1_DAT1, RSVD3, 0x7058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen9_i2c_sda_pg4, I2C9_DAT, RSVD1, SOUNDWIRE1_DAT2, RSVD3, 0x7060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio270_py0, RSVD0, I2C16_CLK, RSVD2, RSVD3, 0xa000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio271_py1, RSVD0, I2C16_DAT, RSVD2, RSVD3, 0xa008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio272_py2, RSVD0, I2S3_SCLK, RSVD2, RSVD3, 0xa010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio273_py3, RSVD0, I2S3_SDATA_OUT, RSVD2, RSVD3, 0xa018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio274_py4, RSVD0, I2S3_SDATA_IN, RSVD2, RSVD3, 0xa020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio275_py5, RSVD0, I2S3_LRCK, RSVD2, RSVD3, 0xa028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio276_py6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio277_py7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio278_pz0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio279_pz1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio282_pz4, RSVD0, PM_TRIG1, RSVD2, RSVD3, 0xa050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio283_pz5, RSVD0, RSVD1, RSVD2, RSVD3, 0xa058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio284_pz6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio285_pz7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio286_pal0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio287_pal1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio288_pal2, RSVD0, RSVD1, RSVD2, RSVD3, 0xa080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(xhalt_trig_pz2, XHALT_TRIG, RSVD1, RSVD2, RSVD3, 0xa088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio281_pz3, RSVD0, PM_TRIG0, RSVD2, RSVD3, 0xa090, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+};
+
+static const struct tegra_pingroup tegra264_aon_groups[] = {
+ PINGROUP(ao_retention_n_paa2, RSVD0, RSVD1, RSVD2, ISTCTRL_IST_DONE_N, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(batt_oc_paa3, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(power_on_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(vcomp_alert_paa1, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(bootv_ctl_n_paa4, RSVD0, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio00_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio07_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio08_pbb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio09_pbb1, RSVD0, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(hdmi_cec_paa6, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen2_i2c_scl_pcc0, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen2_i2c_sda_pcc1, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen3_i2c_scl_pcc2, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gen3_i2c_sda_pcc3, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(gp_pwm4_pcc4, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart0_tx_pcc5, UARTA_TXD, RSVD1, UARTL_TXD, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(uart0_rx_pcc6, UARTA_RXD, RSVD1, UARTL_RXD, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi2_sck_pcc7, SPI2_SCK, RSVD1, I2S9_SCLK, SOUNDWIRE0_CLK, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi2_miso_pdd0, SPI2_DIN, RSVD1, I2S9_SDATA_OUT, SOUNDWIRE0_DAT0, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi2_mosi_pdd1, SPI2_DOUT, RSVD1, I2S9_SDATA_IN, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(spi2_cs0_n_pdd2, SPI2_CS0, RSVD1, I2S9_LRCK, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio21_pdd3, RSVD0, TSC_SYNC1, DMIC5_DAT, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio22_pdd4, RSVD0, RSVD1, DMIC5_CLK, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio23_pdd5, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio24_pdd6, RSVD0, TSC_EDGE_OUT3, RSVD2, TSC_EDGE_OUT0D, 0x1070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio25_pdd7, RSVD0, TSC_EDGE_OUT0, RSVD2, TSC_EDGE_OUT0A, 0x1078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio26_pee0, RSVD0, TSC_EDGE_OUT1, RSVD2, TSC_EDGE_OUT0B, 0x1080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio27_pee1, RSVD0, TSC_SYNC0, RSVD2, RSVD3, 0x1088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+ PINGROUP(soc_gpio28_pee2, L0L1_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1090, 0, N, -1, -1, -1, -1, -1, 10, -1),
+ PINGROUP(soc_gpio29_pee3, L2_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1098, 0, N, -1, -1, -1, -1, -1, 10, -1),
+};
+
+static const struct tegra_pinctrl_soc_data tegra264_uphy_pinctrl = {
+ .pins = tegra264_uphy_pins,
+ .npins = ARRAY_SIZE(tegra264_uphy_pins),
+ .functions = tegra264_functions,
+ .nfunctions = ARRAY_SIZE(tegra264_functions),
+ .groups = tegra264_uphy_groups,
+ .ngroups = ARRAY_SIZE(tegra264_uphy_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = true,
+ .drvtype_in_mux = true,
+ .sfsel_in_mux = true,
+};
+
+static const struct tegra_pinctrl_soc_data tegra264_main_pinctrl = {
+ .pins = tegra264_main_pins,
+ .npins = ARRAY_SIZE(tegra264_main_pins),
+ .functions = tegra264_functions,
+ .nfunctions = ARRAY_SIZE(tegra264_functions),
+ .groups = tegra264_main_groups,
+ .ngroups = ARRAY_SIZE(tegra264_main_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = true,
+ .drvtype_in_mux = true,
+ .sfsel_in_mux = true,
+};
+
+static const struct tegra_pinctrl_soc_data tegra264_aon_pinctrl = {
+ .pins = tegra264_aon_pins,
+ .npins = ARRAY_SIZE(tegra264_aon_pins),
+ .functions = tegra264_functions,
+ .nfunctions = ARRAY_SIZE(tegra264_functions),
+ .groups = tegra264_aon_groups,
+ .ngroups = ARRAY_SIZE(tegra264_aon_groups),
+ .hsm_in_mux = false,
+ .schmitt_in_mux = true,
+ .drvtype_in_mux = true,
+ .sfsel_in_mux = true,
+};
+
+static int tegra264_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);
+
+ return tegra_pinctrl_probe(pdev, soc);
+}
+
+static const struct of_device_id tegra264_pinctrl_of_match[] = {
+ { .compatible = "nvidia,tegra264-pinmux-uphy", .data = &tegra264_uphy_pinctrl},
+ { .compatible = "nvidia,tegra264-pinmux-main", .data = &tegra264_main_pinctrl},
+ { .compatible = "nvidia,tegra264-pinmux-aon", .data = &tegra264_aon_pinctrl},
+ { }
+};
+MODULE_DEVICE_TABLE(of, tegra264_pinctrl_of_match);
+
+static struct platform_driver tegra264_pinctrl_driver = {
+ .driver = {
+ .name = "tegra264-pinctrl",
+ .of_match_table = tegra264_pinctrl_of_match,
+ },
+ .probe = tegra264_pinctrl_probe,
+};
+
+static int __init tegra264_pinctrl_init(void)
+{
+ return platform_driver_register(&tegra264_pinctrl_driver);
+}
+module_init(tegra264_pinctrl_init);
+
+static void __exit tegra264_pinctrl_exit(void)
+{
+ platform_driver_unregister(&tegra264_pinctrl_driver);
+}
+module_exit(tegra264_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_DESCRIPTION("NVIDIA Tegra264 pinctrl driver");
--
2.43.0
^ permalink raw reply related
* [PATCH 6/6] arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module
From: pshete @ 2026-04-09 13:13 UTC (permalink / raw)
To: linux-gpio, devicetree, linux-tegra, linux-kernel, arnd,
bjorn.andersson, conor+dt, dmitry.baryshkov, ebiggers, geert,
jonathanh, krzk+dt, kuninori.morimoto.gx, linusw, luca.weiss,
michal.simek, prabhakar.mahadev-lad.rj, robh, rosenp, sven,
thierry.reding, webgeek1234
Cc: pshete
In-Reply-To: <20260409131340.168556-1-pshete@nvidia.com>
From: Prathamesh Shete <pshete@nvidia.com>
Building the Pinctrl driver into the kernel image increases its size.
These drivers are not required during early boot, build them as a loadable
module instead to reduce the kernel image size.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dd1ac01ee29b..f525670d3b84 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
CONFIG_PINCTRL_SM8550_LPASS_LPI=m
CONFIG_PINCTRL_SM8650_LPASS_LPI=m
CONFIG_PINCTRL_SOPHGO_SG2000=y
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m
CONFIG_GPIO_ALTERA=m
CONFIG_GPIO_CADENCE=m
CONFIG_GPIO_DAVINCI=y
--
2.43.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox