* [PATCH 0/2] Update Sasha Finkelstein's email address
From: Sasha Finkelstein @ 2026-04-11 14:36 UTC (permalink / raw)
To: Sasha Finkelstein, Janne Grunau, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sven Peter, Neal Gompa, asahi
Cc: linux-kernel, devicetree
Moving away from gmail
Signed-off-by: Sasha Finkelstein <k@chaosmail.tech>
---
Sasha Finkelstein (2):
mailmap: Update Sasha Finkelstein's email address
dt-bindings: Update Sasha Finkelstein's email address
.mailmap | 1 +
Documentation/devicetree/bindings/display/apple,h7-display-pipe-mipi.yaml | 2 +-
Documentation/devicetree/bindings/display/apple,h7-display-pipe.yaml | 2 +-
Documentation/devicetree/bindings/display/panel/apple,summit.yaml | 2 +-
Documentation/devicetree/bindings/gpu/apple,agx.yaml | 2 +-
Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml | 2 +-
Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml | 2 +-
Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml | 2 +-
Documentation/devicetree/bindings/spmi/apple,spmi.yaml | 2 +-
MAINTAINERS | 2 +-
10 files changed, 10 insertions(+), 9 deletions(-)
---
base-commit: 7c6c4ed80b874f721bc7c2c937e098c56e37d2f0
change-id: 20260410-mailmap-7953b322000a
Best regards,
--
Sasha Finkelstein <k@chaosmail.tech>
^ permalink raw reply
* [PATCH 1/2] mailmap: Update Sasha Finkelstein's email address
From: Sasha Finkelstein @ 2026-04-11 14:36 UTC (permalink / raw)
To: Sasha Finkelstein, Janne Grunau, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sven Peter, Neal Gompa, asahi
Cc: linux-kernel, devicetree
In-Reply-To: <20260411-mailmap-v1-0-5a519f7b00b5@chaosmail.tech>
Add mailmap entry
Signed-off-by: Sasha Finkelstein <k@chaosmail.tech>
---
.mailmap | 1 +
MAINTAINERS | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/.mailmap b/.mailmap
index 22c5ab1c5d55..df3cd6a25780 100644
--- a/.mailmap
+++ b/.mailmap
@@ -733,6 +733,7 @@ Sarangdhar Joshi <spjoshi@codeaurora.org>
Saravana Kannan <saravanak@kernel.org> <skannan@codeaurora.org>
Saravana Kannan <saravanak@kernel.org> <saravanak@google.com>
Sascha Hauer <s.hauer@pengutronix.de>
+Sasha Finkelstein <k@chaosmail.tech> <fnkl.kernel@gmail.com>
Sahitya Tummala <quic_stummala@quicinc.com> <stummala@codeaurora.org>
Sathishkumar Muruganandam <quic_murugana@quicinc.com> <murugana@codeaurora.org>
Satya Priya <quic_skakitap@quicinc.com> <quic_c_skakit@quicinc.com> <skakit@codeaurora.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index d238590a31f2..0d7a00ae3fc3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8668,7 +8668,7 @@ F: include/linux/host1x.h
F: include/uapi/drm/tegra_drm.h
DRM DRIVERS FOR PRE-DCP APPLE DISPLAY OUTPUT
-M: Sasha Finkelstein <fnkl.kernel@gmail.com>
+M: Sasha Finkelstein <k@chaosmail.tech>
R: Janne Grunau <j@jannau.net>
L: dri-devel@lists.freedesktop.org
L: asahi@lists.linux.dev
--
2.53.0
^ permalink raw reply related
* Re: [PATCH 01/35] dt-bindings: qcom,pdc: Tighten reg to single APSS DRV region
From: Dmitry Baryshkov @ 2026-04-11 14:32 UTC (permalink / raw)
To: Mukesh Ojha
Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, cros-qcom-dts-watchers,
linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260410184124.1068210-2-mukesh.ojha@oss.qualcomm.com>
On Sat, Apr 11, 2026 at 12:10:38AM +0530, Mukesh Ojha wrote:
> The PDC has multiple DRV regions, each sized 0x10000, where each region
> serves a specific client in the system. Linux only needs access to the
Nit: there are other OS than Linux. Would you rather point out that
other DRV regions are to be used by ... what?
> APSS DRV region, so the reg property should describe exactly one DRV
> region of size 0x10000.
>
> The example was using 0x30000 (three DRV regions) which is incorrect.
> Fix it to use 0x10000 to match the single APSS DRV region that the
> driver actually maps, consistent with the DT fixes applied across all
> platforms in this series.
>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
> .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> index f9321366cae4..786709f2d13e 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
> @@ -96,7 +96,7 @@ examples:
>
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sdm845-pdc", "qcom,pdc";
> - reg = <0xb220000 0x30000>;
> + reg = <0xb220000 0x10000>;
> qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
> #interrupt-cells = <2>;
> interrupt-parent = <&intc>;
> --
> 2.53.0
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: qcom: sdm845-google: Enable PMI8998 camera flash LED
From: Dmitry Baryshkov @ 2026-04-11 14:29 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Petr Hodina, Richard Acayan, linux-arm-msm,
devicetree, linux-kernel, phone-devel
In-Reply-To: <20260411-pixel3-camera-v2-2-41b889abb14c@ixit.cz>
On Sat, Apr 11, 2026 at 12:12:03PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Enable the PMI8998 flash LED block and describe the white flash LED
> used for the rear camera.
>
> Configure the LED in flash mode with hardware limits matching the
> original device configuration, including maximum current and timeout.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 1/2] arm64: dts: qcom: sdm845-google: Add dual front IMX355 cameras
From: Dmitry Baryshkov @ 2026-04-11 14:29 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Petr Hodina, Richard Acayan, linux-arm-msm,
devicetree, linux-kernel, phone-devel
In-Reply-To: <20260411-pixel3-camera-v2-1-41b889abb14c@ixit.cz>
On Sat, Apr 11, 2026 at 12:12:02PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> The Pixel 3 features two front-facing Sony IMX355 sensors with
> different focal lengths (standard and wide-angle).
>
> Both sensors are connected via CSIPHY1 and controlled over CCI I2C1,
> using MCLK2 as the clock source. Describe the camera nodes and
> associated resources in the device tree.
>
> This enables support for the dual front camera configuration.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 187 ++++++++++++++++++++-
> 1 file changed, 186 insertions(+), 1 deletion(-)
>
> @@ -319,6 +362,12 @@ vreg_l28a_3p0: ldo28 {
> */
> regulator-always-on;
> };
> +
> + cam_vio_1p8:
No need for extra labels.
> + vreg_lvs1_1p8: lvs1 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> };
>
> regulators-1 {
> @@ -351,6 +400,45 @@ vreg_s3c_0p6: smps3 {
> };
> };
>
> +&camss {
> + vdda-phy-supply = <&vreg_l1a_0p875>;
> + vdda-pll-supply = <&vreg_l26a_1p2>;
> +
> + vdda-csi0-supply = <&vdda_mipi_csi0_0p9>;
> + vdda-csi1-supply = <&vdda_mipi_csi1_0p9>;
> + vdda-csi2-supply = <&vdda_mipi_csi2_0p9>;
> +
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + camss_endpoint1: endpoint {
> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&cam_aux_front_endpoint>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + camss_endpoint2: endpoint {
> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&cam_front_endpoint>;
> + };
> + };
> + };
> +};
> +
> +&cci0_sleep {
> + /* bus has external pull-up, don't pull down */
> + bias-disable;
> +};
> +
> &cci {
> status = "okay";
> };
> @@ -358,7 +446,72 @@ &cci {
> &cci_i2c1 {
> /* actuator @0c */
>
> - /* front camera, imx355 @1a */
> + front_cam: camera@10 {
> + compatible = "sony,imx355";
> + reg = <0x10>;
> +
> + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
> + assigned-clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
> + /*
> + * The sensor can accept a 24 MHz clock, but 19.2 MHz has
> + * better driver compatibility.
> + */
> + assigned-clock-rates = <19200000>;
> +
> + reset-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
> +
> + avdd-supply = <&camera_front_avdd>;
> + dvdd-supply = <&vreg_s3a_1p35>;
> + dovdd-supply = <&cam_vio_1p8>;
> +
> + /* MCLK2 pin (gpio15) is claimed by the aux sensor */
Can we require it from the camss node then?
> + pinctrl-0 = <&cam_front_reset_default_pin>;
> + pinctrl-names = "default";
> +
> + rotation = <270>;
> + orientation = <0>;
> +
> + port {
> + cam_front_endpoint: endpoint {
> + data-lanes = <1 2 3 4>;
> + link-frequencies = /bits/ 64 <360000000>;
> + remote-endpoint = <&camss_endpoint2>;
> + };
> + };
> + };
> +
> + front_aux_cam: camera@1a {
> + compatible = "sony,imx355";
> + reg = <0x1a>;
> +
> + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
> + assigned-clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
> + /*
> + * The sensor can accept a 24 MHz clock, but 19.2 MHz has
> + * better driver compatibility.
> + */
> + assigned-clock-rates = <19200000>;
> +
> + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
> +
> + avdd-supply = <&camera_front_aux_avdd>;
> + dvdd-supply = <&vreg_s3a_1p35>;
> + dovdd-supply = <&cam_vio_1p8>;
> +
> + pinctrl-0 = <&cam_mclk2_default &cam_front_aux_reset_default_pin>;
> + pinctrl-names = "default";
> +
> + rotation = <270>;
> + orientation = <0>;
> +
> + port {
> + cam_aux_front_endpoint: endpoint {
> + data-lanes = <1 2 3 4>;
> + link-frequencies = /bits/ 64 <360000000>;
> + remote-endpoint = <&camss_endpoint1>;
> + };
> + };
> + };
>
> /* eeprom @50, at24 driver says 8K */
> };
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints
From: Krzysztof Kozlowski @ 2026-04-11 14:07 UTC (permalink / raw)
To: Swamil Jain
Cc: jyri.sarha, tomi.valkeinen, maarten.lankhorst, mripard,
tzimmermann, airlied, simona, robh, krzk+dt, conor+dt, devarsht,
dri-devel, devicetree, linux-kernel, praneeth, vigneshr
In-Reply-To: <20260410105955.843868-1-s-jain1@ti.com>
On Fri, Apr 10, 2026 at 04:29:55PM +0530, Swamil Jain wrote:
> clocks:
> + minItems: 2
> items:
> - description: fck DSS functional clock
> - description: vp1 Video Port 1 pixel clock
> - description: vp2 Video Port 2 pixel clock
>
> clock-names:
> + minItems: 2
> items:
> - const: fck
> - const: vp1
> @@ -179,6 +195,20 @@ allOf:
> ports:
> properties:
> port@1: false
> + clock-names:
> + maxItems: 2
> + clocks:
> + maxItems: 2
> + reg:
> + maxItems: 5
Also constrain for reg-names,
> + else:
> + properties:
> + clock-names:
> + minItems: 3
> + clocks:
> + minItems: 3
> + reg:
> + minItems: 8
Same here, please.
And if you are sending new version: they should be listed in the same
order as in top-level properties, so reg, reg-names, clocks and
clock-names. (juging by the diff)
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 09/11] dt-bindings: input: touchscreen: st,stmfts: Introduce STM FTS5
From: Krzysztof Kozlowski @ 2026-04-11 14:02 UTC (permalink / raw)
To: David Heidelberg
Cc: Dmitry Torokhov, Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Henrik Rydberg,
Bjorn Andersson, Konrad Dybcio, Petr Hodina, linux-input,
linux-stm32, linux-arm-kernel, linux-kernel, devicetree,
linux-arm-msm, phone-devel
In-Reply-To: <20260409-stmfts5-v4-9-64fe62027db5@ixit.cz>
On Thu, Apr 09, 2026 at 12:15:52AM +0200, David Heidelberg wrote:
> Introduce more recent STM FTS5 touchscreen support.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> .../devicetree/bindings/input/touchscreen/st,stmfts.yaml | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml
> index 64c4f24ea3dd0..441fc92b9a4ed 100644
> --- a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml
> +++ b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml
> @@ -16,10 +16,19 @@ description:
>
> allOf:
> - $ref: touchscreen.yaml#
> + - if:
> + properties:
> + compatible:
> + const: st,stmfts5
> + then:
> + required:
> + - mode-switch-gpios
Does existing variant have these pins? If not, then missing else with
"mode-switch-gpios: false".
Please move entire allOf to the bottom, like in example-schema, so after
"required" block.
>
> properties:
> compatible:
> - const: st,stmfts
> + enum:
> + - st,stmfts
> + - st,stmfts5
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 05/21] dt-bindings: dipslay/panel: describe panels using Focaltech OTA7290B
From: Rob Herring (Arm) @ 2026-04-11 14:02 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Cong Yang, Ondrej Jirman, Maxime Ripard, Linus Walleij,
Javier Martinez Canillas, Krzysztof Kozlowski, Neil Armstrong,
Bartosz Golaszewski, Liam Girdwood, Mark Brown, dri-devel,
Thomas Zimmermann, Jagan Teki, Simona Vetter, David Airlie,
Maarten Lankhorst, Conor Dooley, Jessica Zhang, linux-gpio,
devicetree, linux-kernel
In-Reply-To: <20260411-waveshare-dsi-touch-v2-5-75cdbeac5156@oss.qualcomm.com>
On Sat, 11 Apr 2026 15:10:25 +0300, Dmitry Baryshkov wrote:
> Add schema for the panels using Focaltech OTA7290B controller. For now
> there is only one such panel, from the Waveshare 8.8 DSI TOUCH-A kit.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> .../bindings/display/panel/focaltech,ota7290b.yaml | 70 ++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.example.dtb: /example-0/dsi/panel@0: failed to match any schema with compatible: ['waveshare,8.8-dsi-touch-a']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260411-waveshare-dsi-touch-v2-5-75cdbeac5156@oss.qualcomm.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH v4 07/11] dt-bindings: input: touchscreen: st,stmfts: Introduce reset GPIO
From: Krzysztof Kozlowski @ 2026-04-11 14:01 UTC (permalink / raw)
To: David Heidelberg
Cc: Dmitry Torokhov, Maxime Coquelin, Alexandre Torgue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Henrik Rydberg,
Bjorn Andersson, Konrad Dybcio, Petr Hodina, linux-input,
linux-stm32, linux-arm-kernel, linux-kernel, devicetree,
linux-arm-msm, phone-devel
In-Reply-To: <20260409-stmfts5-v4-7-64fe62027db5@ixit.cz>
On Thu, Apr 09, 2026 at 12:15:50AM +0200, David Heidelberg wrote:
> FTS has associated reset GPIO, document it.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 3/4] arm64: dts: hpe: Add HPE GSC SoC and DL340 Gen12 board DTS
From: Krzysztof Kozlowski @ 2026-04-11 14:00 UTC (permalink / raw)
To: nick.hawkins
Cc: catalin.marinas, will, robh, krzk+dt, conor+dt,
krzysztof.kozlowski, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260410171611.2547255-4-nick.hawkins@hpe.com>
On Fri, Apr 10, 2026 at 05:16:10PM +0000, nick.hawkins@hpe.com wrote:
> + uarte: serial@c00003e0 {
> + compatible = "ns16550a";
> + reg = <0xc00003e0 0x8>;
> + clock-frequency = <1846153>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <0>;
> + };
> +
> + gic: gic@ce000000 {
Nodename should be interrupt-controller@
With this fixed:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 4/4] arm64: defconfig: Enable ARCH_HPE
From: Krzysztof Kozlowski @ 2026-04-11 13:59 UTC (permalink / raw)
To: nick.hawkins
Cc: catalin.marinas, will, robh, krzk+dt, conor+dt,
krzysztof.kozlowski, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260410171611.2547255-5-nick.hawkins@hpe.com>
On Fri, Apr 10, 2026 at 05:16:11PM +0000, nick.hawkins@hpe.com wrote:
> From: Nick Hawkins <nick.hawkins@hpe.com>
>
> Enable ARCH_HPE in the arm64 defconfig to include HPE GSC BMC SoC
> support in the default build.
>
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 3/3] arm64: dts: rockchip: Add Orange Pi 5 Pro board support
From: Krzysztof Kozlowski @ 2026-04-11 13:58 UTC (permalink / raw)
To: dennis
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
FUKAUMI Naoki, Hsun Lai, Jonas Karlman, Chaoyi Chen, John Clark,
Michael Opdenacker, Quentin Schulz, Andrew Lunn, Chukun Pan,
Alexey Charkov, Peter Robinson, Michael Riesch, Mykola Kvach,
Jimmy Hon, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260411024743.195385-4-dennis@ausil.us>
On Fri, Apr 10, 2026 at 09:47:43PM -0500, dennis@ausil.us wrote:
> From: Dennis Gilmore <dennis@ausil.us>
>
> Add device tree for the Xunlong Orange Pi 5 Pro (RK3588S).
>
> - eMMC module, you can optionally solder a SPI NOR in place and turn
> off the eMMC
> - PCIe-attached NIC (pcie2x1l1)
> - PCIe NVMe slot (pcie2x1l2)
> - AP6256 WiFi (BCM43456) via SDIO with mmc-pwrseq
> - BCM4345C5 Bluetooth
> - es8388 audio
> - USB 2.0 and USB 3.0
> - Two HDMI ports, the second is connected to the SoC's DP controller
> driven by a transparent LT8711UXD bridge that has firmware onboard and
> needs no node defined.
>
> Vendors description and links to schematics available:
> http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-Pro.html
>
> Signed-off-by: Dennis Gilmore <dennis@ausil.us>
> ---
> .../display/rockchip/rockchip,dw-dp.yaml | 7 +
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
Didn't you already got this comment?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v9 2/3] hwmon: ltc4283: Add support for the LTC4283 Swap Controller
From: Nuno Sá @ 2026-04-11 12:38 UTC (permalink / raw)
To: Guenter Roeck, nuno.sa, linux-gpio, linux-hwmon, devicetree,
linux-doc
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Corbet,
Linus Walleij, Bartosz Golaszewski
In-Reply-To: <29b207c8-10ab-42b4-a1c8-988aacc75154@roeck-us.net>
On Fri, 2026-04-10 at 16:27 -0700, Guenter Roeck wrote:
> On 4/6/26 07:31, Nuno Sá via B4 Relay wrote:
> > From: Nuno Sá <nuno.sa@analog.com>
> >
> > Support the LTC4283 Hot Swap Controller. The device features programmable
> > current limit with foldback and independently adjustable inrush current to
> > optimize the MOSFET safe operating area (SOA). The SOA timer limits MOSFET
> > temperature rise for reliable protection against overstresses.
> >
> > An I2C interface and onboard ADC allow monitoring of board current,
> > voltage, power, energy, and fault status.
> >
> > Signed-off-by: Nuno Sá <nuno.sa@analog.com>
>
> The patch still has some issues. Please see
>
> https://sashiko.dev/#/patchset/20260406-ltc4283-support-v9-0-b66cfc749261%40analog.com
>
> Specifically:
>
> - regmap_clear_bits() may not cause problems, but it is not the best
> choice either because the register was already read.
> It might be better to just write the value to be masked since
> both the register value and the mask are known.
Fair enough.
>
> - I can't comment on the energy accuracy lost. That is your call.
>
The AI might have a point. Maybe you know better but if I understood correctly,
mul_u64_u64_div_u64() will handle the multiplication by using 128bits (when
available) or if not, using clever tricks. And it should also handle overflows.
So my feeling is that we can simplify all of those check_overflow paths with the
suggested API.
> - Clamping before multiplying is indeed wrong.
> You'll need to clamp before multiplying (and then possibly
> clamp again).
Yeah, the clamp change was just nonsense from me. What about about
val = clamp_val((u64)val * MILLI, ...)
?
> - %*ph: The AI seems to have a point.
Indeed!
FWIW, I was already aware of the AI feedback but I'll just setup things locally and
run the review before submitting again.
- Nuno Sá
>
> - debugfs: False positive. I'll need to check if the guidance ever made it into the
> Agent's prompts.
>
> Thanks,
> Guenter
>
> > ---
> > Documentation/hwmon/index.rst | 1 +
> > Documentation/hwmon/ltc4283.rst | 266 ++++++
> > MAINTAINERS | 1 +
> > drivers/hwmon/Kconfig | 12 +
> > drivers/hwmon/Makefile | 1 +
> > drivers/hwmon/ltc4283.c | 1808 +++++++++++++++++++++++++++++++++++++++
> > 6 files changed, 2089 insertions(+)
> >
> > diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
> > index 199f35a75282..d54dda83ab6e 100644
> > --- a/Documentation/hwmon/index.rst
> > +++ b/Documentation/hwmon/index.rst
> > @@ -144,6 +144,7 @@ Hardware Monitoring Kernel Drivers
> > ltc4260
> > ltc4261
> > ltc4282
> > + ltc4283
> > ltc4286
> > macsmc-hwmon
> > max127
> > diff --git a/Documentation/hwmon/ltc4283.rst b/Documentation/hwmon/ltc4283.rst
> > new file mode 100644
> > index 000000000000..ba88445e45f4
> > --- /dev/null
> > +++ b/Documentation/hwmon/ltc4283.rst
> > @@ -0,0 +1,266 @@
> > +.. SPDX-License-Identifier: GPL-2.0-only
> > +
> > +Kernel drivers ltc4283
> > +==========================================
> > +
> > +Supported chips:
> > +
> > + * Analog Devices LTC4283
> > +
> > + Prefix: 'ltc4283'
> > +
> > + Addresses scanned: -
> > +
> > + Datasheet:
> > +
> > +
> > https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4283.pdf
> > +
> > +Author: Nuno Sá <nuno.sa@analog.com>
> > +
> > +Description
> > +___________
> > +
> > +The LTC4283 negative voltage hot swap controller drives an external N-channel
> > +MOSFET to allow a board to be safely inserted and removed from a live backplane.
> > +The device features programmable current limit with foldback and independently
> > +adjustable inrush current to optimize the MOSFET safe operating area (SOA). The
> > +SOA timer limits MOSFET temperature rise for reliable protection against
> > +overstresses. An I2C interface and onboard gear-shift ADC allow monitoring of
> > +board current, voltage, power, energy, and fault status. Additional features
> > +respond to input UV/OV, interrupt the host when a fault has occurred, notify
> > +when output power is good, detect insertion of a board, turn off the MOSFET
> > +if an external supply monitor fails to indicate power good within a timeout
> > +period, and auto-reboot after a programmable delay following a host commanded
> > +turn-off.
> > +
> > +Sysfs entries
> > +_____________
> > +
> > +The following attributes are supported. Limits are read-write and all the other
> > +attributes are read-only. Note that the VADIOx channels might not be available
> > +if the ADIO pins are used as GPIOs (naturally also affects the respective
> > +differential channels).
> > +
> > +======================= ==========================================
> > +in0_lcrit_alarm Critical Undervoltage alarm
> > +in0_crit_alarm Critical Overvoltage alarm
> > +in0_label Channel label (VIN)
> > +
> > +in1_input Output voltage (mV).
> > +in1_min Undervoltage threshold
> > +in1_max Overvoltage threshold
> > +in1_lowest Lowest measured voltage
> > +in1_highest Highest measured voltage
> > +in1_reset_history Write 1 to reset history.
> > +in1_min_alarm Undervoltage alarm
> > +in1_max_alarm Overvoltage alarm
> > +in1_label Channel label (VPWR)
> > +
> > +in2_input Output voltage (mV).
> > +in2_min Undervoltage threshold
> > +in2_max Overvoltage threshold
> > +in2_lowest Lowest measured voltage
> > +in2_highest Highest measured voltage
> > +in2_reset_history Write 1 to reset history.
> > +in2_min_alarm Undervoltage alarm
> > +in2_max_alarm Overvoltage alarm
> > +in2_enable Enable/Disable monitoring.
> > +in2_label Channel label (VADI1)
> > +
> > +in3_input Output voltage (mV).
> > +in3_min Undervoltage threshold
> > +in3_max Overvoltage threshold
> > +in3_lowest Lowest measured voltage
> > +in3_highest Highest measured voltage
> > +in3_reset_history Write 1 to reset history.
> > +in3_min_alarm Undervoltage alarm
> > +in3_max_alarm Overvoltage alarm
> > +in3_enable Enable/Disable monitoring.
> > +in3_label Channel label (VADI2)
> > +
> > +in4_input Output voltage (mV).
> > +in4_min Undervoltage threshold
> > +in4_max Overvoltage threshold
> > +in4_lowest Lowest measured voltage
> > +in4_highest Highest measured voltage
> > +in4_reset_history Write 1 to reset history.
> > +in4_min_alarm Undervoltage alarm
> > +in4_max_alarm Overvoltage alarm
> > +in4_enable Enable/Disable monitoring.
> > +in4_label Channel label (VADI3)
> > +
> > +in5_input Output voltage (mV).
> > +in5_min Undervoltage threshold
> > +in5_max Overvoltage threshold
> > +in5_lowest Lowest measured voltage
> > +in5_highest Highest measured voltage
> > +in5_reset_history Write 1 to reset history.
> > +in5_min_alarm Undervoltage alarm
> > +in5_max_alarm Overvoltage alarm
> > +in5_enable Enable/Disable monitoring.
> > +in5_label Channel label (VADI4)
> > +
> > +in6_input Output voltage (mV).
> > +in6_min Undervoltage threshold
> > +in6_max Overvoltage threshold
> > +in6_lowest Lowest measured voltage
> > +in6_highest Highest measured voltage
> > +in6_reset_history Write 1 to reset history.
> > +in6_min_alarm Undervoltage alarm
> > +in6_max_alarm Overvoltage alarm
> > +in6_enable Enable/Disable monitoring.
> > +in6_label Channel label (VADIO1)
> > +
> > +in7_input Output voltage (mV).
> > +in7_min Undervoltage threshold
> > +in7_max Overvoltage threshold
> > +in7_lowest Lowest measured voltage
> > +in7_highest Highest measured voltage
> > +in7_reset_history Write 1 to reset history.
> > +in7_min_alarm Undervoltage alarm
> > +in7_max_alarm Overvoltage alarm
> > +in7_enable Enable/Disable monitoring.
> > +in7_label Channel label (VADIO2)
> > +
> > +in8_input Output voltage (mV).
> > +in8_min Undervoltage threshold
> > +in8_max Overvoltage threshold
> > +in8_lowest Lowest measured voltage
> > +in8_highest Highest measured voltage
> > +in8_reset_history Write 1 to reset history.
> > +in8_min_alarm Undervoltage alarm
> > +in8_max_alarm Overvoltage alarm
> > +in8_enable Enable/Disable monitoring.
> > +in8_label Channel label (VADIO3)
> > +
> > +in9_input Output voltage (mV).
> > +in9_min Undervoltage threshold
> > +in9_max Overvoltage threshold
> > +in9_lowest Lowest measured voltage
> > +in9_highest Highest measured voltage
> > +in9_reset_history Write 1 to reset history.
> > +in9_min_alarm Undervoltage alarm
> > +in9_max_alarm Overvoltage alarm
> > +in9_enable Enable/Disable monitoring.
> > +in9_label Channel label (VADIO4)
> > +
> > +in10_input Output voltage (mV).
> > +in10_min Undervoltage threshold
> > +in10_max Overvoltage threshold
> > +in10_lowest Lowest measured voltage
> > +in10_highest Highest measured voltage
> > +in10_reset_history Write 1 to reset history.
> > +in10_min_alarm Undervoltage alarm
> > +in10_max_alarm Overvoltage alarm
> > +in10_enable Enable/Disable monitoring.
> > +in10_label Channel label (DRNS)
> > +
> > +in11_input Output voltage (mV).
> > +in11_min Undervoltage threshold
> > +in11_max Overvoltage threshold
> > +in11_lowest Lowest measured voltage
> > +in11_highest Highest measured voltage
> > +in11_reset_history Write 1 to reset history.
> > + Also clears fet bad and short fault logs.
> > +in11_min_alarm Undervoltage alarm
> > +in11_max_alarm Overvoltage alarm
> > +in11_enable Enable/Disable monitoring
> > +in11_fault Failure in the MOSFET. Either bad or shorted FET.
> > +in11_label Channel label (DRAIN)
> > +
> > +in12_input Output voltage (mV).
> > +in12_min Undervoltage threshold
> > +in12_max Overvoltage threshold
> > +in12_lowest Lowest measured voltage
> > +in12_highest Highest measured voltage
> > +in12_reset_history Write 1 to reset history.
> > +in12_min_alarm Undervoltage alarm
> > +in12_max_alarm Overvoltage alarm
> > +in12_enable Enable/Disable monitoring.
> > +in12_label Channel label (ADIN2-ADIN1)
> > +
> > +in13_input Output voltage (mV).
> > +in13_min Undervoltage threshold
> > +in13_max Overvoltage threshold
> > +in13_lowest Lowest measured voltage
> > +in13_highest Highest measured voltage
> > +in13_reset_history Write 1 to reset history.
> > +in13_min_alarm Undervoltage alarm
> > +in13_max_alarm Overvoltage alarm
> > +in13_enable Enable/Disable monitoring.
> > +in13_label Channel label (ADIN4-ADIN3)
> > +
> > +in14_input Output voltage (mV).
> > +in14_min Undervoltage threshold
> > +in14_max Overvoltage threshold
> > +in14_lowest Lowest measured voltage
> > +in14_highest Highest measured voltage
> > +in14_reset_history Write 1 to reset history.
> > +in14_min_alarm Undervoltage alarm
> > +in14_max_alarm Overvoltage alarm
> > +in14_enable Enable/Disable monitoring.
> > +in14_label Channel label (ADIO2-ADIO1)
> > +
> > +in15_input Output voltage (mV).
> > +in15_min Undervoltage threshold
> > +in15_max Overvoltage threshold
> > +in15_lowest Lowest measured voltage
> > +in15_highest Highest measured voltage
> > +in15_reset_history Write 1 to reset history.
> > +in15_min_alarm Undervoltage alarm
> > +in15_max_alarm Overvoltage alarm
> > +in15_enable Enable/Disable monitoring.
> > +in15_label Channel label (ADIO4-ADIO3)
> > +
> > +curr1_input Sense current (mA)
> > +curr1_min Undercurrent threshold
> > +curr1_max Overcurrent threshold
> > +curr1_lowest Lowest measured current
> > +curr1_highest Highest measured current
> > +curr1_reset_history Write 1 to reset curr1 history.
> > + Also clears overcurrent fault logs.
> > +curr1_min_alarm Undercurrent alarm
> > +curr1_max_alarm Overcurrent alarm
> > +curr1_crit_alarm Critical Overcurrent alarm
> > +curr1_label Channel label (ISENSE)
> > +
> > +power1_input Power (in uW)
> > +power1_min Low power threshold
> > +power1_max High power threshold
> > +power1_input_lowest Historical minimum power use
> > +power1_input_highest Historical maximum power use
> > +power1_reset_history Write 1 to reset power1 history.
> > + Also clears power fault logs.
> > +power1_min_alarm Low power alarm
> > +power1_max_alarm High power alarm
> > +power1_label Channel label (Power)
> > +
> > +energy1_input Measured energy over time (in microJoule)
> > +energy1_enable Enable/Disable Energy accumulation
> > +======================= ==========================================
> > +
> > +DebugFs entries
> > +_______________
> > +
> > +The chip also has a fault log register where failures can be logged. Hence,
> > +as these are logging events, we give access to them in debugfs. Note that
> > +even if some failure is detected in these logs, it does necessarily mean
> > +that the failure is still present. As mentioned in the proper Sysfs entries,
> > +these logs can be cleared by writing in the proper reset_history attribute.
> > +
> > +.. warning:: The debugfs interface is subject to change without notice
> > + and is only available when the kernel is compiled with
> > + ``CONFIG_DEBUG_FS`` defined.
> > +
> > +``/sys/kernel/debug/i2c/i2c-[X]/[X]-addr/``
> > +contains the following attributes:
> > +
> > +======================= ========================================
> > ==
> > +power1_failed_fault_log Set to 1 by a power1 fault occurring.
> > +power1_good_input_fault_log Set to 1 by a power1 good input fault occurring
> > at PGIO3.
> > +in11_fet_short_fault_log Set to 1 when a FET-short fault occurs.
> > +in11_fet_bad_fault_log Set to 1 when a FET-BAD fault occurs.
> > +in0_lcrit_fault_log Set to 1 by a VIN undervoltage fault occurring.
> > +in0_crit_fault_log Set to 1 by a VIN overvoltage fault occurring.
> > +curr1_crit_fault_log Set to 1 by an overcurrent fault occurring.
> > +======================= ==========================================
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 3f727d7fdfa4..a63833b6fe8b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -15166,6 +15166,7 @@ M: Nuno Sá <nuno.sa@analog.com>
> > L: linux-hwmon@vger.kernel.org
> > S: Supported
> > F: Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml
> > +F: drivers/hwmon/ltc4283.c
> >
> > LTC4286 HARDWARE MONITOR DRIVER
> > M: Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com>
> > diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
> > index fb847ab40ab4..4d9f500ae6ee 100644
> > --- a/drivers/hwmon/Kconfig
> > +++ b/drivers/hwmon/Kconfig
> > @@ -1157,6 +1157,18 @@ config SENSORS_LTC4282
> > This driver can also be built as a module. If so, the module will
> > be called ltc4282.
> >
> > +config SENSORS_LTC4283
> > + tristate "Analog Devices LTC4283"
> > + depends on I2C
> > + select REGMAP_I2C
> > + select AUXILIARY_BUS
> > + help
> > + If you say yes here you get support for Analog Devices LTC4283
> > + Negative Voltage Hot Swap Controller I2C interface.
> > +
> > + This driver can also be built as a module. If so, the module will
> > + be called ltc4283.
> > +
> > config SENSORS_LTQ_CPUTEMP
> > bool "Lantiq cpu temperature sensor driver"
> > depends on SOC_XWAY
> > diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
> > index 0fce31b43eb1..b9d7b0287b9c 100644
> > --- a/drivers/hwmon/Makefile
> > +++ b/drivers/hwmon/Makefile
> > @@ -147,6 +147,7 @@ obj-$(CONFIG_SENSORS_LTC4245) += ltc4245.o
> > obj-$(CONFIG_SENSORS_LTC4260) += ltc4260.o
> > obj-$(CONFIG_SENSORS_LTC4261) += ltc4261.o
> > obj-$(CONFIG_SENSORS_LTC4282) += ltc4282.o
> > +obj-$(CONFIG_SENSORS_LTC4283) += ltc4283.o
> > obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
> > obj-$(CONFIG_SENSORS_MACSMC_HWMON) += macsmc-hwmon.o
> > obj-$(CONFIG_SENSORS_MAX1111) += max1111.o
> > diff --git a/drivers/hwmon/ltc4283.c b/drivers/hwmon/ltc4283.c
> > new file mode 100644
> > index 000000000000..2a2674a55167
> > --- /dev/null
> > +++ b/drivers/hwmon/ltc4283.c
> > @@ -0,0 +1,1808 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller (HWMON)
> > + *
> > + * Copyright 2025 Analog Devices Inc.
> > + */
> > +#include <linux/auxiliary_bus.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/bitmap.h>
> > +#include <linux/bitops.h>
> > +#include <linux/bits.h>
> > +
> > +#include <linux/debugfs.h>
> > +#include <linux/device.h>
> > +#include <linux/device/devres.h>
> > +#include <linux/hwmon.h>
> > +#include <linux/i2c.h>
> > +#include <linux/math.h>
> > +#include <linux/math64.h>
> > +#include <linux/minmax.h>
> > +#include <linux/module.h>
> > +
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/overflow.h>
> > +#include <linux/property.h>
> > +#include <linux/regmap.h>
> > +#include <linux/unaligned.h>
> > +#include <linux/units.h>
> > +
> > +#define LTC4283_SYSTEM_STATUS 0x00
> > +#define LTC4283_FAULT_STATUS 0x03
> > +#define LTC4283_OV_MASK BIT(0)
> > +#define LTC4283_UV_MASK BIT(1)
> > +#define LTC4283_OC_MASK BIT(2)
> > +#define LTC4283_FET_BAD_MASK BIT(3)
> > +#define LTC4283_FET_SHORT_MASK BIT(6)
> > +#define LTC4283_FAULT_LOG 0x04
> > +#define LTC4283_OV_FAULT_MASK BIT(0)
> > +#define LTC4283_UV_FAULT_MASK BIT(1)
> > +#define LTC4283_OC_FAULT_MASK BIT(2)
> > +#define LTC4283_FET_BAD_FAULT_MASK BIT(3)
> > +#define LTC4283_PGI_FAULT_MASK BIT(4)
> > +#define LTC4283_PWR_FAIL_FAULT_MASK BIT(5)
> > +#define LTC4283_FET_SHORT_FAULT_MASK BIT(6)
> > +#define LTC4283_ADC_ALM_LOG_1 0x05
> > +#define LTC4283_POWER_LOW_ALM BIT(0)
> > +#define LTC4283_POWER_HIGH_ALM BIT(1)
> > +#define LTC4283_SENSE_LOW_ALM BIT(4)
> > +#define LTC4283_SENSE_HIGH_ALM BIT(5)
> > +#define LTC4283_ADC_ALM_LOG_2 0x06
> > +#define LTC4283_ADC_ALM_LOG_3 0x07
> > +#define LTC4283_ADC_ALM_LOG_4 0x08
> > +#define LTC4283_ADC_ALM_LOG_5 0x09
> > +#define LTC4283_CONTROL_1 0x0a
> > +#define LTC4283_RW_PAGE_MASK BIT(0)
> > +#define LTC4283_PIGIO2_ACLB_MASK BIT(2)
> > +#define LTC4283_PWRGD_RST_CTRL_MASK BIT(3)
> > +#define LTC4283_FET_BAD_OFF_MASK BIT(4)
> > +#define LTC4283_THERM_TMR_MASK BIT(5)
> > +#define LTC4283_DVDT_MASK BIT(6)
> > +#define LTC4283_CONTROL_2 0x0b
> > +#define LTC4283_OV_RETRY_MASK BIT(0)
> > +#define LTC4283_UV_RETRY_MASK BIT(1)
> > +#define LTC4283_OC_RETRY_MASK GENMASK(3, 2)
> > +#define LTC4283_FET_BAD_RETRY_MASK GENMASK(5, 4)
> > +#define LTC4283_EXT_FAULT_RETRY_MASK BIT(7)
> > +#define LTC4283_RESERVED_OC 0x0c
> > +#define LTC4283_CONFIG_1 0x0d
> > +#define LTC4283_FB_MASK GENMASK(3, 2)
> > +#define LTC4283_ILIM_MASK GENMASK(7, 4)
> > +#define LTC4283_CONFIG_2 0x0e
> > +#define LTC4283_COOLING_DL_MASK GENMASK(3, 1)
> > +#define LTC4283_FTBD_DL_MASK GENMASK(5, 4)
> > +#define LTC4283_CONFIG_3 0x0f
> > +#define LTC4283_VPWR_DRNS_MASK BIT(6)
> > +#define LTC4283_EXTFLT_TURN_OFF_MASK BIT(7)
> > +#define LTC4283_PGIO_CONFIG 0x10
> > +#define LTC4283_PGIO1_CFG_MASK GENMASK(1, 0)
> > +#define LTC4283_PGIO2_CFG_MASK GENMASK(3, 2)
> > +#define LTC4283_PGIO3_CFG_MASK GENMASK(5, 4)
> > +#define LTC4283_PGIO4_CFG_MASK GENMASK(7, 6)
> > +#define LTC4283_PGIO_CONFIG_2 0x11
> > +#define LTC4283_ADC_MASK GENMASK(2, 0)
> > +#define LTC4283_ADC_SELECT(c) (0x13 + (c) / 8)
> > +#define LTC4283_ADC_SELECT_MASK(c) BIT((c) % 8)
> > +#define LTC4283_SENSE_MIN_TH 0x1b
> > +#define LTC4283_SENSE_MAX_TH 0x1c
> > +#define LTC4283_VPWR_MIN_TH 0x1d
> > +#define LTC4283_VPWR_MAX_TH 0x1e
> > +#define LTC4283_POWER_MIN_TH 0x1f
> > +#define LTC4283_POWER_MAX_TH 0x20
> > +#define LTC4283_ADC_2_MIN_TH(c) (0x21 + (c) * 2)
> > +#define LTC4283_ADC_2_MAX_TH(c) (0x22 + (c) * 2)
> > +#define LTC4283_ADC_2_MIN_TH_DIFF(c) (0x39 + (c) * 2)
> > +#define LTC4283_ADC_2_MAX_TH_DIFF(c) (0x3a + (c) * 2)
> > +#define LTC4283_SENSE 0x41
> > +#define LTC4283_SENSE_MIN 0x42
> > +#define LTC4283_SENSE_MAX 0x43
> > +#define LTC4283_VPWR 0x44
> > +#define LTC4283_VPWR_MIN 0x45
> > +#define LTC4283_VPWR_MAX 0x46
> > +#define LTC4283_POWER 0x47
> > +#define LTC4283_POWER_MIN 0x48
> > +#define LTC4283_POWER_MAX 0x49
> > +#define LTC4283_RESERVED_68 0x68
> > +#define LTC4283_RESERVED_6D 0x6D
> > +/* get channels from ADC 2 */
> > +#define LTC4283_ADC_2(c) (0x4a + (c) * 3)
> > +#define LTC4283_ADC_2_MIN(c) (0x4b + (c) * 3)
> > +#define LTC4283_ADC_2_MAX(c) (0x4c + (c) * 3)
> > +#define LTC4283_ADC_2_DIFF(c) (0x6e + (c) * 3)
> > +#define LTC4283_ADC_2_MIN_DIFF(c) (0x6f + (c) * 3)
> > +#define LTC4283_ADC_2_MAX_DIFF(c) (0x70 + (c) * 3)
> > +#define LTC4283_ENERGY 0x7a
> > +#define LTC4283_METER_CONTROL 0x84
> > +#define LTC4283_INTEGRATE_I_MASK BIT(0)
> > +#define LTC4283_METER_HALT_MASK BIT(6)
> > +#define LTC4283_RESERVED_86 0x86
> > +#define LTC4283_RESERVED_8F 0x8F
> > +#define LTC4283_FAULT_LOG_CTRL 0x90
> > +#define LTC4283_FAULT_LOG_EN_MASK BIT(7)
> > +#define LTC4283_RESERVED_91 0x91
> > +#define LTC4283_RESERVED_A1 0xA1
> > +#define LTC4283_RESERVED_A3 0xA3
> > +#define LTC4283_RESERVED_AC 0xAC
> > +#define LTC4283_POWER_PLAY_MSB 0xE7
> > +#define LTC4283_POWER_PLAY_LSB 0xE8
> > +#define LTC4283_RESERVED_F1 0xF1
> > +#define LTC4283_RESERVED_FF 0xFF
> > +
> > +/* also applies for differential channels */
> > +#define LTC4283_ADC1_FS_uV 32768
> > +#define LTC4283_ADC2_FS_mV 2048
> > +#define LTC4283_TCONV_uS 64103
> > +#define LTC4283_VILIM_MIN_uV 15000
> > +#define LTC4283_VILIM_MAX_uV 30000
> > +#define LTC4283_VILIM_RANGE \
> > + (LTC4283_VILIM_MAX_uV - LTC4283_VILIM_MIN_uV + 1)
> > +
> > +#define LTC4283_PGIO_FUNC_GPIO 2
> > +#define LTC4283_PGIO2_FUNC_ACLB 3
> > +
> > +/*
> > + * Maximum value for rsense in nano ohms. The reasoning for this value is that
> > + * it's the max value for which multiplying by 256 does not overflow long on
> > + * 32bits. For the minimum value, is a sane minimum rsense for which power_max
> > + * does not overflow 32bits.
> > + */
> > +#define LTC4283_MAX_RSENSE 1677721599
> > +#define LTC4283_MIN_RSENSE 50000
> > +
> > +/* voltage channels */
> > +enum {
> > + LTC4283_CHAN_VIN,
> > + LTC4283_CHAN_VPWR,
> > + LTC4283_CHAN_ADI_1,
> > + LTC4283_CHAN_ADI_2,
> > + LTC4283_CHAN_ADI_3,
> > + LTC4283_CHAN_ADI_4,
> > + LTC4283_CHAN_ADIO_1,
> > + LTC4283_CHAN_ADIO_2,
> > + LTC4283_CHAN_ADIO_3,
> > + LTC4283_CHAN_ADIO_4,
> > + LTC4283_CHAN_DRNS,
> > + LTC4283_CHAN_DRAIN,
> > + /* differential channels */
> > + LTC4283_CHAN_ADIN12,
> > + LTC4283_CHAN_ADIN34,
> > + LTC4283_CHAN_ADIO12,
> > + LTC4283_CHAN_ADIO34,
> > + LTC4283_CHAN_MAX
> > +};
> > +
> > +/* Just for ease of use on the regmap */
> > +#define LTC4283_ADIO34_MAX \
> > + LTC4283_ADC_2_MAX_DIFF(LTC4283_CHAN_ADIO34 - LTC4283_CHAN_ADIN12)
> > +
> > +struct ltc4283_hwmon {
> > + struct regmap *map;
> > + struct i2c_client *client;
> > + unsigned long gpio_mask;
> > + unsigned long ch_enable_mask;
> > + /* in microwatt */
> > + long power_max;
> > + /* in millivolt */
> > + u32 vsense_max;
> > + /* in tenths of microohm*/
> > + u32 rsense;
> > + bool energy_en;
> > + bool ext_fault;
> > +};
> > +
> > +static int ltc4283_read_voltage_word(const struct ltc4283_hwmon *st,
> > + u32 reg, u32 fs, long *val)
> > +{
> > + unsigned int __raw;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, reg, &__raw);
> > + if (ret)
> > + return ret;
> > +
> > + *val = DIV_ROUND_CLOSEST(__raw * fs, BIT(16));
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_voltage_byte(const struct ltc4283_hwmon *st,
> > + u32 reg, u32 fs, long *val)
> > +{
> > + int ret;
> > + u32 in;
> > +
> > + ret = regmap_read(st->map, reg, &in);
> > + if (ret)
> > + return ret;
> > +
> > + *val = DIV_ROUND_CLOSEST(in * fs, BIT(8));
> > + return 0;
> > +}
> > +
> > +static u32 ltc4283_in_reg(u32 attr, u32 channel)
> > +{
> > + switch (attr) {
> > + case hwmon_in_input:
> > + if (channel == LTC4283_CHAN_VPWR)
> > + return LTC4283_VPWR;
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <=
> > LTC4283_CHAN_DRAIN)
> > + return LTC4283_ADC_2(channel - LTC4283_CHAN_ADI_1);
> > + return LTC4283_ADC_2_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + case hwmon_in_highest:
> > + if (channel == LTC4283_CHAN_VPWR)
> > + return LTC4283_VPWR_MAX;
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <=
> > LTC4283_CHAN_DRAIN)
> > + return LTC4283_ADC_2_MAX(channel - LTC4283_CHAN_ADI_1);
> > + return LTC4283_ADC_2_MAX_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + case hwmon_in_lowest:
> > + if (channel == LTC4283_CHAN_VPWR)
> > + return LTC4283_VPWR_MIN;
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <=
> > LTC4283_CHAN_DRAIN)
> > + return LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1);
> > + return LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + case hwmon_in_max:
> > + if (channel == LTC4283_CHAN_VPWR)
> > + return LTC4283_VPWR_MAX_TH;
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <=
> > LTC4283_CHAN_DRAIN)
> > + return LTC4283_ADC_2_MAX_TH(channel -
> > LTC4283_CHAN_ADI_1);
> > + return LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + default:
> > + if (channel == LTC4283_CHAN_VPWR)
> > + return LTC4283_VPWR_MIN_TH;
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <=
> > LTC4283_CHAN_DRAIN)
> > + return LTC4283_ADC_2_MIN_TH(channel -
> > LTC4283_CHAN_ADI_1);
> > + return LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + }
> > +}
> > +
> > +static int ltc4283_read_in_vals(const struct ltc4283_hwmon *st,
> > + u32 attr, u32 channel, long *val)
> > +{
> > + u32 reg = ltc4283_in_reg(attr, channel);
> > + int ret;
> > +
> > + if (channel < LTC4283_CHAN_ADIN12) {
> > + if (attr != hwmon_in_max && attr != hwmon_in_min)
> > + return ltc4283_read_voltage_word(st, reg,
> > + LTC4283_ADC2_FS_mV,
> > + val);
> > +
> > + return ltc4283_read_voltage_byte(st, reg,
> > + LTC4283_ADC2_FS_mV, val);
> > + }
> > +
> > + if (attr != hwmon_in_max && attr != hwmon_in_min)
> > + ret = ltc4283_read_voltage_word(st, reg,
> > + LTC4283_ADC1_FS_uV, val);
> > + else
> > + ret = ltc4283_read_voltage_byte(st, reg,
> > + LTC4283_ADC1_FS_uV, val);
> > + if (ret)
> > + return ret;
> > +
> > + *val = DIV_ROUND_CLOSEST(*val, MILLI);
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_alarm(struct ltc4283_hwmon *st, u32 reg,
> > + u32 mask, long *val)
> > +{
> > + u32 alarm;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, reg, &alarm);
> > + if (ret)
> > + return ret;
> > +
> > + *val = !!(alarm & mask);
> > +
> > + /* If not status/fault logs, clear the alarm after reading it. */
> > + if (reg != LTC4283_FAULT_STATUS && reg != LTC4283_FAULT_LOG)
> > + return regmap_clear_bits(st->map, reg, mask);
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_in_alarm(struct ltc4283_hwmon *st, u32 channel,
> > + bool max_alm, long *val)
> > +{
> > + if (channel == LTC4283_VPWR)
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
> > + BIT(2 + max_alm), val);
> > +
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_ADI_4) {
> > + u32 bit = (channel - LTC4283_CHAN_ADI_1) * 2;
> > + /*
> > + * Lower channels go to higher bits. We also want to go +1 down
> > + * in the min_alarm case.
> > + */
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_2,
> > + BIT(7 - bit - !max_alm), val);
> > + }
> > +
> > + if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) {
> > + u32 bit = (channel - LTC4283_CHAN_ADIO_1) * 2;
> > +
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_3,
> > + BIT(7 - bit - !max_alm), val);
> > + }
> > +
> > + if (channel >= LTC4283_CHAN_ADIN12 && channel <= LTC4283_CHAN_ADIO34) {
> > + u32 bit = (channel - LTC4283_CHAN_ADIN12) * 2;
> > +
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_5,
> > + BIT(7 - bit - !max_alm), val);
> > + }
> > +
> > + if (channel == LTC4283_CHAN_DRNS)
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4,
> > + BIT(6 + max_alm), val);
> > +
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4, BIT(4 + max_alm),
> > + val);
> > +}
> > +
> > +static int ltc4283_read_in(struct ltc4283_hwmon *st, u32 attr, u32 channel,
> > + long *val)
> > +{
> > + switch (attr) {
> > + case hwmon_in_input:
> > + if (!test_bit(channel, &st->ch_enable_mask))
> > + return -ENODATA;
> > +
> > + return ltc4283_read_in_vals(st, attr, channel, val);
> > + case hwmon_in_highest:
> > + case hwmon_in_lowest:
> > + case hwmon_in_max:
> > + case hwmon_in_min:
> > + return ltc4283_read_in_vals(st, attr, channel, val);
> > + case hwmon_in_max_alarm:
> > + return ltc4283_read_in_alarm(st, channel, true, val);
> > + case hwmon_in_min_alarm:
> > + return ltc4283_read_in_alarm(st, channel, false, val);
> > + case hwmon_in_crit_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
> > + LTC4283_OV_MASK, val);
> > + case hwmon_in_lcrit_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
> > + LTC4283_UV_MASK, val);
> > + case hwmon_in_fault:
> > + /*
> > + * We report failure if we detect either a fer_bad or a
> > + * fet_short in the status register.
> > + */
> > + return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
> > + LTC4283_FET_BAD_MASK |
> > LTC4283_FET_SHORT_MASK, val);
> > + case hwmon_in_enable:
> > + *val = test_bit(channel, &st->ch_enable_mask);
> > + return 0;
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_current_word(const struct ltc4283_hwmon *st, u32 reg,
> > + long *val)
> > +{
> > + u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI;
> > + unsigned int __raw;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, reg, &__raw);
> > + if (ret)
> > + return ret;
> > +
> > + *val = DIV64_U64_ROUND_CLOSEST(__raw * temp,
> > + BIT_ULL(16) * st->rsense);
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_current_byte(const struct ltc4283_hwmon *st, u32 reg,
> > + long *val)
> > +{
> > + u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI;
> > + u32 curr;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, reg, &curr);
> > + if (ret)
> > + return ret;
> > +
> > + *val = DIV_ROUND_CLOSEST_ULL(curr * temp, BIT(8) * st->rsense);
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_curr(struct ltc4283_hwmon *st, u32 attr, long *val)
> > +{
> > + switch (attr) {
> > + case hwmon_curr_input:
> > + return ltc4283_read_current_word(st, LTC4283_SENSE, val);
> > + case hwmon_curr_highest:
> > + return ltc4283_read_current_word(st, LTC4283_SENSE_MAX, val);
> > + case hwmon_curr_lowest:
> > + return ltc4283_read_current_word(st, LTC4283_SENSE_MIN, val);
> > + case hwmon_curr_max:
> > + return ltc4283_read_current_byte(st, LTC4283_SENSE_MAX_TH, val);
> > + case hwmon_curr_min:
> > + return ltc4283_read_current_byte(st, LTC4283_SENSE_MIN_TH, val);
> > + case hwmon_curr_max_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
> > + LTC4283_SENSE_HIGH_ALM, val);
> > + case hwmon_curr_min_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
> > + LTC4283_SENSE_LOW_ALM, val);
> > + case hwmon_curr_crit_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
> > + LTC4283_OC_MASK, val);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static int ltc4283_read_power_word(const struct ltc4283_hwmon *st,
> > + u32 reg, long *val)
> > +{
> > + u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> > + unsigned int __raw;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, reg, &__raw);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * Power is given by:
> > + * P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense)
> > + */
> > + *val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense);
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_power_byte(const struct ltc4283_hwmon *st,
> > + u32 reg, long *val)
> > +{
> > + u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> > + u32 power;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, reg, &power);
> > + if (ret)
> > + return ret;
> > +
> > + *val = DIV_ROUND_CLOSEST_ULL(power * temp, BIT(8) * st->rsense);
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read_power(struct ltc4283_hwmon *st, u32 attr, long *val)
> > +{
> > + switch (attr) {
> > + case hwmon_power_input:
> > + return ltc4283_read_power_word(st, LTC4283_POWER, val);
> > + case hwmon_power_input_highest:
> > + return ltc4283_read_power_word(st, LTC4283_POWER_MAX, val);
> > + case hwmon_power_input_lowest:
> > + return ltc4283_read_power_word(st, LTC4283_POWER_MIN, val);
> > + case hwmon_power_max_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
> > + LTC4283_POWER_HIGH_ALM, val);
> > + case hwmon_power_min_alarm:
> > + return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
> > + LTC4283_POWER_LOW_ALM, val);
> > + case hwmon_power_max:
> > + return ltc4283_read_power_byte(st, LTC4283_POWER_MAX_TH, val);
> > + case hwmon_power_min:
> > + return ltc4283_read_power_byte(st, LTC4283_POWER_MIN_TH, val);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static int ltc4283_read_energy(struct ltc4283_hwmon *st, u32 attr, s64 *val)
> > +{
> > + u64 temp = LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV, energy, temp_2;
> > + u8 raw[8] = {};
> > + int ret;
> > +
> > + if (!st->energy_en)
> > + return -ENODATA;
> > +
> > + ret = i2c_smbus_read_i2c_block_data(st->client, LTC4283_ENERGY, 6, raw);
> > + if (ret < 0)
> > + return ret;
> > + if (ret != 6)
> > + return -EIO;
> > +
> > + energy = get_unaligned_be64(raw) >> 16;
> > +
> > + /*
> > + * The formula for energy is given by:
> > + * E = CODE(48b) * 32.768mV * 2.048V * Tconv / 2^24 * Rsense
> > + *
> > + * As Rsense can have tenths of micro-ohm resolution, we need to
> > + * multiply by DECA to get microjoule.
> > + */
> > + if (check_mul_overflow(temp * LTC4283_TCONV_uS, energy, &temp_2)) {
> > + /*
> > + * We multiply again by 1000 to make sure that we don't get 0
> > + * in the following division which could happen for big rsense
> > + * values. OTOH, we then divide energy first by 1000 so that
> > + * we do not overflow u64 again for very small rsense values.
> > + * We add 100 factor for proper conversion to microjoule.
> > + */
> > + temp_2 = DIV64_U64_ROUND_CLOSEST(temp * LTC4283_TCONV_uS *
> > MILLI,
> > + BIT_ULL(24) * st->rsense);
> > + energy = DIV_ROUND_CLOSEST_ULL(energy, MILLI * CENTI) * temp_2;
> > + } else {
> > + /* Put rsense back into nanoohm so we get microjoule. */
> > + energy = DIV64_U64_ROUND_CLOSEST(temp_2, BIT_ULL(24) * st-
> > >rsense * CENTI);
> > + }
> > +
> > + *val = energy;
> > + return 0;
> > +}
> > +
> > +static int ltc4283_read(struct device *dev, enum hwmon_sensor_types type,
> > + u32 attr, int channel, long *val)
> > +{
> > + struct ltc4283_hwmon *st = dev_get_drvdata(dev);
> > +
> > + switch (type) {
> > + case hwmon_in:
> > + return ltc4283_read_in(st, attr, channel, val);
> > + case hwmon_curr:
> > + return ltc4283_read_curr(st, attr, val);
> > + case hwmon_power:
> > + return ltc4283_read_power(st, attr, val);
> > + case hwmon_energy:
> > + *val = st->energy_en;
> > + return 0;
> > + case hwmon_energy64:
> > + return ltc4283_read_energy(st, attr, (s64 *)val);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static int ltc4283_write_power_byte(const struct ltc4283_hwmon *st, u32 reg,
> > + long val)
> > +{
> > + u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> > + u32 __raw;
> > +
> > + val = clamp_val(val, 0, st->power_max);
> > + __raw = DIV64_U64_ROUND_CLOSEST(val * BIT_ULL(8) * st->rsense, temp);
> > +
> > + return regmap_write(st->map, reg, __raw);
> > +}
> > +
> > +static int ltc4283_write_power_word(const struct ltc4283_hwmon *st,
> > + u32 reg, long val)
> > +{
> > + u64 temp = st->rsense * BIT_ULL(16), temp_2;
> > + u16 __raw;
> > +
> > + if (check_mul_overflow(val, temp, &temp_2)) {
> > + temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MILLI);
> > + __raw = DIV_ROUND_CLOSEST_ULL(temp * val, LTC4283_ADC1_FS_uV *
> > LTC4283_ADC2_FS_mV);
> > + } else {
> > + temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA *
> > MILLI;
> > + __raw = DIV64_U64_ROUND_CLOSEST(temp_2, temp);
> > + }
> > +
> > + return regmap_write(st->map, reg, __raw);
> > +}
> > +
> > +static int ltc4283_reset_power_hist(struct ltc4283_hwmon *st)
> > +{
> > + int ret;
> > +
> > + ret = ltc4283_write_power_word(st, LTC4283_POWER_MIN, st->power_max);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ltc4283_write_power_word(st, LTC4283_POWER_MAX, 0);
> > + if (ret)
> > + return ret;
> > +
> > + /* Clear possible power faults. */
> > + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
> > + LTC4283_PWR_FAIL_FAULT_MASK |
> > LTC4283_PGI_FAULT_MASK);
> > +}
> > +
> > +static int ltc4283_write_power(struct ltc4283_hwmon *st, u32 attr, long val)
> > +{
> > + switch (attr) {
> > + case hwmon_power_max:
> > + return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, val);
> > + case hwmon_power_min:
> > + return ltc4283_write_power_byte(st, LTC4283_POWER_MIN_TH, val);
> > + case hwmon_power_reset_history:
> > + return ltc4283_reset_power_hist(st);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static int ltc4283_write_in_history(struct ltc4283_hwmon *st, u32 reg,
> > + long lowest, u32 fs)
> > +{
> > + u32 __raw;
> > + int ret;
> > +
> > + __raw = DIV_ROUND_CLOSEST(BIT(16) * lowest, fs);
> > + if (__raw == BIT(16))
> > + __raw = U16_MAX;
> > +
> > + ret = regmap_write(st->map, reg, __raw);
> > + if (ret)
> > + return ret;
> > +
> > + return regmap_write(st->map, reg + 1, 0);
> > +}
> > +
> > +static int ltc4283_write_in_byte(const struct ltc4283_hwmon *st,
> > + u32 reg, u32 fs, long val)
> > +{
> > + u32 __raw;
> > +
> > + val = clamp_val(val, 0, fs);
> > + __raw = DIV_ROUND_CLOSEST(val * BIT(8), fs);
> > + if (__raw == BIT(8))
> > + __raw = U8_MAX;
> > +
> > + return regmap_write(st->map, reg, __raw);
> > +}
> > +
> > +static int ltc4283_reset_in_hist(struct ltc4283_hwmon *st, u32 channel)
> > +{
> > + u32 reg, fs;
> > + int ret;
> > +
> > + /*
> > + * Make sure to clear possible under/over voltage faults. Otherwise the
> > + * chip won't latch on again.
> > + */
> > + if (channel == LTC4283_CHAN_VIN)
> > + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
> > + LTC4283_OV_FAULT_MASK |
> > LTC4283_UV_FAULT_MASK);
> > +
> > + if (channel == LTC4283_CHAN_VPWR)
> > + return ltc4283_write_in_history(st, LTC4283_VPWR_MIN,
> > + LTC4283_ADC2_FS_mV,
> > + LTC4283_ADC2_FS_mV);
> > +
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) {
> > + fs = LTC4283_ADC2_FS_mV;
> > + reg = LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1);
> > + } else {
> > + fs = LTC4283_ADC1_FS_uV;
> > + reg = LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + }
> > +
> > + ret = ltc4283_write_in_history(st, reg, fs, fs);
> > + if (ret)
> > + return ret;
> > + if (channel != LTC4283_CHAN_DRAIN)
> > + return 0;
> > +
> > + /* Then, let's also clear possible fet faults. Same as above. */
> > + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
> > + LTC4283_FET_BAD_FAULT_MASK |
> > LTC4283_FET_SHORT_FAULT_MASK);
> > +}
> > +
> > +static int ltc4283_write_in_en(struct ltc4283_hwmon *st, u32 channel, bool en)
> > +{
> > + unsigned int bit, adc_idx = channel - LTC4283_CHAN_ADI_1;
> > + unsigned int reg = LTC4283_ADC_SELECT(adc_idx);
> > + int ret;
> > +
> > + bit = LTC4283_ADC_SELECT_MASK(adc_idx);
> > + if (channel > LTC4283_CHAN_DRAIN)
> > + /* Account for two reserved fields after DRAIN. */
> > + bit <<= 2;
> > +
> > + if (en)
> > + ret = regmap_set_bits(st->map, reg, bit);
> > + else
> > + ret = regmap_clear_bits(st->map, reg, bit);
> > + if (ret)
> > + return ret;
> > +
> > + __assign_bit(channel, &st->ch_enable_mask, en);
> > + return 0;
> > +}
> > +
> > +static int ltc4283_write_minmax(struct ltc4283_hwmon *st, long val,
> > + u32 channel, bool is_max)
> > +{
> > + u32 reg;
> > +
> > + if (channel == LTC4283_CHAN_VPWR) {
> > + if (is_max)
> > + return ltc4283_write_in_byte(st, LTC4283_VPWR_MAX_TH,
> > + LTC4283_ADC2_FS_mV, val);
> > +
> > + return ltc4283_write_in_byte(st, LTC4283_VPWR_MIN_TH,
> > + LTC4283_ADC2_FS_mV, val);
> > + }
> > +
> > + if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) {
> > + if (is_max) {
> > + reg = LTC4283_ADC_2_MAX_TH(channel -
> > LTC4283_CHAN_ADI_1);
> > + return ltc4283_write_in_byte(st, reg,
> > + LTC4283_ADC2_FS_mV, val);
> > + }
> > +
> > + reg = LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1);
> > + return ltc4283_write_in_byte(st, reg, LTC4283_ADC2_FS_mV, val);
> > + }
> > +
> > + /* Just sanity check we do not overflow val for 32bit */
> > + val = clamp_val(val * MILLI, 0, LTC4283_ADC1_FS_uV);
> > +
> > + if (is_max) {
> > + reg = LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, val);
> > + }
> > +
> > + reg = LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
> > + return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, val);
> > +}
> > +
> > +static int ltc4283_write_in(struct ltc4283_hwmon *st, u32 attr, long val,
> > + int channel)
> > +{
> > + switch (attr) {
> > + case hwmon_in_max:
> > + return ltc4283_write_minmax(st, val, channel, true);
> > + case hwmon_in_min:
> > + return ltc4283_write_minmax(st, val, channel, false);
> > + case hwmon_in_reset_history:
> > + return ltc4283_reset_in_hist(st, channel);
> > + case hwmon_in_enable:
> > + return ltc4283_write_in_en(st, channel, !!val);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static int ltc4283_write_curr_byte(const struct ltc4283_hwmon *st,
> > + u32 reg, long val)
> > +{
> > + u32 temp = LTC4283_ADC1_FS_uV * DECA * MILLI;
> > + u32 reg_val, isense_max;
> > +
> > + isense_max = DIV_ROUND_CLOSEST(st->vsense_max * MICRO * DECA, st-
> > >rsense);
> > + val = clamp_val(val, 0, isense_max);
> > + reg_val = DIV_ROUND_CLOSEST_ULL(val * BIT_ULL(8) * st->rsense, temp);
> > +
> > + return regmap_write(st->map, reg, reg_val);
> > +}
> > +
> > +static int ltc4283_write_curr_history(struct ltc4283_hwmon *st)
> > +{
> > + int ret;
> > +
> > + ret = ltc4283_write_in_history(st, LTC4283_SENSE_MIN,
> > + st->vsense_max * MILLI,
> > + LTC4283_ADC1_FS_uV);
> > + if (ret)
> > + return ret;
> > +
> > + /* Now, let's also clear possible overcurrent logs. */
> > + return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
> > + LTC4283_OC_FAULT_MASK);
> > +}
> > +
> > +static int ltc4283_write_curr(struct ltc4283_hwmon *st, u32 attr, long val)
> > +{
> > + switch (attr) {
> > + case hwmon_curr_max:
> > + return ltc4283_write_curr_byte(st, LTC4283_SENSE_MAX_TH, val);
> > + case hwmon_curr_min:
> > + return ltc4283_write_curr_byte(st, LTC4283_SENSE_MIN_TH, val);
> > + case hwmon_curr_reset_history:
> > + return ltc4283_write_curr_history(st);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static int ltc4283_energy_enable_set(struct ltc4283_hwmon *st, long val)
> > +{
> > + int ret;
> > +
> > + /* Setting the bit halts the meter. */
> > + val = !!val;
> > + ret = regmap_update_bits(st->map, LTC4283_METER_CONTROL,
> > + LTC4283_METER_HALT_MASK,
> > + FIELD_PREP(LTC4283_METER_HALT_MASK, !val));
> > + if (ret)
> > + return ret;
> > +
> > + st->energy_en = val;
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_write(struct device *dev, enum hwmon_sensor_types type,
> > + u32 attr, int channel, long val)
> > +{
> > + struct ltc4283_hwmon *st = dev_get_drvdata(dev);
> > +
> > + switch (type) {
> > + case hwmon_power:
> > + return ltc4283_write_power(st, attr, val);
> > + case hwmon_in:
> > + return ltc4283_write_in(st, attr, val, channel);
> > + case hwmon_curr:
> > + return ltc4283_write_curr(st, attr, val);
> > + case hwmon_energy:
> > + return ltc4283_energy_enable_set(st, val);
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +static umode_t ltc4283_in_is_visible(const struct ltc4283_hwmon *st,
> > + u32 attr, int channel)
> > +{
> > + /* If ADIO is set as a GPIO, don´t make it visible. */
> > + if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) {
> > + /* ADIOX pins come at index 0 in the gpio mask. */
> > + channel -= LTC4283_CHAN_ADIO_1;
> > + if (test_bit(channel, &st->gpio_mask))
> > + return 0;
> > + }
> > +
> > + /* Also take care of differential channels. */
> > + if (channel >= LTC4283_CHAN_ADIO12 && channel <= LTC4283_CHAN_ADIO34) {
> > + channel -= LTC4283_CHAN_ADIO12;
> > + /* If one channel in the pair is used, make it invisible. */
> > + if (test_bit(channel * 2, &st->gpio_mask) ||
> > + test_bit(channel * 2 + 1, &st->gpio_mask))
> > + return 0;
> > + }
> > +
> > + switch (attr) {
> > + case hwmon_in_input:
> > + case hwmon_in_highest:
> > + case hwmon_in_lowest:
> > + case hwmon_in_max_alarm:
> > + case hwmon_in_min_alarm:
> > + case hwmon_in_label:
> > + case hwmon_in_lcrit_alarm:
> > + case hwmon_in_crit_alarm:
> > + case hwmon_in_fault:
> > + return 0444;
> > + case hwmon_in_max:
> > + case hwmon_in_min:
> > + case hwmon_in_enable:
> > + return 0644;
> > + case hwmon_in_reset_history:
> > + return 0200;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > +static umode_t ltc4283_curr_is_visible(u32 attr)
> > +{
> > + switch (attr) {
> > + case hwmon_curr_input:
> > + case hwmon_curr_highest:
> > + case hwmon_curr_lowest:
> > + case hwmon_curr_max_alarm:
> > + case hwmon_curr_min_alarm:
> > + case hwmon_curr_crit_alarm:
> > + case hwmon_curr_label:
> > + return 0444;
> > + case hwmon_curr_max:
> > + case hwmon_curr_min:
> > + return 0644;
> > + case hwmon_curr_reset_history:
> > + return 0200;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > +static umode_t ltc4283_power_is_visible(u32 attr)
> > +{
> > + switch (attr) {
> > + case hwmon_power_input:
> > + case hwmon_power_input_highest:
> > + case hwmon_power_input_lowest:
> > + case hwmon_power_label:
> > + case hwmon_power_max_alarm:
> > + case hwmon_power_min_alarm:
> > + return 0444;
> > + case hwmon_power_max:
> > + case hwmon_power_min:
> > + return 0644;
> > + case hwmon_power_reset_history:
> > + return 0200;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > +static umode_t ltc4283_is_visible(const void *data,
> > + enum hwmon_sensor_types type,
> > + u32 attr, int channel)
> > +{
> > + switch (type) {
> > + case hwmon_in:
> > + return ltc4283_in_is_visible(data, attr, channel);
> > + case hwmon_curr:
> > + return ltc4283_curr_is_visible(attr);
> > + case hwmon_power:
> > + return ltc4283_power_is_visible(attr);
> > + case hwmon_energy:
> > + /* hwmon_energy_enable */
> > + return 0644;
> > + case hwmon_energy64:
> > + /* hwmon_energy_input */
> > + return 0444;
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > +static const char * const ltc4283_in_strs[] = {
> > + "VIN", "VPWR", "VADI1", "VADI2", "VADI3", "VADI4", "VADIO1", "VADIO2",
> > + "VADIO3", "VADIO4", "DRNS", "DRAIN", "ADIN2-ADIN1", "ADIN4-ADIN3",
> > + "ADIO2-ADIO1", "ADIO4-ADIO3"
> > +};
> > +
> > +static int ltc4283_read_labels(struct device *dev,
> > + enum hwmon_sensor_types type,
> > + u32 attr, int channel, const char **str)
> > +{
> > + switch (type) {
> > + case hwmon_in:
> > + *str = ltc4283_in_strs[channel];
> > + return 0;
> > + case hwmon_curr:
> > + *str = "ISENSE";
> > + return 0;
> > + case hwmon_power:
> > + *str = "Power";
> > + return 0;
> > + default:
> > + return -EOPNOTSUPP;
> > + }
> > +}
> > +
> > +/*
> > + * Set max limits for ISENSE and Power as that depends on the max voltage on
> > + * rsense that is defined in ILIM_ADJUST. This is specially important for power
> > + * because for some rsense and vfsout values, if we allow the default raw 255
> > + * value, that would overflow long in 32bit archs when reading back the max
> > + * power limit.
> > + */
> > +static int ltc4283_set_max_limits(struct ltc4283_hwmon *st, struct device *dev)
> > +{
> > + u32 temp = st->vsense_max * DECA * MICRO;
> > + int ret;
> > +
> > + ret = ltc4283_write_in_byte(st, LTC4283_SENSE_MAX_TH,
> > LTC4283_ADC1_FS_uV,
> > + st->vsense_max * MILLI);
> > + if (ret)
> > + return ret;
> > +
> > + /* Power is given by ISENSE * Vout. */
> > + st->power_max = DIV_ROUND_CLOSEST(temp, st->rsense) *
> > LTC4283_ADC2_FS_mV;
> > + return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, st-
> > >power_max);
> > +}
> > +
> > +static int ltc4283_parse_array_prop(const struct ltc4283_hwmon *st,
> > + struct device *dev, const char *prop,
> > + const u32 *vals, u32 n_vals)
> > +{
> > + u32 prop_val;
> > + int ret;
> > + u32 i;
> > +
> > + ret = device_property_read_u32(dev, prop, &prop_val);
> > + if (ret)
> > + return n_vals;
> > +
> > + for (i = 0; i < n_vals; i++) {
> > + if (prop_val != vals[i])
> > + continue;
> > +
> > + return i;
> > + }
> > +
> > + return dev_err_probe(dev, -EINVAL,
> > + "Invalid %s property value %u, expected one of:
> > %*ph\n",
> > + prop, prop_val, n_vals, vals);
> > +}
> > +
> > +static int ltc4283_get_defaults(struct ltc4283_hwmon *st)
> > +{
> > + u32 reg_val, ilm_adjust, c;
> > + int ret;
> > +
> > + ret = regmap_read(st->map, LTC4283_METER_CONTROL, ®_val);
> > + if (ret)
> > + return ret;
> > +
> > + st->energy_en = !FIELD_GET(LTC4283_METER_HALT_MASK, reg_val);
> > +
> > + ret = regmap_read(st->map, LTC4283_CONFIG_1, ®_val);
> > + if (ret)
> > + return ret;
> > +
> > + ilm_adjust = FIELD_GET(LTC4283_ILIM_MASK, reg_val);
> > + st->vsense_max = LTC4283_VILIM_MIN_uV / MILLI + ilm_adjust;
> > +
> > + ret = regmap_read(st->map, LTC4283_PGIO_CONFIG, ®_val);
> > + if (ret)
> > + return ret;
> > +
> > + /* Can be latter overwritten in ltc4283_pgio_config() */
> > + if (FIELD_GET(LTC4283_PGIO4_CFG_MASK, reg_val) < LTC4283_PGIO_FUNC_GPIO)
> > + st->ext_fault = true;
> > +
> > + /* VPWR and VIN are always enabled */
> > + __set_bit(LTC4283_CHAN_VIN, &st->ch_enable_mask);
> > + __set_bit(LTC4283_CHAN_VPWR, &st->ch_enable_mask);
> > + for (c = LTC4283_CHAN_ADI_1; c < LTC4283_CHAN_MAX; c++) {
> > + u32 chan = c - LTC4283_CHAN_ADI_1, bit;
> > +
> > + ret = regmap_read(st->map, LTC4283_ADC_SELECT(chan), ®_val);
> > + if (ret)
> > + return ret;
> > +
> > + bit = LTC4283_ADC_SELECT_MASK(chan);
> > + if (c > LTC4283_CHAN_DRAIN)
> > + /* account for two reserved fields after DRAIN */
> > + bit <<= 2;
> > +
> > + if (!(bit & reg_val))
> > + continue;
> > +
> > + __set_bit(c, &st->ch_enable_mask);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const char * const ltc4283_pgio1_funcs[] = {
> > + "inverted_power_good", "power_good", "gpio"
> > +};
> > +
> > +static const char * const ltc4283_pgio2_funcs[] = {
> > + "inverted_power_good", "power_good", "gpio", "active_current_limiting"
> > +};
> > +
> > +static const char * const ltc4283_pgio3_funcs[] = {
> > + "inverted_power_good_input", "power_good_input", "gpio"
> > +};
> > +
> > +static const char * const ltc4283_pgio4_funcs[] = {
> > + "inverted_external_fault", "external_fault", "gpio"
> > +};
> > +
> > +enum {
> > + LTC4283_PIN_ADIO1,
> > + LTC4283_PIN_ADIO2,
> > + LTC4283_PIN_ADIO3,
> > + LTC4283_PIN_ADIO4,
> > + LTC4283_PIN_PGIO1,
> > + LTC4283_PIN_PGIO2,
> > + LTC4283_PIN_PGIO3,
> > + LTC4283_PIN_PGIO4,
> > +};
> > +
> > +static int ltc4283_pgio_config(struct ltc4283_hwmon *st, struct device *dev)
> > +{
> > + int ret, func;
> > +
> > + func = device_property_match_property_string(dev, "adi,pgio1-func",
> > + ltc4283_pgio1_funcs,
> > +
> > ARRAY_SIZE(ltc4283_pgio1_funcs));
> > + if (func < 0 && func != -EINVAL)
> > + return dev_err_probe(dev, func,
> > + "Invalid adi,pgio1-func property\n");
> > + if (func >= 0) {
> > + if (func == LTC4283_PGIO_FUNC_GPIO) {
> > + __set_bit(LTC4283_PIN_PGIO1, &st->gpio_mask);
> > + /* If GPIO, default to an input pin. */
> > + func++;
> > + }
> > +
> > + ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
> > + LTC4283_PGIO1_CFG_MASK,
> > + FIELD_PREP(LTC4283_PGIO1_CFG_MASK,
> > func));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + func = device_property_match_property_string(dev, "adi,pgio2-func",
> > + ltc4283_pgio2_funcs,
> > +
> > ARRAY_SIZE(ltc4283_pgio2_funcs));
> > +
> > + if (func < 0 && func != -EINVAL)
> > + return dev_err_probe(dev, func,
> > + "Invalid adi,pgio2-func property\n");
> > + if (func >= 0) {
> > + if (func != LTC4283_PGIO2_FUNC_ACLB) {
> > + if (func == LTC4283_PGIO_FUNC_GPIO) {
> > + __set_bit(LTC4283_PIN_PGIO2, &st->gpio_mask);
> > + func++;
> > + }
> > +
> > + ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
> > + LTC4283_PGIO2_CFG_MASK,
> > +
> > FIELD_PREP(LTC4283_PGIO2_CFG_MASK, func));
> > + } else {
> > + ret = regmap_set_bits(st->map, LTC4283_CONTROL_1,
> > + LTC4283_PIGIO2_ACLB_MASK);
> > + }
> > +
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + func = device_property_match_property_string(dev, "adi,pgio3-func",
> > + ltc4283_pgio3_funcs,
> > +
> > ARRAY_SIZE(ltc4283_pgio3_funcs));
> > +
> > + if (func < 0 && func != -EINVAL)
> > + return dev_err_probe(dev, func,
> > + "Invalid adi,pgio3-func property\n");
> > + if (func >= 0) {
> > + if (func == LTC4283_PGIO_FUNC_GPIO) {
> > + __set_bit(LTC4283_PIN_PGIO3, &st->gpio_mask);
> > + func++;
> > + }
> > +
> > + ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
> > + LTC4283_PGIO3_CFG_MASK,
> > + FIELD_PREP(LTC4283_PGIO3_CFG_MASK,
> > func));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + func = device_property_match_property_string(dev, "adi,pgio4-func",
> > + ltc4283_pgio4_funcs,
> > +
> > ARRAY_SIZE(ltc4283_pgio4_funcs));
> > +
> > + if (func < 0 && func != -EINVAL)
> > + return dev_err_probe(dev, func,
> > + "Invalid adi,pgio4-func property\n");
> > + if (func >= 0) {
> > + if (func == LTC4283_PGIO_FUNC_GPIO) {
> > + __set_bit(LTC4283_PIN_PGIO4, &st->gpio_mask);
> > + func++;
> > + st->ext_fault = false;
> > + } else {
> > + st->ext_fault = true;
> > + }
> > +
> > + ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
> > + LTC4283_PGIO4_CFG_MASK,
> > + FIELD_PREP(LTC4283_PGIO4_CFG_MASK,
> > func));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_adio_config(struct ltc4283_hwmon *st, struct device *dev,
> > + const char *prop, u32 pin)
> > +{
> > + u32 adc_idx;
> > + int ret;
> > +
> > + if (!device_property_read_bool(dev, prop))
> > + return 0;
> > +
> > + adc_idx = LTC4283_CHAN_ADIO_1 - LTC4283_CHAN_ADI_1 + pin;
> > + ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(adc_idx),
> > + LTC4283_ADC_SELECT_MASK(adc_idx));
> > + if (ret)
> > + return ret;
> > +
> > + __set_bit(pin, &st->gpio_mask);
> > + return 0;
> > +}
> > +
> > +static int ltc4283_pin_config(struct ltc4283_hwmon *st, struct device *dev)
> > +{
> > + int ret;
> > +
> > + ret = ltc4283_pgio_config(st, dev);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio1",
> > LTC4283_PIN_ADIO1);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio2",
> > LTC4283_PIN_ADIO2);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio3",
> > LTC4283_PIN_ADIO3);
> > + if (ret)
> > + return ret;
> > +
> > + return ltc4283_adio_config(st, dev, "adi,gpio-on-adio4",
> > LTC4283_PIN_ADIO4);
> > +}
> > +
> > +static const char * const ltc4283_oc_fet_retry[] = {
> > + "latch-off", "1", "7", "unlimited"
> > +};
> > +
> > +static const u32 ltc4283_fb_factor[] = {
> > + 100, 50, 20, 10
> > +};
> > +
> > +static const u32 ltc4283_cooling_dl[] = {
> > + 512, 1002, 2005, 4100, 8190, 16400, 32800, 65600
> > +};
> > +
> > +static const u32 ltc4283_fet_bad_delay[] = {
> > + 256, 512, 1002, 2005
> > +};
> > +
> > +static int ltc4283_setup(struct ltc4283_hwmon *st, struct device *dev)
> > +{
> > + u32 val;
> > + int ret;
> > +
> > + /* The part has an eeprom so let's get the needed defaults from it */
> > + ret = ltc4283_get_defaults(st);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * Default to LTC4283_MIN_RSENSE so we can probe without FW properties.
> > + */
> > + st->rsense = LTC4283_MIN_RSENSE;
> > + ret = device_property_read_u32(dev, "adi,rsense-nano-ohms",
> > + &st->rsense);
> > + if (!ret) {
> > + if (st->rsense < LTC4283_MIN_RSENSE || st->rsense >
> > LTC4283_MAX_RSENSE)
> > + return dev_err_probe(dev, -EINVAL,
> > + "adi,rsense-nano-ohms(%u) too small
> > or too large [%u %u]\n",
> > + st->rsense, LTC4283_MIN_RSENSE,
> > LTC4283_MAX_RSENSE);
> > + }
> > +
> > + /*
> > + * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which
> > + * means we need nano in the bindings. However, to make things easier to
> > + * handle (with respect to overflows) we divide it by 100 as we don't
> > + * really need the last two digits.
> > + */
> > + st->rsense /= CENTI;
> > +
> > + ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt",
> > + &st->vsense_max);
> > + if (!ret) {
> > + u32 reg_val;
> > +
> > + if (!in_range(st->vsense_max, LTC4283_VILIM_MIN_uV,
> > + LTC4283_VILIM_RANGE)) {
> > + return dev_err_probe(dev, -EINVAL,
> > + "adi,current-limit-sense-microvolt
> > (%u) out of range [%u %u]\n",
> > + st->vsense_max,
> > LTC4283_VILIM_MIN_uV,
> > + LTC4283_VILIM_MAX_uV);
> > + }
> > +
> > + st->vsense_max /= MILLI;
> > + reg_val = FIELD_PREP(LTC4283_ILIM_MASK,
> > + st->vsense_max - LTC4283_VILIM_MIN_uV /
> > MILLI);
> > + ret = regmap_update_bits(st->map, LTC4283_CONFIG_1,
> > + LTC4283_ILIM_MASK, reg_val);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = ltc4283_parse_array_prop(st, dev, "adi,current-limit-foldback-
> > factor",
> > + ltc4283_fb_factor,
> > ARRAY_SIZE(ltc4283_fb_factor));
> > + if (ret < 0)
> > + return ret;
> > + if (ret < ARRAY_SIZE(ltc4283_fb_factor)) {
> > + ret = regmap_update_bits(st->map, LTC4283_CONFIG_1,
> > LTC4283_FB_MASK,
> > + FIELD_PREP(LTC4283_FB_MASK, ret));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = ltc4283_parse_array_prop(st, dev, "adi,cooling-delay-ms",
> > + ltc4283_cooling_dl,
> > ARRAY_SIZE(ltc4283_cooling_dl));
> > + if (ret < 0)
> > + return ret;
> > + if (ret < ARRAY_SIZE(ltc4283_cooling_dl)) {
> > + ret = regmap_update_bits(st->map, LTC4283_CONFIG_2,
> > LTC4283_COOLING_DL_MASK,
> > + FIELD_PREP(LTC4283_COOLING_DL_MASK,
> > ret));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = ltc4283_parse_array_prop(st, dev, "adi,fet-bad-timer-delay-ms",
> > + ltc4283_fet_bad_delay,
> > ARRAY_SIZE(ltc4283_fet_bad_delay));
> > + if (ret < 0)
> > + return ret;
> > + if (ret < ARRAY_SIZE(ltc4283_fet_bad_delay)) {
> > + ret = regmap_update_bits(st->map, LTC4283_CONFIG_2,
> > LTC4283_FTBD_DL_MASK,
> > + FIELD_PREP(LTC4283_FTBD_DL_MASK, ret));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = ltc4283_set_max_limits(st, dev);
> > + if (ret)
> > + return ret;
> > +
> > + ret = ltc4283_pin_config(st, dev);
> > + if (ret)
> > + return ret;
> > +
> > + if (device_property_read_bool(dev, "adi,power-good-reset-on-fet")) {
> > + ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1,
> > + LTC4283_PWRGD_RST_CTRL_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,fet-turn-off-disable")) {
> > + ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1,
> > + LTC4283_FET_BAD_OFF_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,tmr-pull-down-disable")) {
> > + ret = regmap_set_bits(st->map, LTC4283_CONTROL_1,
> > + LTC4283_THERM_TMR_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,dvdt-inrush-control-disable")) {
> > + ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1,
> > + LTC4283_DVDT_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) {
> > + ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2,
> > + LTC4283_UV_RETRY_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) {
> > + ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2,
> > + LTC4283_OV_RETRY_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,external-fault-retry-enable")) {
> > + if (!st->ext_fault)
> > + return dev_err_probe(dev, -EINVAL,
> > + "adi,external-fault-retry-enable
> > set but PGIO4 not configured\n");
> > + ret = regmap_set_bits(st->map, LTC4283_CONTROL_2,
> > + LTC4283_EXT_FAULT_RETRY_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,fault-log-enable")) {
> > + ret = regmap_set_bits(st->map, LTC4283_FAULT_LOG_CTRL,
> > + LTC4283_FAULT_LOG_EN_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = device_property_match_property_string(dev, "adi,overcurrent-
> > retries",
> > + ltc4283_oc_fet_retry,
> > +
> > ARRAY_SIZE(ltc4283_oc_fet_retry));
> > + /* We still want to catch when an invalid string is given. */
> > + if (ret < 0 && ret != -EINVAL)
> > + return dev_err_probe(dev, ret,
> > + "adi,overcurrent-retries invalid value\n");
> > + if (ret >= 0) {
> > + ret = regmap_update_bits(st->map, LTC4283_CONTROL_2,
> > + LTC4283_OC_RETRY_MASK,
> > + FIELD_PREP(LTC4283_OC_RETRY_MASK,
> > ret));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = device_property_match_property_string(dev, "adi,fet-bad-retries",
> > + ltc4283_oc_fet_retry,
> > +
> > ARRAY_SIZE(ltc4283_oc_fet_retry));
> > + if (ret < 0 && ret != -EINVAL)
> > + return dev_err_probe(dev, ret,
> > + "adi,fet-bad-retries invalid value\n");
> > + if (ret >= 0) {
> > + ret = regmap_update_bits(st->map, LTC4283_CONTROL_2,
> > + LTC4283_FET_BAD_RETRY_MASK,
> > + FIELD_PREP(LTC4283_FET_BAD_RETRY_MASK,
> > ret));
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,external-fault-fet-off-enable"))
> > {
> > + if (!st->ext_fault)
> > + return dev_err_probe(dev, -EINVAL,
> > + "adi,external-fault-fet-off-enable
> > set but PGIO4 not configured\n");
> > + ret = regmap_set_bits(st->map, LTC4283_CONFIG_3,
> > + LTC4283_EXTFLT_TURN_OFF_MASK);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + if (device_property_read_bool(dev, "adi,vpower-drns-enable")) {
> > + u32 chan = LTC4283_CHAN_DRNS - LTC4283_CHAN_ADI_1;
> > +
> > + __clear_bit(LTC4283_CHAN_DRNS, &st->ch_enable_mask);
> > + /*
> > + * Then, let's by default disable DRNS from ADC2 given that it
> > + * is already being monitored by the VPWR channel. One can still
> > + * enable it later on if needed.
> > + */
> > + ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(chan),
> > + LTC4283_ADC_SELECT_MASK(chan));
> > + if (ret)
> > + return ret;
> > +
> > + val = 1;
> > + } else {
> > + val = 0;
> > + }
> > +
> > + ret = regmap_update_bits(st->map, LTC4283_CONFIG_3,
> > + LTC4283_VPWR_DRNS_MASK,
> > + FIELD_PREP(LTC4283_VPWR_DRNS_MASK, val));
> > + if (ret)
> > + return ret;
> > +
> > + /* Make sure the ADC has 12bit resolution since we're assuming that. */
> > + ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG_2,
> > + LTC4283_ADC_MASK,
> > + FIELD_PREP(LTC4283_ADC_MASK, 3));
> > + if (ret)
> > + return ret;
> > +
> > + /* Energy reads (which are 6 byte block reads) rely on page access */
> > + ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, LTC4283_RW_PAGE_MASK);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * Make sure we are integrating power as we only support reporting
> > + * consumed energy.
> > + */
> > + return regmap_clear_bits(st->map, LTC4283_METER_CONTROL,
> > + LTC4283_INTEGRATE_I_MASK);
> > +}
> > +
> > +static const struct hwmon_channel_info * const ltc4283_info[] = {
> > + HWMON_CHANNEL_INFO(in,
> > + HWMON_I_LCRIT_ALARM | HWMON_I_CRIT_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_MAX_ALARM | HWMON_I_RESET_HISTORY |
> > + HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_FAULT | HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL,
> > + HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
> > + HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
> > + HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
> > + HWMON_I_ENABLE | HWMON_I_LABEL),
> > + HWMON_CHANNEL_INFO(curr,
> > + HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST |
> > + HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM |
> > + HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM |
> > + HWMON_C_RESET_HISTORY | HWMON_C_LABEL),
> > + HWMON_CHANNEL_INFO(power,
> > + HWMON_P_INPUT | HWMON_P_INPUT_LOWEST |
> > + HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN |
> > + HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM |
> > + HWMON_P_RESET_HISTORY | HWMON_P_LABEL),
> > + HWMON_CHANNEL_INFO(energy,
> > + HWMON_E_ENABLE),
> > + HWMON_CHANNEL_INFO(energy64,
> > + HWMON_E_INPUT),
> > + NULL
> > +};
> > +
> > +static const struct hwmon_ops ltc4283_ops = {
> > + .read = ltc4283_read,
> > + .write = ltc4283_write,
> > + .is_visible = ltc4283_is_visible,
> > + .read_string = ltc4283_read_labels,
> > +};
> > +
> > +static const struct hwmon_chip_info ltc4283_chip_info = {
> > + .ops = <c4283_ops,
> > + .info = ltc4283_info,
> > +};
> > +
> > +static int ltc4283_show_fault_log(void *arg, u64 *val, u32 mask)
> > +{
> > + struct ltc4283_hwmon *st = arg;
> > + long alarm;
> > + int ret;
> > +
> > + ret = ltc4283_read_alarm(st, LTC4283_FAULT_LOG, mask, &alarm);
> > + if (ret)
> > + return ret;
> > +
> > + *val = alarm;
> > +
> > + return 0;
> > +}
> > +
> > +static int ltc4283_show_in0_lcrit_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_UV_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_lcrit_fault_log,
> > + ltc4283_show_in0_lcrit_fault_log, NULL, "%llu\n");
> > +
> > +static int ltc4283_show_in0_crit_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_OV_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_crit_fault_log,
> > + ltc4283_show_in0_crit_fault_log, NULL, "%llu\n");
> > +
> > +static int ltc4283_show_fet_bad_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_FET_BAD_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_bad_fault_log,
> > + ltc4283_show_fet_bad_fault_log, NULL, "%llu\n");
> > +
> > +static int ltc4283_show_fet_short_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_FET_SHORT_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_short_fault_log,
> > + ltc4283_show_fet_short_fault_log, NULL, "%llu\n");
> > +
> > +static int ltc4283_show_curr1_crit_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_OC_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_curr1_crit_fault_log,
> > + ltc4283_show_curr1_crit_fault_log, NULL, "%llu\n");
> > +
> > +static int ltc4283_show_power1_failed_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_PWR_FAIL_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_failed_fault_log,
> > + ltc4283_show_power1_failed_fault_log, NULL, "%llu\n");
> > +
> > +static int ltc4283_show_power1_good_input_fault_log(void *arg, u64 *val)
> > +{
> > + return ltc4283_show_fault_log(arg, val, LTC4283_PGI_FAULT_MASK);
> > +}
> > +DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_good_input_fault_log,
> > + ltc4283_show_power1_good_input_fault_log, NULL,
> > "%llu\n");
> > +
> > +static void ltc4283_debugfs_init(struct ltc4283_hwmon *st, struct i2c_client
> > *i2c)
> > +{
> > + debugfs_create_file_unsafe("in0_crit_fault_log", 0400, i2c->debugfs, st,
> > + <c4283_in0_crit_fault_log);
> > + debugfs_create_file_unsafe("in0_lcrit_fault_log", 0400, i2c->debugfs,
> > st,
> > + <c4283_in0_lcrit_fault_log);
> > + debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, i2c->debugfs,
> > st,
> > + <c4283_fet_bad_fault_log);
> > + debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, i2c-
> > >debugfs, st,
> > + <c4283_fet_short_fault_log);
> > + debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs,
> > st,
> > + <c4283_curr1_crit_fault_log);
> > + debugfs_create_file_unsafe("power1_failed_fault_log", 0400, i2c-
> > >debugfs, st,
> > + <c4283_power1_failed_fault_log);
> > + debugfs_create_file_unsafe("power1_good_input_fault_log", 0400, i2c-
> > >debugfs,
> > + st, <c4283_power1_good_input_fault_log);
> > +}
> > +
> > +static bool ltc4283_is_word_reg(unsigned int reg)
> > +{
> > + return reg >= LTC4283_SENSE && reg <= LTC4283_ADIO34_MAX;
> > +}
> > +
> > +static int ltc4283_reg_read(void *context, unsigned int reg, unsigned int *val)
> > +{
> > + struct i2c_client *client = context;
> > + int ret;
> > +
> > + if (ltc4283_is_word_reg(reg))
> > + ret = i2c_smbus_read_word_swapped(client, reg);
> > + else
> > + ret = i2c_smbus_read_byte_data(client, reg);
> > +
> > + if (ret < 0)
> > + return ret;
> > +
> > + *val = ret;
> > + return 0;
> > +}
> > +
> > +static int ltc4283_reg_write(void *context, unsigned int reg, unsigned int val)
> > +{
> > + struct i2c_client *client = context;
> > +
> > + if (ltc4283_is_word_reg(reg))
> > + return i2c_smbus_write_word_swapped(client, reg, val);
> > +
> > + return i2c_smbus_write_byte_data(client, reg, val);
> > +}
> > +
> > +static const struct regmap_bus ltc4283_regmap_bus = {
> > + .reg_read = ltc4283_reg_read,
> > + .reg_write = ltc4283_reg_write,
> > +};
> > +
> > +static bool ltc4283_writable_reg(struct device *dev, unsigned int reg)
> > +{
> > + switch (reg) {
> > + case LTC4283_SYSTEM_STATUS ... LTC4283_FAULT_STATUS:
> > + return false;
> > + case LTC4283_RESERVED_OC:
> > + return false;
> > + case LTC4283_RESERVED_86 ... LTC4283_RESERVED_8F:
> > + return false;
> > + case LTC4283_RESERVED_91 ... LTC4283_RESERVED_A1:
> > + return false;
> > + case LTC4283_RESERVED_A3:
> > + return false;
> > + case LTC4283_RESERVED_AC:
> > + return false;
> > + case LTC4283_POWER_PLAY_MSB ... LTC4283_POWER_PLAY_LSB:
> > + return false;
> > + case LTC4283_RESERVED_F1 ... LTC4283_RESERVED_FF:
> > + return false;
> > + default:
> > + return true;
> > + }
> > +}
> > +
> > +static const struct regmap_config ltc4283_regmap_config = {
> > + .reg_bits = 8,
> > + .val_bits = 16,
> > + .max_register = 0xFF,
> > + .writeable_reg = ltc4283_writable_reg,
> > +};
> > +
> > +static int ltc4283_probe(struct i2c_client *client)
> > +{
> > + struct device *dev = &client->dev, *hwmon;
> > + struct auxiliary_device *adev;
> > + struct ltc4283_hwmon *st;
> > + int ret, id;
> > +
> > + st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
> > + if (!st)
> > + return -ENOMEM;
> > +
> > + if (!i2c_check_functionality(client->adapter,
> > + I2C_FUNC_SMBUS_BYTE_DATA |
> > + I2C_FUNC_SMBUS_WORD_DATA |
> > + I2C_FUNC_SMBUS_READ_I2C_BLOCK))
> > + return -EOPNOTSUPP;
> > +
> > + st->client = client;
> > + st->map = devm_regmap_init(dev, <c4283_regmap_bus, client,
> > + <c4283_regmap_config);
> > + if (IS_ERR(st->map))
> > + return dev_err_probe(dev, PTR_ERR(st->map),
> > + "Failed to create regmap\n");
> > +
> > + ret = ltc4283_setup(st, dev);
> > + if (ret)
> > + return ret;
> > +
> > + hwmon = devm_hwmon_device_register_with_info(dev, "ltc4283", st,
> > + <c4283_chip_info, NULL);
> > +
> > + if (IS_ERR(hwmon))
> > + return PTR_ERR(hwmon);
> > +
> > + ltc4283_debugfs_init(st, client);
> > +
> > + if (!st->gpio_mask)
> > + return 0;
> > +
> > + id = (client->adapter->nr << 10) | client->addr;
> > + adev = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, "gpio",
> > + NULL, id);
> > + if (!adev)
> > + return dev_err_probe(dev, -ENODEV, "Failed to add GPIO
> > device\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id ltc4283_of_match[] = {
> > + { .compatible = "adi,ltc4283" },
> > + { }
> > +};
> > +
> > +static const struct i2c_device_id ltc4283_i2c_id[] = {
> > + { "ltc4283" },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(i2c, ltc4283_i2c_id);
> > +
> > +static struct i2c_driver ltc4283_driver = {
> > + .driver = {
> > + .name = "ltc4283",
> > + .of_match_table = ltc4283_of_match,
> > + },
> > + .probe = ltc4283_probe,
> > + .id_table = ltc4283_i2c_id,
> > +};
> > +module_i2c_driver(ltc4283_driver);
> > +
> > +MODULE_AUTHOR("Nuno Sá <nuno.sa@analog.com>");
> > +MODULE_DESCRIPTION("LTC4283 Hot Swap Controller driver");
> > +MODULE_LICENSE("GPL");
> >
^ permalink raw reply
* [PATCH v5 3/3] MAINTAINERS: Add entry for Onsemi LC898217XC lens voice coil driver
From: Vasiliy Doylov via B4 Relay @ 2026-04-11 13:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, david
Cc: linux-media, devicetree, linux-kernel, phone-devel,
Vitalii Skorkin, Antonio Rische, Vasiliy Doylov
In-Reply-To: <20260411-media-i2c-lc898217xc-initial-driver-v5-0-c71ddcf40bad@mainlining.org>
From: Vasiliy Doylov <nekocwd@mainlining.org>
Add entry for Onsemi LC898217XC lens voice coil driver
Signed-off-by: Vasiliy Doylov <nekocwd@mainlining.org>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d4b396dccfe9..a87c03ad740b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19938,6 +19938,13 @@ S: Supported
W: http://www.onsemi.com
F: drivers/net/phy/ncn*
+ONSEMI LC898217XC LENS VOICE COIL DRIVER
+M: Vasiliy Doylov <nekocwd@mainlining.org>
+L: linux-media@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/media/i2c/onnn,lc898217xc.yaml
+F: drivers/media/i2c/lc898217xc.c
+
OP-TEE DRIVER
M: Jens Wiklander <jens.wiklander@linaro.org>
L: op-tee@lists.trustedfirmware.org (moderated for non-subscribers)
--
2.50.1
^ permalink raw reply related
* [PATCH v5 0/3] media: i2c: lc898217xc: initial driver
From: Vasiliy Doylov via B4 Relay @ 2026-04-11 13:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, david
Cc: linux-media, devicetree, linux-kernel, phone-devel,
Vitalii Skorkin, Antonio Rische, Vasiliy Doylov,
Krzysztof Kozlowski
LX898217XC is a 11 bit DAC, designed for linear control
of voice coil motor. This driver creates a V4L2 subdevice
and provides control to set the desired focus.
Tested on Oneplus 6 (oneplus-enchilada)
Co-developed-by: Vitalii Skorkin <nikroks@mainlining.org>
Signed-off-by: Vitalii Skorkin <nikroks@mainlining.org>
Co-developed-by: Antonio Rische <nt8r@protonmail.com>
Signed-off-by: Antonio Rische <nt8r@protonmail.com>
Signed-off-by: Vasiliy Doylov <nekocwd@mainlining.org>
---
Changes in v5:
- Add Reviewed-by tag (Krzysztof)
- Link to v4: https://lore.kernel.org/r/20260325-media-i2c-lc898217xc-initial-driver-v4-0-6ad6fd74915e@mainlining.org
Changes in v4:
- Removed unused focus ctrl (Dave)
- Added ctrl state restore on runtime_resume (Dave)
- Removed subscribe/unsubscribe event handlers (Dave)
- Removed V4L2_SUBDEV_FL_HAS_EVENTS flag (Dave)
- Changed supplies from vcc to vdd + vana
- Fixed free and PM issues on probe fail
- Fixed typo in devicetree documentation
- Link to v3: https://lore.kernel.org/r/20251201-media-i2c-lc898217xc-initial-driver-v3-0-46e23897e921@mainlining.org
Changes in v3:
- Fixed MAINTAINERS (Krzysztof)
- Reordered commits (Krzysztof)
- Removed blank line from device-tree documentation (Krzysztof)
- Refactored to use CCI regmap
- Refactored to use dev_err_probe in probe
- Link to v2: https://lore.kernel.org/all/20250304-media-i2c-lc898217xc-initial-driver-v2-0-6a463cef3ea8@mainlining.org/
Changes in v2:
- PM functions annotated as __maybe_unused.
- Fixed dt bindings documentation commit message
- Added v4l2 events (now v4l2-compliance shows no failed tests)
- Link to v1: https://lore.kernel.org/r/20250304-media-i2c-lc898217xc-initial-driver-v1-0-e2ffd2b2fd5e@mainlining.org
---
Vasiliy Doylov (3):
media: dt-bindings: Add LC898217XC documentation
media: i2c: Add driver for LC898217XC VCM
MAINTAINERS: Add entry for Onsemi LC898217XC lens voice coil driver
.../bindings/media/i2c/onnn,lc898217xc.yaml | 59 +++++
MAINTAINERS | 7 +
drivers/media/i2c/Kconfig | 9 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/lc898217xc.c | 289 +++++++++++++++++++++
5 files changed, 365 insertions(+)
---
base-commit: 66672af7a095d89f082c5327f3b15bc2f93d558e
change-id: 20250227-media-i2c-lc898217xc-initial-driver-d7b50a135ce5
Best regards,
--
Vasiliy Doylov <nekocwd@mainlining.org>
^ permalink raw reply
* [PATCH v5 1/3] media: dt-bindings: Add LC898217XC documentation
From: Vasiliy Doylov via B4 Relay @ 2026-04-11 13:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, david
Cc: linux-media, devicetree, linux-kernel, phone-devel,
Vitalii Skorkin, Antonio Rische, Vasiliy Doylov,
Krzysztof Kozlowski
In-Reply-To: <20260411-media-i2c-lc898217xc-initial-driver-v5-0-c71ddcf40bad@mainlining.org>
From: Vasiliy Doylov <nekocwd@mainlining.org>
Add device tree bindings documentation for ON Semiconductor
LC898217XC voice coil motor.
Signed-off-by: Vasiliy Doylov <nekocwd@mainlining.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/media/i2c/onnn,lc898217xc.yaml | 59 ++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/onnn,lc898217xc.yaml b/Documentation/devicetree/bindings/media/i2c/onnn,lc898217xc.yaml
new file mode 100644
index 000000000000..3dd137d4c67c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/onnn,lc898217xc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2025 Vasiliy Doylov <nekocwd@mainlining.org>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/onnn,lc898217xc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ON Semiconductor LC898217XC Voice Coil Motor (VCM) Lens
+
+maintainers:
+ - Vasiliy Doylov <nekocwd@mainlining.org>
+
+description:
+ The LC898217XC is a 11-bit digital-to-analog (DAC) converter.
+ VCM current is controlled with a linear mode driver.The DAC is controlled
+ via a 2-wire (I2C-compatible) serial interface that operates at clock
+ rates up to 1MHz. This chip integrates Advanced Actuator Control (AAC)
+ technology and is intended for driving voice coil lenses in camera modules.
+
+properties:
+ compatible:
+ enum:
+ - onnn,lc898217xc
+
+ reg:
+ maxItems: 1
+
+ vana-supply:
+ description:
+ Definition of the regulator used as motor voltage supply.
+
+ vdd-supply:
+ description:
+ Definition of the regulator used as digital core voltage supply.
+
+required:
+ - compatible
+ - reg
+ - vana-supply
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera-lens@74 {
+ compatible = "onnn,lc898217xc";
+ reg = <0x74>;
+
+ vana-supply = <&mt6358_vaf_reg>;
+ vdd-supply = <&mt6358_vcamio_reg>;
+ };
+ };
+
+...
--
2.50.1
^ permalink raw reply related
* [PATCH v5 2/3] media: i2c: Add driver for LC898217XC VCM
From: Vasiliy Doylov via B4 Relay @ 2026-04-11 13:13 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, david
Cc: linux-media, devicetree, linux-kernel, phone-devel,
Vitalii Skorkin, Antonio Rische, Vasiliy Doylov
In-Reply-To: <20260411-media-i2c-lc898217xc-initial-driver-v5-0-c71ddcf40bad@mainlining.org>
From: Vasiliy Doylov <nekocwd@mainlining.org>
LC898217XC is a 11 bit DAC, designed for linear control
of voice coil motor. This driver creates a V4L2 subdevice
and provides control to set the desired focus.
Tested on Oneplus 6 (oneplus-enchilada)
Signed-off-by: Vasiliy Doylov <nekocwd@mainlining.org>
---
drivers/media/i2c/Kconfig | 9 ++
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/lc898217xc.c | 289 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 299 insertions(+)
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 8f2ba4121586..346dd4a14105 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -926,6 +926,15 @@ config VIDEO_DW9807_VCM
capability. This is designed for linear control of
voice coil motors, controlled via I2C serial interface.
+config VIDEO_LC898217XC
+ tristate "LC898217XC lens voice coil support"
+ select V4L2_CCI_I2C
+ help
+ This is a driver for the LC898217XC camera lens voice coil.
+ LC898217XC is a 11 bit DAC with 110mA output current sink
+ capability. This is designed for linear control of
+ voice coil motors, controlled via I2C serial interface.
+
endif
menu "Flash devices"
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index 90b276a7417a..f55c44feca53 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_IMX415) += imx415.o
obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o
obj-$(CONFIG_VIDEO_KS0127) += ks0127.o
+obj-$(CONFIG_VIDEO_LC898217XC) += lc898217xc.o
obj-$(CONFIG_VIDEO_LM3560) += lm3560.o
obj-$(CONFIG_VIDEO_LM3646) += lm3646.o
obj-$(CONFIG_VIDEO_LT6911UXE) += lt6911uxe.o
diff --git a/drivers/media/i2c/lc898217xc.c b/drivers/media/i2c/lc898217xc.c
new file mode 100644
index 000000000000..cfac7e7ce3d6
--- /dev/null
+++ b/drivers/media/i2c/lc898217xc.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2025 Vasiliy Doylov <nekocwd@mainlining.org>
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-cci.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-event.h>
+
+#define LC898217XC_NAME "lc898217xc"
+/* Actuator has 11 bit resolution */
+#define LC898217XC_MAX_FOCUS_POS (2048 - 1)
+#define LC898217XC_MIN_FOCUS_POS 0
+#define LC898217XC_FOCUS_STEPS 1
+#define LC898217XC_DAC_ADDR CCI_REG16(0x84)
+
+static const char *const lc898217xc_supply_names[] = {
+ "vdd",
+ "vana",
+};
+
+struct lc898217xc {
+ struct regulator_bulk_data supplies[ARRAY_SIZE(lc898217xc_supply_names)];
+ struct v4l2_ctrl_handler ctrls;
+ struct v4l2_subdev sd;
+ struct regmap *regmap;
+};
+
+static inline struct lc898217xc *sd_to_lc898217xc(struct v4l2_subdev *subdev)
+{
+ return container_of(subdev, struct lc898217xc, sd);
+}
+
+static int lc898217xc_set_dac(struct lc898217xc *lc898217xc, u16 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&lc898217xc->sd);
+ int ret;
+
+ ret = cci_write(lc898217xc->regmap, LC898217XC_DAC_ADDR, val, NULL);
+ if (ret)
+ dev_err(&client->dev, "failed to set DAC: %d\n", ret);
+
+ return ret;
+}
+
+static int lc898217xc_power_on(struct lc898217xc *lc898217xc)
+{
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(lc898217xc_supply_names),
+ lc898217xc->supplies);
+ if (ret < 0)
+ return ret;
+
+ usleep_range(8000, 10000);
+ return 0;
+}
+
+static int lc898217xc_power_off(struct lc898217xc *lc898217xc)
+{
+ regulator_bulk_disable(ARRAY_SIZE(lc898217xc_supply_names),
+ lc898217xc->supplies);
+ return 0;
+}
+
+static int __maybe_unused lc898217xc_runtime_suspend(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct lc898217xc *lc898217xc = sd_to_lc898217xc(sd);
+
+ lc898217xc_power_off(lc898217xc);
+ return 0;
+}
+
+static int __maybe_unused lc898217xc_runtime_resume(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct lc898217xc *lc898217xc = sd_to_lc898217xc(sd);
+ int ret;
+
+ ret = lc898217xc_power_on(lc898217xc);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable regulators\n");
+ return ret;
+ }
+
+ __v4l2_ctrl_handler_setup(&lc898217xc->ctrls);
+
+ return ret;
+}
+
+static int lc898217xc_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct lc898217xc *lc898217xc = container_of(ctrl->handler,
+ struct lc898217xc, ctrls);
+
+ if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE)
+ return lc898217xc_set_dac(lc898217xc, ctrl->val);
+
+ return 0;
+}
+
+static const struct v4l2_ctrl_ops lc898217xc_ctrl_ops = {
+ .s_ctrl = lc898217xc_set_ctrl,
+};
+
+static int lc898217xc_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ return pm_runtime_resume_and_get(sd->dev);
+}
+
+static int lc898217xc_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ pm_runtime_put_autosuspend(sd->dev);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_internal_ops lc898217xc_int_ops = {
+ .open = lc898217xc_open,
+ .close = lc898217xc_close,
+};
+
+static const struct v4l2_subdev_core_ops lc898217xc_core_ops = {
+ .log_status = v4l2_ctrl_subdev_log_status,
+};
+
+static const struct v4l2_subdev_ops lc898217xc_ops = {
+ .core = &lc898217xc_core_ops,
+};
+
+static int lc898217xc_init_controls(struct lc898217xc *lc898217xc)
+{
+ struct v4l2_ctrl_handler *hdl = &lc898217xc->ctrls;
+ const struct v4l2_ctrl_ops *ops = &lc898217xc_ctrl_ops;
+
+ v4l2_ctrl_handler_init(hdl, 1);
+
+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE,
+ LC898217XC_MIN_FOCUS_POS,
+ LC898217XC_MAX_FOCUS_POS,
+ LC898217XC_FOCUS_STEPS, 0);
+
+ if (hdl->error)
+ return hdl->error;
+
+ lc898217xc->sd.ctrl_handler = hdl;
+
+ return 0;
+}
+
+static int lc898217xc_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct lc898217xc *lc898217xc;
+ unsigned int i;
+ int ret;
+
+ lc898217xc = devm_kzalloc(dev, sizeof(*lc898217xc), GFP_KERNEL);
+ if (!lc898217xc)
+ return -ENOMEM;
+
+ lc898217xc->regmap = devm_cci_regmap_init_i2c(client, 8);
+ if (IS_ERR(lc898217xc->regmap))
+ return dev_err_probe(dev, PTR_ERR(lc898217xc->regmap),
+ "failed to initialize CCI\n");
+
+ /* Initialize subdev */
+ v4l2_i2c_subdev_init(&lc898217xc->sd, client, &lc898217xc_ops);
+
+ for (i = 0; i < ARRAY_SIZE(lc898217xc_supply_names); i++)
+ lc898217xc->supplies[i].supply = lc898217xc_supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(lc898217xc_supply_names),
+ lc898217xc->supplies);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get regulators\n");
+
+ ret = lc898217xc_power_on(lc898217xc);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable regulators\n");
+
+ ret = lc898217xc_init_controls(lc898217xc);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to init v4l2 controls\n");
+ goto err_power_off;
+ }
+
+ /* Initialize subdev */
+ lc898217xc->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ lc898217xc->sd.internal_ops = &lc898217xc_int_ops;
+
+ ret = media_entity_pads_init(&lc898217xc->sd.entity, 0, NULL);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "failed to init media entity pads");
+ goto err_free_handler;
+ }
+
+ lc898217xc->sd.entity.function = MEDIA_ENT_F_LENS;
+
+ /*
+ * Enable runtime PM. As the device has been powered manually, mark it
+ * as active, and increase the usage count without resuming the device.
+ */
+ pm_runtime_set_active(dev);
+ pm_runtime_get_noresume(dev);
+ pm_runtime_enable(dev);
+
+ ret = v4l2_async_register_subdev(&lc898217xc->sd);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
+ goto err_pm;
+ }
+
+ /*
+ * Finally, enable autosuspend and decrease the usage count. The device
+ * will get suspended after the autosuspend delay, turning the power
+ * off.
+ */
+ pm_runtime_set_autosuspend_delay(dev, 1000);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ return 0;
+
+err_pm:
+ pm_runtime_disable(dev);
+ pm_runtime_put_noidle(dev);
+ media_entity_cleanup(&lc898217xc->sd.entity);
+err_free_handler:
+ v4l2_ctrl_handler_free(&lc898217xc->ctrls);
+err_power_off:
+ lc898217xc_power_off(lc898217xc);
+ return ret;
+}
+
+static void lc898217xc_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct lc898217xc *lc898217xc = sd_to_lc898217xc(sd);
+ struct device *dev = &client->dev;
+
+ v4l2_async_unregister_subdev(&lc898217xc->sd);
+ v4l2_ctrl_handler_free(&lc898217xc->ctrls);
+ media_entity_cleanup(&lc898217xc->sd.entity);
+
+ /*
+ * Disable runtime PM. In case runtime PM is disabled in the kernel,
+ * make sure to turn power off manually.
+ */
+ pm_runtime_disable(dev);
+ if (!pm_runtime_status_suspended(dev))
+ lc898217xc_power_off(lc898217xc);
+ pm_runtime_set_suspended(dev);
+}
+
+static const struct of_device_id lc898217xc_of_table[] = {
+ { .compatible = "onnn,lc898217xc" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, lc898217xc_of_table);
+
+static const struct dev_pm_ops lc898217xc_pm_ops = {
+ SET_RUNTIME_PM_OPS(lc898217xc_runtime_suspend,
+ lc898217xc_runtime_resume, NULL)
+};
+
+static struct i2c_driver lc898217xc_i2c_driver = {
+ .driver = {
+ .name = LC898217XC_NAME,
+ .pm = &lc898217xc_pm_ops,
+ .of_match_table = lc898217xc_of_table,
+ },
+ .probe = lc898217xc_probe,
+ .remove = lc898217xc_remove,
+};
+module_i2c_driver(lc898217xc_i2c_driver);
+
+MODULE_AUTHOR("Vasiliy Doylov <nekocwd@mainlining.org>");
+MODULE_DESCRIPTION("Onsemi LC898217XC VCM driver");
+MODULE_LICENSE("GPL");
--
2.50.1
^ permalink raw reply related
* [PATCH] arm64: dts: st: Fix SAI addresses on stm32mp251
From: Marek Vasut @ 2026-04-11 13:02 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Alexandre Torgue, Conor Dooley, Krzysztof Kozlowski,
Maxime Coquelin, Olivier Moysan, Rob Herring, devicetree,
linux-kernel, linux-stm32
The second field of SAI register addresses should be within 0x3f0 bytes
from the start of the SAI register addresses, the second field describes
the ID registers which are at that addrses. Currently, the second field
does not match RM, fix it.
Fixes: bf26d75a95f1 ("arm64: dts: st: add sai support on stm32mp251")
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Olivier Moysan <olivier.moysan@foss.st.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 673fbc5632e69..9c63fdb5a885a 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -1202,7 +1202,7 @@ spi5: spi@40280000 {
sai1: sai@40290000 {
compatible = "st,stm32mp25-sai";
- reg = <0x40290000 0x4>, <0x4029a3f0 0x10>;
+ reg = <0x40290000 0x4>, <0x402903f0 0x10>;
ranges = <0 0x40290000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1236,7 +1236,7 @@ sai1b: audio-controller@40290024 {
sai2: sai@402a0000 {
compatible = "st,stm32mp25-sai";
- reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>;
+ reg = <0x402a0000 0x4>, <0x402a03f0 0x10>;
ranges = <0 0x402a0000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1270,7 +1270,7 @@ sai2b: audio-controller@402a0024 {
sai3: sai@402b0000 {
compatible = "st,stm32mp25-sai";
- reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>;
+ reg = <0x402b0000 0x4>, <0x402b03f0 0x10>;
ranges = <0 0x402b0000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
@@ -1362,7 +1362,7 @@ usart1: serial@40330000 {
sai4: sai@40340000 {
compatible = "st,stm32mp25-sai";
- reg = <0x40340000 0x4>, <0x4034a3f0 0x10>;
+ reg = <0x40340000 0x4>, <0x403403f0 0x10>;
ranges = <0 0x40340000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
--
2.53.0
^ permalink raw reply related
* [PATCH] ARM: dts: stm32: Enable PHY SSC on DH STM32MP13xx DHCOR DHSBC board
From: Marek Vasut @ 2026-04-11 13:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Marek Vasut, Alexandre Torgue, Christoph Niedermaier,
Conor Dooley, Krzysztof Kozlowski, Maxime Coquelin, Rob Herring,
devicetree, kernel, linux-kernel, linux-stm32
Add realtek,rxc-ssc-enable and realtek,sysclk-ssc-enable to both PHY
DT nodes to enable PHY Spread Spectrum on RXC and SYSCLK, CLKOUT is
disabled and therefore does not need SSC enabled.
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: kernel@dh-electronics.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
---
arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
index 9902849ed0406..70d85af467353 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
@@ -97,6 +97,8 @@ ethphy1: ethernet-phy@1 {
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
reg = <1>;
realtek,clkout-disable;
+ realtek,rxc-ssc-enable;
+ realtek,sysclk-ssc-enable;
reset-assert-us = <15000>;
reset-deassert-us = <55000>;
reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
@@ -146,6 +148,8 @@ ethphy2: ethernet-phy@1 {
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
reg = <1>;
realtek,clkout-disable;
+ realtek,rxc-ssc-enable;
+ realtek,sysclk-ssc-enable;
reset-assert-us = <15000>;
reset-deassert-us = <55000>;
reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>;
--
2.53.0
^ permalink raw reply related
* [PATCH v2 21/21] gpio: add GPIO controller found on Waveshare DSI TOUCH panels
From: Dmitry Baryshkov @ 2026-04-11 12:10 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio, Riccardo Mereu
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
The Waveshare DSI TOUCH family of panels has separate on-board GPIO
controller, which controls power supplies to the panel and the touch
screen and provides reset pins for both the panel and the touchscreen.
Also it provides a simple PWM controller for panel backlight. Add
support for this GPIO controller.
Tested-by: Riccardo Mereu <r.mereu@arduino.cc>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpio/Kconfig | 10 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-waveshare-dsi.c | 208 ++++++++++++++++++++++++++++++++++++++
3 files changed, 219 insertions(+)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index dbe7c6e63eab..1b210c451151 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -805,6 +805,16 @@ config GPIO_VISCONTI
help
Say yes here to support GPIO on Tohisba Visconti.
+config GPIO_WAVESHARE_DSI_TOUCH
+ tristate "Waveshare GPIO controller for DSI panels"
+ depends on BACKLIGHT_CLASS_DEVICE
+ depends on I2C
+ select REGMAP_I2C
+ help
+ Enable support for the GPIO and PWM controller found on Waveshare DSI
+ TOUCH panel kits. It provides GPIOs (used for regulator control and
+ resets) and backlight support.
+
config GPIO_WCD934X
tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
depends on MFD_WCD934X
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 20d4a57afdaa..75ce89fc3b93 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -207,6 +207,7 @@ obj-$(CONFIG_GPIO_VIRTUSER) += gpio-virtuser.o
obj-$(CONFIG_GPIO_VIRTIO) += gpio-virtio.o
obj-$(CONFIG_GPIO_VISCONTI) += gpio-visconti.o
obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
+obj-$(CONFIG_GPIO_WAVESHARE_DSI_TOUCH) += gpio-waveshare-dsi.o
obj-$(CONFIG_GPIO_WCD934X) += gpio-wcd934x.o
obj-$(CONFIG_GPIO_WHISKEY_COVE) += gpio-wcove.o
obj-$(CONFIG_GPIO_WINBOND) += gpio-winbond.o
diff --git a/drivers/gpio/gpio-waveshare-dsi.c b/drivers/gpio/gpio-waveshare-dsi.c
new file mode 100644
index 000000000000..f4a1d4d3b872
--- /dev/null
+++ b/drivers/gpio/gpio-waveshare-dsi.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Waveshare International Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/fb.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+/* I2C registers of the microcontroller. */
+#define REG_TP 0x94
+#define REG_LCD 0x95
+#define REG_PWM 0x96
+#define REG_SIZE 0x97
+#define REG_ID 0x98
+#define REG_VERSION 0x99
+
+enum {
+ GPIO_AVDD = 0,
+ GPIO_PANEL_RESET = 1,
+ GPIO_BL_ENABLE = 2,
+ GPIO_IOVCC = 4,
+ GPIO_VCC = 8,
+ GPIO_TS_RESET = 9,
+};
+
+#define NUM_GPIO 16
+
+struct waveshare_gpio {
+ struct mutex dir_lock;
+ struct mutex pwr_lock;
+ struct regmap *regmap;
+ u16 poweron_state;
+
+ struct gpio_chip gc;
+};
+
+static const struct regmap_config waveshare_gpio_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = REG_PWM,
+};
+
+static int waveshare_gpio_get(struct waveshare_gpio *state, unsigned int offset)
+{
+ u16 pwr_state;
+
+ guard(mutex)(&state->pwr_lock);
+ pwr_state = state->poweron_state & BIT(offset);
+
+ return !!pwr_state;
+}
+
+static int waveshare_gpio_set(struct waveshare_gpio *state, unsigned int offset, int value)
+{
+ u16 last_val;
+ int err;
+
+ guard(mutex)(&state->pwr_lock);
+
+ last_val = state->poweron_state;
+ if (value)
+ last_val |= BIT(offset);
+ else
+ last_val &= ~BIT(offset);
+
+ state->poweron_state = last_val;
+
+ err = regmap_write(state->regmap, REG_TP, last_val >> 8);
+ if (!err)
+ err = regmap_write(state->regmap, REG_LCD, last_val & 0xff);
+
+ return err;
+}
+
+static int waveshare_gpio_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int waveshare_gpio_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct waveshare_gpio *state = gpiochip_get_data(gc);
+
+ return waveshare_gpio_get(state, offset);
+}
+
+static int waveshare_gpio_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct waveshare_gpio *state = gpiochip_get_data(gc);
+
+ return waveshare_gpio_set(state, offset, value);
+}
+
+static int waveshare_gpio_update_status(struct backlight_device *bl)
+{
+ struct waveshare_gpio *state = bl_get_data(bl);
+ int brightness = backlight_get_brightness(bl);
+
+ waveshare_gpio_set(state, GPIO_BL_ENABLE, brightness);
+
+ return regmap_write(state->regmap, REG_PWM, brightness);
+}
+
+static const struct backlight_ops waveshare_gpio_bl = {
+ .update_status = waveshare_gpio_update_status,
+};
+
+static int waveshare_gpio_probe(struct i2c_client *i2c)
+{
+ struct backlight_properties props = {};
+ struct waveshare_gpio *state;
+ struct device *dev = &i2c->dev;
+ struct backlight_device *bl;
+ struct regmap *regmap;
+ unsigned int data;
+ int ret;
+
+ state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ ret = devm_mutex_init(dev, &state->dir_lock);
+ if (ret)
+ return ret;
+
+ ret = devm_mutex_init(dev, &state->pwr_lock);
+ if (ret)
+ return ret;
+
+ regmap = devm_regmap_init_i2c(i2c, &waveshare_gpio_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
+
+ state->regmap = regmap;
+ i2c_set_clientdata(i2c, state);
+
+ ret = regmap_read(regmap, REG_ID, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel hw id = 0x%x\n", data);
+
+ ret = regmap_read(regmap, REG_SIZE, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel size = %d\n", data);
+
+ ret = regmap_read(regmap, REG_VERSION, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel mcu version = 0x%x\n", data);
+
+ ret = waveshare_gpio_set(state, GPIO_TS_RESET, 1);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to program GPIOs\n");
+
+ msleep(20);
+
+ state->gc.parent = dev;
+ state->gc.label = i2c->name;
+ state->gc.owner = THIS_MODULE;
+ state->gc.base = -1;
+ state->gc.ngpio = NUM_GPIO;
+
+ /* it is output only */
+ state->gc.get = waveshare_gpio_gpio_get;
+ state->gc.set = waveshare_gpio_gpio_set;
+ state->gc.get_direction = waveshare_gpio_gpio_get_direction;
+ state->gc.can_sleep = true;
+
+ ret = devm_gpiochip_add_data(dev, &state->gc, state);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to create gpiochip\n");
+
+ props.type = BACKLIGHT_RAW;
+ props.max_brightness = 255;
+ props.brightness = 255;
+ bl = devm_backlight_device_register(dev, dev_name(dev), dev, state,
+ &waveshare_gpio_bl, &props);
+ return PTR_ERR_OR_ZERO(bl);
+}
+
+static const struct of_device_id waveshare_gpio_dt_ids[] = {
+ { .compatible = "waveshare,dsi-touch-gpio" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, waveshare_gpio_dt_ids);
+
+static struct i2c_driver waveshare_gpio_regulator_driver = {
+ .driver = {
+ .name = "waveshare-regulator",
+ .of_match_table = of_match_ptr(waveshare_gpio_dt_ids),
+ },
+ .probe = waveshare_gpio_probe,
+};
+
+module_i2c_driver(waveshare_gpio_regulator_driver);
+
+MODULE_DESCRIPTION("GPIO controller driver for Waveshare DSI touch panels");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH v2 20/21] dt-bindings: gpio: describe Waveshare GPIO controller
From: Dmitry Baryshkov @ 2026-04-11 12:10 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio, Riccardo Mereu
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
The Waveshare DSI TOUCH family of panels has separate on-board GPIO
controller, which controls power supplies to the panel and the touch
screen and provides reset pins for both the panel and the touchscreen.
Also it provides a simple PWM controller for panel backlight.
Add bindings for these GPIO controllers. As overall integration might be
not very obvious (and it differs significantly from the bindings used by
the original drivers), provide complete example with the on-board
regulators and the DSI panel.
Tested-by: Riccardo Mereu <r.mereu@arduino.cc>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/gpio/waveshare,dsi-touch-gpio.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml
new file mode 100644
index 000000000000..410348fcda25
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/waveshare,dsi-touch-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Waveshare GPIO controller on DSI TOUCH panels
+
+maintainers:
+ - Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+
+description:
+ Waveshare DSI TOUCH panel kits contain separate GPIO controller for toggling
+ power supplies and panel / touchscreen resets.
+
+properties:
+ compatible:
+ const: waveshare,dsi-touch-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wsgpio: gpio@45 {
+ compatible = "waveshare,dsi-touch-gpio";
+ reg = <0x45>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ panel_avdd: regulator-panel-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-avdd";
+ gpios = <&wsgpio 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel_iovcc: regulator-panel-iovcc {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-iovcc";
+ gpios = <&wsgpio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel_vcc: regulator-panel-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-vcc";
+ gpios = <&wsgpio 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ reg = <0>;
+ compatible = "waveshare,8.0-dsi-touch-a", "jadard,jd9365da-h3";
+ reset-gpios = <&wsgpio 1 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&panel_avdd>;
+ vccio-supply = <&panel_iovcc>;
+ backlight = <&wsgpio>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+
+ port {
+ dsi_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+...
--
2.47.3
^ permalink raw reply related
* [PATCH v2 19/21] drm/panel: add driver for Waveshare 8.8" DSI TOUCH-A panel
From: Dmitry Baryshkov @ 2026-04-11 12:10 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
Add driver for the panel found on Waveshare 8.8" DSI TOUCH-A kit. It
uses ota7290b IC as a controller.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/Kconfig | 12 ++
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-focaltech-ota7290b.c | 208 +++++++++++++++++++++++
3 files changed, 221 insertions(+)
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index ba527b4d7737..979109c27b9b 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -144,6 +144,18 @@ config DRM_PANEL_FEIYANG_FY07024DI26A30D
Say Y if you want to enable support for panels based on the
Feiyang FY07024DI26A30-D MIPI-DSI interface.
+config DRM_PANEL_FOCALTECH_OTA7290B
+ tristate "Focaltech OTA7290B"
+ depends on DRM_MIPI_DSI
+ depends on I2C
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_KMS_HELPER
+ help
+ Enable support for panels using OTA7290B as a controller (for
+ example, Waveshare 12.3" DSI TOUCH-A panel). Say Y here if you want
+ to enable support for this panel. To compile this driver as a module,
+ choose M here.
+
config DRM_PANEL_DSI_CM
tristate "Generic DSI command mode panels"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index a4291dc3905b..0d694acbfbb6 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
+obj-$(CONFIG_DRM_PANEL_FOCALTECH_OTA7290B) += panel-focaltech-ota7290b.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX8279) += panel-himax-hx8279.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83102) += panel-himax-hx83102.o
obj-$(CONFIG_DRM_PANEL_HIMAX_HX83112A) += panel-himax-hx83112a.o
diff --git a/drivers/gpu/drm/panel/panel-focaltech-ota7290b.c b/drivers/gpu/drm/panel/panel-focaltech-ota7290b.c
new file mode 100644
index 000000000000..991d6a4caf17
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-focaltech-ota7290b.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Waveshare International Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+struct ota7290b {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+
+ struct regulator *power;
+ struct gpio_desc *reset;
+ struct regulator *avdd;
+ struct regulator *iovcc;
+
+ enum drm_panel_orientation orientation;
+};
+
+static inline struct ota7290b *panel_to_ota(struct drm_panel *panel)
+{
+ return container_of(panel, struct ota7290b, panel);
+}
+
+static int ota7290b_prepare(struct drm_panel *panel)
+{
+ struct ota7290b *ctx = panel_to_ota(panel);
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+ int ret;
+
+ if (ctx->iovcc) {
+ ret = regulator_enable(ctx->iovcc);
+ if (ret)
+ dev_err(panel->dev, "failed to enable IO regulator: %d\n", ret);
+ }
+
+ if (ctx->avdd) {
+ ret = regulator_enable(ctx->avdd);
+ if (ret)
+ dev_err(panel->dev, "failed to enable AVDD regulator: %d\n", ret);
+ }
+
+ if (ctx->reset) {
+ gpiod_set_value_cansleep(ctx->reset, 0);
+ msleep(60);
+ gpiod_set_value_cansleep(ctx->reset, 1);
+ msleep(60);
+ gpiod_set_value_cansleep(ctx->reset, 0);
+ msleep(60);
+ }
+
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 50);
+
+ if (dsi_ctx.accum_err < 0)
+ dev_err(panel->dev, "failed to init panel: %d\n", ret);
+
+ return dsi_ctx.accum_err;
+}
+
+static int ota7290b_unprepare(struct drm_panel *panel)
+{
+ struct ota7290b *ctx = panel_to_ota(panel);
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+ mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+
+ if (ctx->reset) {
+ gpiod_set_value_cansleep(ctx->reset, 1);
+ msleep(5);
+ }
+
+ if (ctx->avdd)
+ regulator_disable(ctx->avdd);
+
+ if (ctx->iovcc)
+ regulator_disable(ctx->iovcc);
+
+ return 0;
+}
+
+static const struct drm_display_mode waveshare_dsi_touch_8_8_a_mode = {
+ .clock = 75000,
+
+ .hdisplay = 480,
+ .hsync_start = 480 + 50,
+ .hsync_end = 480 + 50 + 50,
+ .htotal = 480 + 50 + 50 + 50,
+
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 20,
+ .vsync_end = 1920 + 20 + 20,
+ .vtotal = 1920 + 20 + 20 + 20,
+
+ .width_mm = 68,
+ .height_mm = 219,
+ .type = DRM_MODE_TYPE_DRIVER,
+};
+
+static int ota7290b_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ return drm_connector_helper_get_modes_fixed(connector, &waveshare_dsi_touch_8_8_a_mode);
+}
+
+static enum drm_panel_orientation ota7290b_get_orientation(struct drm_panel *panel)
+{
+ struct ota7290b *ctx = panel_to_ota(panel);
+
+ return ctx->orientation;
+}
+
+static const struct drm_panel_funcs ota7290b_funcs = {
+ .prepare = ota7290b_prepare,
+ .unprepare = ota7290b_unprepare,
+ .get_modes = ota7290b_get_modes,
+ .get_orientation = ota7290b_get_orientation,
+};
+
+static int ota7290b_probe(struct mipi_dsi_device *dsi)
+{
+ struct ota7290b *ctx;
+ int ret;
+
+ ctx = devm_drm_panel_alloc(&dsi->dev, struct ota7290b, panel,
+ &ota7290b_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ if (!ctx)
+ return -ENOMEM;
+ mipi_dsi_set_drvdata(dsi, ctx);
+ ctx->dsi = dsi;
+
+ ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->reset))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
+ "Couldn't get our reset GPIO\n");
+
+ ctx->iovcc = devm_regulator_get_optional(&dsi->dev, "iovcc");
+ if (IS_ERR(ctx->iovcc))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->iovcc),
+ "Couldn't get our iovcc supply\n");
+
+ ctx->avdd = devm_regulator_get_optional(&dsi->dev, "avdd");
+ if (IS_ERR(ctx->avdd))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->avdd),
+ "Couldn't get our avdd supply\n");
+
+ ret = of_drm_get_panel_orientation(
+ dsi->dev.of_node, &ctx->orientation);
+ if (ret) {
+ dev_err(&dsi->dev, "%pOF: failed to get orientation: %d\n",
+ dsi->dev.of_node, ret);
+ return ret;
+ }
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return ret;
+
+ ctx->panel.prepare_prev_first = true;
+
+ ret = devm_drm_panel_add(&dsi->dev, &ctx->panel);
+ if (ret)
+ return ret;
+
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_HSE |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ dsi->format = MIPI_DSI_FMT_RGB888,
+ dsi->lanes = 2;
+
+ return devm_mipi_dsi_attach(&dsi->dev, dsi);
+}
+
+static const struct of_device_id ota7290b_of_match[] = {
+ { .compatible = "waveshare,8.8-dsi-touch-a", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ota7290b_of_match);
+
+static struct mipi_dsi_driver ota7290b_driver = {
+ .probe = ota7290b_probe,
+ .driver = {
+ .name = "focaltech-ota7290b",
+ .of_match_table = ota7290b_of_match,
+ },
+};
+module_mipi_dsi_driver(ota7290b_driver);
+
+MODULE_DESCRIPTION("Panel driver for Focaltech OTA7290B panels");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* [PATCH v2 18/21] drm/panel: add devm_drm_panel_add() helper
From: Dmitry Baryshkov @ 2026-04-11 12:10 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
Add devm_drm_panel_add(), devres-managed version of drm_panel_add().
It's not uncommon for the panel drivers to use devres functions for most
of the resources. Provide corresponding replacement for drm_panel_add().
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/drm_panel.c | 23 +++++++++++++++++++++++
include/drm/drm_panel.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c
index d1e6598ea3bc..a6029b699b73 100644
--- a/drivers/gpu/drm/drm_panel.c
+++ b/drivers/gpu/drm/drm_panel.c
@@ -101,6 +101,29 @@ void drm_panel_remove(struct drm_panel *panel)
}
EXPORT_SYMBOL(drm_panel_remove);
+static void drm_panel_add_release(void *data)
+{
+ drm_panel_remove(data);
+}
+
+/**
+ * devm_drm_panel_add - add a panel to the global registry using devres
+ * @panel: panel to add
+ *
+ * Add a panel to the global registry so that it can be looked
+ * up by display drivers. The panel to be added must have been
+ * allocated by devm_drm_panel_alloc(). Unlike drm_panel_add() with this
+ * function there is no need to call drm_panel_remove(), it will be called
+ * automatically.
+ */
+int devm_drm_panel_add(struct device *dev, struct drm_panel *panel)
+{
+ drm_panel_add(panel);
+
+ return devm_add_action_or_reset(dev, drm_panel_add_release, panel);
+}
+EXPORT_SYMBOL(devm_drm_panel_add);
+
/**
* drm_panel_prepare - power on a panel
* @panel: DRM panel
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 2407bfa60236..1fb9148dd095 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -329,6 +329,7 @@ void drm_panel_put(struct drm_panel *panel);
void drm_panel_add(struct drm_panel *panel);
void drm_panel_remove(struct drm_panel *panel);
+int devm_drm_panel_add(struct device *dev, struct drm_panel *panel);
void drm_panel_prepare(struct drm_panel *panel);
void drm_panel_unprepare(struct drm_panel *panel);
--
2.47.3
^ permalink raw reply related
* [PATCH v2 17/21] drm/panel: ilitek-ili9881c: support Waveshare 7.0" DSI panel
From: Dmitry Baryshkov @ 2026-04-11 12:10 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
Enable support for Waveshare 7.0" DSI TOUCH-A panel. It requires
additional voltage regulator, iovcc.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 251 +++++++++++++++++++++++++-
1 file changed, 249 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
index 947b47841b01..0652cdb57d11 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9881c.c
@@ -52,6 +52,7 @@ struct ili9881c {
const struct ili9881c_desc *desc;
struct regulator *power;
+ struct regulator *iovcc;
struct gpio_desc *reset;
enum drm_panel_orientation orientation;
@@ -1997,6 +1998,205 @@ static const struct ili9881c_instr bsd1218_a101kl68_init[] = {
ILI9881C_COMMAND_INSTR(0xd3, 0x3f),
};
+static const struct ili9881c_instr waveshare_7inch_a_init[] = {
+ ILI9881C_SWITCH_PAGE_INSTR(3),
+ ILI9881C_COMMAND_INSTR(0x01, 0x00),
+ ILI9881C_COMMAND_INSTR(0x02, 0x00),
+ ILI9881C_COMMAND_INSTR(0x03, 0x73),
+ ILI9881C_COMMAND_INSTR(0x04, 0x00),
+ ILI9881C_COMMAND_INSTR(0x05, 0x00),
+ ILI9881C_COMMAND_INSTR(0x06, 0x0a),
+ ILI9881C_COMMAND_INSTR(0x07, 0x00),
+ ILI9881C_COMMAND_INSTR(0x08, 0x00),
+ ILI9881C_COMMAND_INSTR(0x09, 0x61),
+ ILI9881C_COMMAND_INSTR(0x0a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0c, 0x01),
+ ILI9881C_COMMAND_INSTR(0x0d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x0f, 0x61),
+ ILI9881C_COMMAND_INSTR(0x10, 0x61),
+ ILI9881C_COMMAND_INSTR(0x11, 0x00),
+ ILI9881C_COMMAND_INSTR(0x12, 0x00),
+ ILI9881C_COMMAND_INSTR(0x13, 0x00),
+ ILI9881C_COMMAND_INSTR(0x14, 0x00),
+ ILI9881C_COMMAND_INSTR(0x15, 0x00),
+ ILI9881C_COMMAND_INSTR(0x16, 0x00),
+ ILI9881C_COMMAND_INSTR(0x17, 0x00),
+ ILI9881C_COMMAND_INSTR(0x18, 0x00),
+ ILI9881C_COMMAND_INSTR(0x19, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1c, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x1e, 0x40),
+ ILI9881C_COMMAND_INSTR(0x1f, 0x80),
+ ILI9881C_COMMAND_INSTR(0x20, 0x06),
+ ILI9881C_COMMAND_INSTR(0x21, 0x01),
+ ILI9881C_COMMAND_INSTR(0x22, 0x00),
+ ILI9881C_COMMAND_INSTR(0x23, 0x00),
+ ILI9881C_COMMAND_INSTR(0x24, 0x00),
+ ILI9881C_COMMAND_INSTR(0x25, 0x00),
+ ILI9881C_COMMAND_INSTR(0x26, 0x00),
+ ILI9881C_COMMAND_INSTR(0x27, 0x00),
+ ILI9881C_COMMAND_INSTR(0x28, 0x33),
+ ILI9881C_COMMAND_INSTR(0x29, 0x03),
+ ILI9881C_COMMAND_INSTR(0x2a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2c, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x2f, 0x00),
+ ILI9881C_COMMAND_INSTR(0x30, 0x00),
+ ILI9881C_COMMAND_INSTR(0x31, 0x00),
+ ILI9881C_COMMAND_INSTR(0x32, 0x00),
+ ILI9881C_COMMAND_INSTR(0x33, 0x00),
+ ILI9881C_COMMAND_INSTR(0x34, 0x04),
+ ILI9881C_COMMAND_INSTR(0x35, 0x00),
+ ILI9881C_COMMAND_INSTR(0x36, 0x00),
+ ILI9881C_COMMAND_INSTR(0x37, 0x00),
+ ILI9881C_COMMAND_INSTR(0x38, 0x3c),
+ ILI9881C_COMMAND_INSTR(0x39, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3b, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3c, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3d, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x3f, 0x00),
+ ILI9881C_COMMAND_INSTR(0x40, 0x00),
+ ILI9881C_COMMAND_INSTR(0x41, 0x00),
+ ILI9881C_COMMAND_INSTR(0x42, 0x00),
+ ILI9881C_COMMAND_INSTR(0x43, 0x00),
+ ILI9881C_COMMAND_INSTR(0x44, 0x00),
+ ILI9881C_COMMAND_INSTR(0x50, 0x10),
+ ILI9881C_COMMAND_INSTR(0x51, 0x32),
+ ILI9881C_COMMAND_INSTR(0x52, 0x54),
+ ILI9881C_COMMAND_INSTR(0x53, 0x76),
+ ILI9881C_COMMAND_INSTR(0x54, 0x98),
+ ILI9881C_COMMAND_INSTR(0x55, 0xba),
+ ILI9881C_COMMAND_INSTR(0x56, 0x10),
+ ILI9881C_COMMAND_INSTR(0x57, 0x32),
+ ILI9881C_COMMAND_INSTR(0x58, 0x54),
+ ILI9881C_COMMAND_INSTR(0x59, 0x76),
+ ILI9881C_COMMAND_INSTR(0x5a, 0x98),
+ ILI9881C_COMMAND_INSTR(0x5b, 0xba),
+ ILI9881C_COMMAND_INSTR(0x5c, 0xdc),
+ ILI9881C_COMMAND_INSTR(0x5d, 0xfe),
+ ILI9881C_COMMAND_INSTR(0x5e, 0x00),
+ ILI9881C_COMMAND_INSTR(0x5f, 0x0e),
+ ILI9881C_COMMAND_INSTR(0x60, 0x0f),
+ ILI9881C_COMMAND_INSTR(0x61, 0x0c),
+ ILI9881C_COMMAND_INSTR(0x62, 0x0d),
+ ILI9881C_COMMAND_INSTR(0x63, 0x06),
+ ILI9881C_COMMAND_INSTR(0x64, 0x07),
+ ILI9881C_COMMAND_INSTR(0x65, 0x02),
+ ILI9881C_COMMAND_INSTR(0x66, 0x02),
+ ILI9881C_COMMAND_INSTR(0x67, 0x02),
+ ILI9881C_COMMAND_INSTR(0x68, 0x02),
+ ILI9881C_COMMAND_INSTR(0x69, 0x01),
+ ILI9881C_COMMAND_INSTR(0x6a, 0x00),
+ ILI9881C_COMMAND_INSTR(0x6b, 0x02),
+ ILI9881C_COMMAND_INSTR(0x6c, 0x15),
+ ILI9881C_COMMAND_INSTR(0x6d, 0x14),
+ ILI9881C_COMMAND_INSTR(0x6e, 0x02),
+ ILI9881C_COMMAND_INSTR(0x6f, 0x02),
+ ILI9881C_COMMAND_INSTR(0x70, 0x02),
+ ILI9881C_COMMAND_INSTR(0x71, 0x02),
+ ILI9881C_COMMAND_INSTR(0x72, 0x02),
+ ILI9881C_COMMAND_INSTR(0x73, 0x02),
+ ILI9881C_COMMAND_INSTR(0x74, 0x02),
+ ILI9881C_COMMAND_INSTR(0x75, 0x0e),
+ ILI9881C_COMMAND_INSTR(0x76, 0x0f),
+ ILI9881C_COMMAND_INSTR(0x77, 0x0c),
+ ILI9881C_COMMAND_INSTR(0x78, 0x0d),
+ ILI9881C_COMMAND_INSTR(0x79, 0x06),
+ ILI9881C_COMMAND_INSTR(0x7a, 0x07),
+ ILI9881C_COMMAND_INSTR(0x7b, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7c, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7d, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7e, 0x02),
+ ILI9881C_COMMAND_INSTR(0x7f, 0x01),
+ ILI9881C_COMMAND_INSTR(0x80, 0x00),
+ ILI9881C_COMMAND_INSTR(0x81, 0x02),
+ ILI9881C_COMMAND_INSTR(0x82, 0x14),
+ ILI9881C_COMMAND_INSTR(0x83, 0x15),
+ ILI9881C_COMMAND_INSTR(0x84, 0x02),
+ ILI9881C_COMMAND_INSTR(0x85, 0x02),
+ ILI9881C_COMMAND_INSTR(0x86, 0x02),
+ ILI9881C_COMMAND_INSTR(0x87, 0x02),
+ ILI9881C_COMMAND_INSTR(0x88, 0x02),
+ ILI9881C_COMMAND_INSTR(0x89, 0x02),
+ ILI9881C_COMMAND_INSTR(0x8a, 0x02),
+
+ ILI9881C_SWITCH_PAGE_INSTR(4),
+ ILI9881C_COMMAND_INSTR(0x38, 0x01),
+ ILI9881C_COMMAND_INSTR(0x39, 0x00),
+ ILI9881C_COMMAND_INSTR(0x6c, 0x15),
+ ILI9881C_COMMAND_INSTR(0x6e, 0x2a),
+ ILI9881C_COMMAND_INSTR(0x6f, 0x33),
+ ILI9881C_COMMAND_INSTR(0x3a, 0x94),
+ ILI9881C_COMMAND_INSTR(0x8d, 0x14),
+ ILI9881C_COMMAND_INSTR(0x87, 0xba),
+ ILI9881C_COMMAND_INSTR(0x26, 0x76),
+ ILI9881C_COMMAND_INSTR(0xb2, 0xd1),
+ ILI9881C_COMMAND_INSTR(0xb5, 0x06),
+ ILI9881C_COMMAND_INSTR(0x3b, 0x98),
+
+ ILI9881C_SWITCH_PAGE_INSTR(1),
+ ILI9881C_COMMAND_INSTR(0x22, 0x0a),
+ ILI9881C_COMMAND_INSTR(0x31, 0x00),
+ ILI9881C_COMMAND_INSTR(0x53, 0x71),
+ ILI9881C_COMMAND_INSTR(0x55, 0x8f),
+ ILI9881C_COMMAND_INSTR(0x40, 0x33),
+ ILI9881C_COMMAND_INSTR(0x50, 0x96),
+ ILI9881C_COMMAND_INSTR(0x51, 0x96),
+ ILI9881C_COMMAND_INSTR(0x60, 0x23),
+ ILI9881C_COMMAND_INSTR(0xa0, 0x08),
+ ILI9881C_COMMAND_INSTR(0xa1, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xa2, 0x2a),
+ ILI9881C_COMMAND_INSTR(0xa3, 0x10),
+ ILI9881C_COMMAND_INSTR(0xa4, 0x15),
+ ILI9881C_COMMAND_INSTR(0xa5, 0x28),
+ ILI9881C_COMMAND_INSTR(0xa6, 0x1c),
+ ILI9881C_COMMAND_INSTR(0xa7, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xa8, 0x7e),
+ ILI9881C_COMMAND_INSTR(0xa9, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xaa, 0x29),
+ ILI9881C_COMMAND_INSTR(0xab, 0x6b),
+ ILI9881C_COMMAND_INSTR(0xac, 0x1a),
+ ILI9881C_COMMAND_INSTR(0xad, 0x18),
+ ILI9881C_COMMAND_INSTR(0xae, 0x4b),
+ ILI9881C_COMMAND_INSTR(0xaf, 0x20),
+ ILI9881C_COMMAND_INSTR(0xb0, 0x27),
+ ILI9881C_COMMAND_INSTR(0xb1, 0x50),
+ ILI9881C_COMMAND_INSTR(0xb2, 0x64),
+ ILI9881C_COMMAND_INSTR(0xb3, 0x39),
+ ILI9881C_COMMAND_INSTR(0xc0, 0x08),
+ ILI9881C_COMMAND_INSTR(0xc1, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xc2, 0x2a),
+ ILI9881C_COMMAND_INSTR(0xc3, 0x10),
+ ILI9881C_COMMAND_INSTR(0xc4, 0x15),
+ ILI9881C_COMMAND_INSTR(0xc5, 0x28),
+ ILI9881C_COMMAND_INSTR(0xc6, 0x1c),
+ ILI9881C_COMMAND_INSTR(0xc7, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xc8, 0x7e),
+ ILI9881C_COMMAND_INSTR(0xc9, 0x1d),
+ ILI9881C_COMMAND_INSTR(0xca, 0x29),
+ ILI9881C_COMMAND_INSTR(0xcb, 0x6b),
+ ILI9881C_COMMAND_INSTR(0xcc, 0x1a),
+ ILI9881C_COMMAND_INSTR(0xcd, 0x18),
+ ILI9881C_COMMAND_INSTR(0xce, 0x4b),
+ ILI9881C_COMMAND_INSTR(0xcf, 0x20),
+ ILI9881C_COMMAND_INSTR(0xd0, 0x27),
+ ILI9881C_COMMAND_INSTR(0xd1, 0x50),
+ ILI9881C_COMMAND_INSTR(0xd2, 0x64),
+ ILI9881C_COMMAND_INSTR(0xd3, 0x39),
+
+ ILI9881C_SWITCH_PAGE_INSTR(0),
+ ILI9881C_COMMAND_INSTR(0x3a, 0x77),
+ ILI9881C_COMMAND_INSTR(0x36, 0x00),
+};
+
static inline struct ili9881c *panel_to_ili9881c(struct drm_panel *panel)
{
return container_of(panel, struct ili9881c, panel);
@@ -2035,9 +2235,19 @@ static int ili9881c_prepare(struct drm_panel *panel)
int ret;
/* Power the panel */
+ if (ctx->iovcc) {
+ ret = regulator_enable(ctx->iovcc);
+ if (ret)
+ return ret;
+ }
+
+ msleep(5);
ret = regulator_enable(ctx->power);
- if (ret)
- return ret;
+ if (ret) {
+ mctx.accum_err = ret;
+ goto disable_iovcc;
+ }
+
msleep(5);
/* And reset it */
@@ -2074,6 +2284,9 @@ static int ili9881c_prepare(struct drm_panel *panel)
disable_power:
regulator_disable(ctx->power);
+disable_iovcc:
+ if (ctx->iovcc)
+ regulator_disable(ctx->iovcc);
return mctx.accum_err;
}
@@ -2085,6 +2298,8 @@ static int ili9881c_unprepare(struct drm_panel *panel)
mipi_dsi_dcs_set_display_off_multi(&mctx);
mipi_dsi_dcs_enter_sleep_mode_multi(&mctx);
regulator_disable(ctx->power);
+ if (ctx->iovcc)
+ regulator_disable(ctx->iovcc);
gpiod_set_value_cansleep(ctx->reset, 1);
return 0;
@@ -2260,6 +2475,23 @@ static const struct drm_display_mode bsd1218_a101kl68_default_mode = {
.height_mm = 170,
};
+static const struct drm_display_mode waveshare_7inch_a_mode = {
+ .clock = 83333,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 120,
+ .hsync_end = 720 + 120 + 100,
+ .htotal = 720 + 120 + 100 + 100,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 10,
+ .vsync_end = 1280 + 10 + 10,
+ .vtotal = 1280 + 10 + 10 + 10,
+
+ .width_mm = 85,
+ .height_mm = 154,
+};
+
static int ili9881c_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
@@ -2329,6 +2561,11 @@ static int ili9881c_dsi_probe(struct mipi_dsi_device *dsi)
return dev_err_probe(&dsi->dev, PTR_ERR(ctx->power),
"Couldn't get our power regulator\n");
+ ctx->iovcc = devm_regulator_get_optional(&dsi->dev, "iovcc");
+ if (IS_ERR(ctx->iovcc))
+ return dev_err_probe(&dsi->dev, PTR_ERR(ctx->iovcc),
+ "Couldn't get our iovcc regulator\n");
+
ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(ctx->reset))
return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),
@@ -2454,6 +2691,15 @@ static const struct ili9881c_desc bsd1218_a101kl68_desc = {
.lanes = 4,
};
+static const struct ili9881c_desc waveshare_7inch_a_desc = {
+ .init = waveshare_7inch_a_init,
+ .init_length = ARRAY_SIZE(waveshare_7inch_a_init),
+ .mode = &waveshare_7inch_a_mode,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_HSE |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+ .lanes = 2,
+};
+
static const struct of_device_id ili9881c_of_match[] = {
{ .compatible = "bananapi,lhr050h41", .data = &lhr050h41_desc },
{ .compatible = "bestar,bsd1218-a101kl68", .data = &bsd1218_a101kl68_desc },
@@ -2462,6 +2708,7 @@ static const struct of_device_id ili9881c_of_match[] = {
{ .compatible = "tdo,tl050hdv35", .data = &tl050hdv35_desc },
{ .compatible = "wanchanglong,w552946aaa", .data = &w552946aaa_desc },
{ .compatible = "wanchanglong,w552946aba", .data = &w552946aba_desc },
+ { .compatible = "waveshare,7.0-dsi-touch-a", .data = &waveshare_7inch_a_desc },
{ .compatible = "ampire,am8001280g", .data = &am8001280g_desc },
{ .compatible = "raspberrypi,dsi-5inch", &rpi_5inch_desc },
{ .compatible = "raspberrypi,dsi-7inch", &rpi_7inch_desc },
--
2.47.3
^ permalink raw reply related
* [PATCH v2 16/21] drm/panel: jadard-jd9365da-h3: support Waveshare 720p DSI panels
From: Dmitry Baryshkov @ 2026-04-11 12:10 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio, Riccardo Mereu
In-Reply-To: <20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>
Add configuration for Waveshare 9.0" and 10.1" 720p DSI panels using
JD9365 controller.
Tested-by: Riccardo Mereu <r.mereu@arduino.cc>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 312 +++++++++++++++++++++++
1 file changed, 312 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index 49c47f2bfbb9..e9a461239301 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -21,6 +21,8 @@
#include <linux/of.h>
#include <linux/regulator/consumer.h>
+#include <video/mipi_display.h>
+
struct jadard;
struct jadard_panel_desc {
@@ -2283,6 +2285,49 @@ static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {
MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
};
+static int waveshare_10_1_b_init(struct jadard *jadard);
+
+static const struct jadard_panel_desc waveshare_9_0_inch_b_desc = {
+ .mode_4ln = &(const struct drm_display_mode) {
+ .clock = (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 60,
+ .hsync_end = 720 + 60 + 60,
+ .htotal = 720 + 60 + 60 + 4,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 16,
+ .vsync_end = 1280 + 16 + 12,
+ .vtotal = 1280 + 16 + 12 + 4,
+
+ .width_mm = 114,
+ .height_mm = 196,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .mode_2ln = &(const struct drm_display_mode) {
+ .clock = (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 50,
+ .hsync_end = 720 + 50 + 50,
+ .htotal = 720 + 50 + 50 + 50,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 26,
+ .vsync_end = 1280 + 26 + 12,
+ .vtotal = 1280 + 26 + 12 + 4,
+
+ .width_mm = 114,
+ .height_mm = 196,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_10_1_b_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
static const struct drm_display_mode waveshare_10_1_a_mode = {
.clock = (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,
@@ -2627,6 +2672,265 @@ static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {
MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
};
+static int waveshare_10_1_b_init(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ jadard_enable_standard_cmds(&dsi_ctx);
+
+ jd9365da_switch_page(&dsi_ctx, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x7e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x38);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x52);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x34);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x27);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x52);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x14);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x25);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x3f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x34);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x27);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x18);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
+
+ jd9365da_switch_page(&dsi_ctx, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x66);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x13);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x66);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xe3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x21);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x66);
+
+ jd9365da_switch_page(&dsi_ctx, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
+
+ jd9365da_switch_page(&dsi_ctx, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1d);
+
+ jd9365da_switch_page(&dsi_ctx, 0x00);
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+ msleep(120);
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+ msleep(5);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_TEAR_ON);
+
+ return 0;
+}
+
+static const struct jadard_panel_desc waveshare_10_1_inch_b_desc = {
+ .mode_4ln = &(const struct drm_display_mode) {
+ .clock = (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 60,
+ .hsync_end = 720 + 60 + 60,
+ .htotal = 720 + 60 + 60 + 4,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 16,
+ .vsync_end = 1280 + 16 + 12,
+ .vtotal = 1280 + 16 + 12 + 4,
+
+ .width_mm = 125,
+ .height_mm = 222,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .mode_2ln = &(const struct drm_display_mode) {
+ .clock = (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,
+
+ .hdisplay = 720,
+ .hsync_start = 720 + 50,
+ .hsync_end = 720 + 50 + 50,
+ .htotal = 720 + 50 + 50 + 50,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 26,
+ .vsync_end = 1280 + 26 + 12,
+ .vtotal = 1280 + 26 + 12 + 4,
+
+ .width_mm = 125,
+ .height_mm = 222,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = waveshare_10_1_b_init,
+ .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
+};
+
static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
{
struct device *dev = &dsi->dev;
@@ -2748,10 +3052,18 @@ static const struct of_device_id jadard_of_match[] = {
.compatible = "waveshare,8.0-dsi-touch-a",
.data = &waveshare_8_0_inch_a_desc
},
+ {
+ .compatible = "waveshare,9.0-dsi-touch-b",
+ .data = &waveshare_9_0_inch_b_desc
+ },
{
.compatible = "waveshare,10.1-dsi-touch-a",
.data = &waveshare_10_1_inch_a_desc
},
+ {
+ .compatible = "waveshare,10.1-dsi-touch-b",
+ .data = &waveshare_10_1_inch_b_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);
--
2.47.3
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