* [PATCH v4 3/4] dt-bindings: gpio: describe Waveshare GPIO controller
From: Dmitry Baryshkov @ 2026-04-17 23:16 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski, Jie Gan
Cc: dri-devel, devicetree, linux-kernel, linux-gpio, Conor Dooley
In-Reply-To: <20260418-waveshare-dsi-touch-v4-0-b249f3e702bd@oss.qualcomm.com>
The Waveshare DSI TOUCH family of panels has separate on-board GPIO
controller, which controls power supplies to the panel and the touch
screen and provides reset pins for both the panel and the touchscreen.
Also it provides a simple PWM controller for panel backlight.
Add bindings for these GPIO controllers. As overall integration might be
not very obvious (and it differs significantly from the bindings used by
the original drivers), provide complete example with the on-board
regulators and the DSI panel.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../bindings/gpio/waveshare,dsi-touch-gpio.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml
new file mode 100644
index 000000000000..410348fcda25
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/waveshare,dsi-touch-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Waveshare GPIO controller on DSI TOUCH panels
+
+maintainers:
+ - Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+
+description:
+ Waveshare DSI TOUCH panel kits contain separate GPIO controller for toggling
+ power supplies and panel / touchscreen resets.
+
+properties:
+ compatible:
+ const: waveshare,dsi-touch-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wsgpio: gpio@45 {
+ compatible = "waveshare,dsi-touch-gpio";
+ reg = <0x45>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ panel_avdd: regulator-panel-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-avdd";
+ gpios = <&wsgpio 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel_iovcc: regulator-panel-iovcc {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-iovcc";
+ gpios = <&wsgpio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ panel_vcc: regulator-panel-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-vcc";
+ gpios = <&wsgpio 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ reg = <0>;
+ compatible = "waveshare,8.0-dsi-touch-a", "jadard,jd9365da-h3";
+ reset-gpios = <&wsgpio 1 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&panel_avdd>;
+ vccio-supply = <&panel_iovcc>;
+ backlight = <&wsgpio>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+
+ port {
+ dsi_out: endpoint {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+...
--
2.47.3
^ permalink raw reply related
* [PATCH v4 4/4] gpio: add GPIO controller found on Waveshare DSI TOUCH panels
From: Dmitry Baryshkov @ 2026-04-17 23:16 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski, Jie Gan
Cc: dri-devel, devicetree, linux-kernel, linux-gpio, Riccardo Mereu
In-Reply-To: <20260418-waveshare-dsi-touch-v4-0-b249f3e702bd@oss.qualcomm.com>
The Waveshare DSI TOUCH family of panels has separate on-board GPIO
controller, which controls power supplies to the panel and the touch
screen and provides reset pins for both the panel and the touchscreen.
Also it provides a simple PWM controller for panel backlight. Add
support for this GPIO controller.
Tested-by: Riccardo Mereu <r.mereu@arduino.cc>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpio/Kconfig | 10 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-waveshare-dsi.c | 208 ++++++++++++++++++++++++++++++++++++++
3 files changed, 219 insertions(+)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b45fb799e36c..e24ad7e32034 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -804,6 +804,16 @@ config GPIO_VISCONTI
help
Say yes here to support GPIO on Tohisba Visconti.
+config GPIO_WAVESHARE_DSI_TOUCH
+ tristate "Waveshare GPIO controller for DSI panels"
+ depends on BACKLIGHT_CLASS_DEVICE
+ depends on I2C
+ select REGMAP_I2C
+ help
+ Enable support for the GPIO and PWM controller found on Waveshare DSI
+ TOUCH panel kits. It provides GPIOs (used for regulator control and
+ resets) and backlight support.
+
config GPIO_WCD934X
tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
depends on MFD_WCD934X && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c05f7d795c43..94f16f0f28d9 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -206,6 +206,7 @@ obj-$(CONFIG_GPIO_VIRTUSER) += gpio-virtuser.o
obj-$(CONFIG_GPIO_VIRTIO) += gpio-virtio.o
obj-$(CONFIG_GPIO_VISCONTI) += gpio-visconti.o
obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
+obj-$(CONFIG_GPIO_WAVESHARE_DSI_TOUCH) += gpio-waveshare-dsi.o
obj-$(CONFIG_GPIO_WCD934X) += gpio-wcd934x.o
obj-$(CONFIG_GPIO_WHISKEY_COVE) += gpio-wcove.o
obj-$(CONFIG_GPIO_WINBOND) += gpio-winbond.o
diff --git a/drivers/gpio/gpio-waveshare-dsi.c b/drivers/gpio/gpio-waveshare-dsi.c
new file mode 100644
index 000000000000..38f52351bb58
--- /dev/null
+++ b/drivers/gpio/gpio-waveshare-dsi.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Waveshare International Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/fb.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+/* I2C registers of the microcontroller. */
+#define REG_TP 0x94
+#define REG_LCD 0x95
+#define REG_PWM 0x96
+#define REG_SIZE 0x97
+#define REG_ID 0x98
+#define REG_VERSION 0x99
+
+enum {
+ GPIO_AVDD = 0,
+ GPIO_PANEL_RESET = 1,
+ GPIO_BL_ENABLE = 2,
+ GPIO_IOVCC = 4,
+ GPIO_VCC = 8,
+ GPIO_TS_RESET = 9,
+};
+
+#define NUM_GPIO 16
+
+struct waveshare_gpio {
+ struct mutex dir_lock;
+ struct mutex pwr_lock;
+ struct regmap *regmap;
+ u16 poweron_state;
+
+ struct gpio_chip gc;
+};
+
+static const struct regmap_config waveshare_gpio_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = REG_VERSION,
+};
+
+static int waveshare_gpio_get(struct waveshare_gpio *state, unsigned int offset)
+{
+ u16 pwr_state;
+
+ guard(mutex)(&state->pwr_lock);
+ pwr_state = state->poweron_state & BIT(offset);
+
+ return !!pwr_state;
+}
+
+static int waveshare_gpio_set(struct waveshare_gpio *state, unsigned int offset, int value)
+{
+ u16 last_val;
+ int err;
+
+ guard(mutex)(&state->pwr_lock);
+
+ last_val = state->poweron_state;
+ if (value)
+ last_val |= BIT(offset);
+ else
+ last_val &= ~BIT(offset);
+
+ state->poweron_state = last_val;
+
+ err = regmap_write(state->regmap, REG_TP, last_val >> 8);
+ if (!err)
+ err = regmap_write(state->regmap, REG_LCD, last_val & 0xff);
+
+ return err;
+}
+
+static int waveshare_gpio_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int waveshare_gpio_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct waveshare_gpio *state = gpiochip_get_data(gc);
+
+ return waveshare_gpio_get(state, offset);
+}
+
+static int waveshare_gpio_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
+{
+ struct waveshare_gpio *state = gpiochip_get_data(gc);
+
+ return waveshare_gpio_set(state, offset, value);
+}
+
+static int waveshare_gpio_update_status(struct backlight_device *bl)
+{
+ struct waveshare_gpio *state = bl_get_data(bl);
+ int brightness = backlight_get_brightness(bl);
+
+ waveshare_gpio_set(state, GPIO_BL_ENABLE, brightness);
+
+ return regmap_write(state->regmap, REG_PWM, brightness);
+}
+
+static const struct backlight_ops waveshare_gpio_bl = {
+ .update_status = waveshare_gpio_update_status,
+};
+
+static int waveshare_gpio_probe(struct i2c_client *i2c)
+{
+ struct backlight_properties props = {};
+ struct waveshare_gpio *state;
+ struct device *dev = &i2c->dev;
+ struct backlight_device *bl;
+ struct regmap *regmap;
+ unsigned int data;
+ int ret;
+
+ state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ ret = devm_mutex_init(dev, &state->dir_lock);
+ if (ret)
+ return ret;
+
+ ret = devm_mutex_init(dev, &state->pwr_lock);
+ if (ret)
+ return ret;
+
+ regmap = devm_regmap_init_i2c(i2c, &waveshare_gpio_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
+
+ state->regmap = regmap;
+ i2c_set_clientdata(i2c, state);
+
+ ret = regmap_read(regmap, REG_ID, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel hw id = 0x%x\n", data);
+
+ ret = regmap_read(regmap, REG_SIZE, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel size = %d\n", data);
+
+ ret = regmap_read(regmap, REG_VERSION, &data);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to read register\n");
+
+ dev_dbg(dev, "waveshare panel mcu version = 0x%x\n", data);
+
+ ret = waveshare_gpio_set(state, GPIO_TS_RESET, 1);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to program GPIOs\n");
+
+ msleep(20);
+
+ state->gc.parent = dev;
+ state->gc.label = i2c->name;
+ state->gc.owner = THIS_MODULE;
+ state->gc.base = -1;
+ state->gc.ngpio = NUM_GPIO;
+
+ /* it is output only */
+ state->gc.get = waveshare_gpio_gpio_get;
+ state->gc.set = waveshare_gpio_gpio_set;
+ state->gc.get_direction = waveshare_gpio_gpio_get_direction;
+ state->gc.can_sleep = true;
+
+ ret = devm_gpiochip_add_data(dev, &state->gc, state);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to create gpiochip\n");
+
+ props.type = BACKLIGHT_RAW;
+ props.max_brightness = 255;
+ props.brightness = 255;
+ bl = devm_backlight_device_register(dev, dev_name(dev), dev, state,
+ &waveshare_gpio_bl, &props);
+ return PTR_ERR_OR_ZERO(bl);
+}
+
+static const struct of_device_id waveshare_gpio_dt_ids[] = {
+ { .compatible = "waveshare,dsi-touch-gpio" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, waveshare_gpio_dt_ids);
+
+static struct i2c_driver waveshare_gpio_regulator_driver = {
+ .driver = {
+ .name = "waveshare-regulator",
+ .of_match_table = of_match_ptr(waveshare_gpio_dt_ids),
+ },
+ .probe = waveshare_gpio_probe,
+};
+
+module_i2c_driver(waveshare_gpio_regulator_driver);
+
+MODULE_DESCRIPTION("GPIO controller driver for Waveshare DSI touch panels");
+MODULE_LICENSE("GPL");
--
2.47.3
^ permalink raw reply related
* Re: [PATCH 00/40] arm64: dts: rockchip: Wire up frl-enable-gpios for RK3576/RK3588 boards
From: Heiko Stuebner @ 2026-04-17 23:18 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Cristian Ciocaltea
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <70e9a8a0-414d-428f-8da8-9b65cc764849@collabora.com>
Hi Cristan,
Am Freitag, 17. April 2026, 19:55:17 Mitteleuropäische Sommerzeit schrieb Cristian Ciocaltea:
> On 4/17/26 2:34 PM, Heiko Stuebner wrote:
> > Am Freitag, 17. April 2026, 11:24:34 Mitteleuropäische Sommerzeit schrieb Cristian Ciocaltea:
> >
> > [...]
> >
> >> Cristian Ciocaltea (40):
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-100ask-dshanpi-a1
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-armsom-sige5
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-evb1-v10
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-evb2-v10
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-luckfox-core3576
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-nanopi-m5
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-nanopi-r76s
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-roc-pc
> >> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-rock-4d
> >
> > I do think one patch per SoC (rk3576, rk3588, rk3588s) would make more
> > sense, because these patches really are mostly identical :-)
>
> Yeah, apologies for the large number of patches, I went this way to allow
> per-board reviews. As previously noted, I tried to identify the GPIO pins from
> multiple sources, so I'm not entirely sure about the accuracy in every case.
>
> Would it be preferable to squash the patches per SoC and board vendor, instead?
I really would just do it per soc .. so 3 patches. That is a size that is
still reviewable for people, who can then check for their board.
If the patch is labeled "Add frl-enable-gpios for all RK3588s boards", I
do expect people to notice it the same as "oh _my_ board gets changed".
("all" could also be "most" :-) ).
Heiko
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: purwa: Add EL2 overlay for purwa-iot-evk
From: Dmitry Baryshkov @ 2026-04-17 23:27 UTC (permalink / raw)
To: Xin Liu
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, linux-arm-msm,
devicetree, linux-kernel, tingwei.zhang, jie.gan
In-Reply-To: <20260417054200.2402281-1-xin.liu@oss.qualcomm.com>
On Thu, Apr 16, 2026 at 10:42:00PM -0700, Xin Liu wrote:
> Add support for building an EL2 combined DTB for the purwa-iot-evk
> in the Qualcomm DTS Makefile.
>
> The new purwa-iot-evk-el2.dtb is generated by combining the base
> purwa-iot-evk.dtb with the x1-el2.dtbo overlay, enabling EL2-specific
> configurations required by the platform.
>
> Signed-off-by: Xin Liu <xin.liu@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 2/2] spmi: spmi-pmic-arb: add support for PMIC arbiter v8.5
From: Dmitry Baryshkov @ 2026-04-17 23:29 UTC (permalink / raw)
To: Fenglin Wu
Cc: Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio, Subbaraman Narayanamurthy, David Collins,
linux-arm-msm, linux-kernel, devicetree, kernel
In-Reply-To: <48bbcc34-f5bf-4ada-8210-b115f72ee850@oss.qualcomm.com>
On Fri, Apr 17, 2026 at 01:24:07PM +0800, Fenglin Wu wrote:
>
> On 4/2/2026 12:18 PM, Fenglin Wu wrote:
> >
> > On 4/1/2026 7:22 PM, Dmitry Baryshkov wrote:
> > > On Wed, Apr 01, 2026 at 02:41:24AM -0700, Fenglin Wu wrote:
> > > > PMIC arbiter v8.5 is an extension of PMIC arbiter v8 that updated
> > > > the definition of the channel status register bit fields. Add support
> > > > to handle this difference.
> > > >
> > > > Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
> > > > ---
> > > > drivers/spmi/spmi-pmic-arb.c | 69
> > > > ++++++++++++++++++++++++++++++++++++++------
> > > > 1 file changed, 60 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/spmi/spmi-pmic-arb.c
> > > > b/drivers/spmi/spmi-pmic-arb.c
> > > > index 69f8d456324a..deeaa39bb647 100644
> > > > --- a/drivers/spmi/spmi-pmic-arb.c
> > > > +++ b/drivers/spmi/spmi-pmic-arb.c
> > > > @@ -28,6 +28,7 @@
> > > > #define PMIC_ARB_VERSION_V5_MIN 0x50000000
> > > > #define PMIC_ARB_VERSION_V7_MIN 0x70000000
> > > > #define PMIC_ARB_VERSION_V8_MIN 0x80000000
> > > > +#define PMIC_ARB_VERSION_V8P5_MIN 0x80050000
> > > > #define PMIC_ARB_INT_EN 0x0004
> > > > #define PMIC_ARB_FEATURES 0x0004
> > > > @@ -63,11 +64,34 @@
> > > > #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
> > > > /* Channel Status fields */
> > > > -enum pmic_arb_chnl_status {
> > > > - PMIC_ARB_STATUS_DONE = BIT(0),
> > > > - PMIC_ARB_STATUS_FAILURE = BIT(1),
> > > > - PMIC_ARB_STATUS_DENIED = BIT(2),
> > > > - PMIC_ARB_STATUS_DROPPED = BIT(3),
> > > > +struct pmic_arb_chnl_status_mask {
> > > > + u8 done;
> > > > + u8 failure;
> > > > + u8 crc;
> > > > + u8 parity;
> > > > + u8 nack;
> > > > + u8 denied;
> > > > + u8 dropped;
> > > > +};
> > > > +
> > > > +static const struct pmic_arb_chnl_status_mask chnl_status_mask = {
> > > > + .done = BIT(0),
> > > > + .failure = BIT(1),
> > > > + .crc = 0,
> > > > + .parity = 0,
> > > > + .nack = 0,
> > > > + .denied = BIT(2),
> > > > + .dropped = BIT(3),
> > > > +};
> > > > +
> > > > +static const struct pmic_arb_chnl_status_mask
> > > > chnl_status_mask_v8p5 = {
> > > > + .done = BIT(0),
> > > > + .failure = BIT(1),
> > > > + .crc = BIT(2),
> > > > + .parity = BIT(3),
> > > > + .nack = BIT(4),
> > > > + .denied = BIT(5),
> > > > + .dropped = BIT(6),
> > > Would it be better to extract generation-specific callback to decode the
> > > error rather than defining the list of masks?
> >
> > Are you proposing to add a callback in pmic_arb_ver_ops, like
> > '*check_chnl_status', and create separate implementations for PMIC
> > arbiter versions before and after v8.5?
> >
> > This approach would add more extensive code changes with some code
> > duplication, especially for handling common error bits shared across all
> > versions—even if they only print error messages and return an error
> > code. Is that a concern?
> >
> > Fenglin
>
> Hi Dmitry,
>
> Please let me know if this your preferred way and if you are fine with the
> concern that I mentioned.
>
> I can come up with this approach and post a new patch.
Sorry.
Yes, a somewhat duplicate code would be better than having a bitfields
where the individual fields will differ from platform to platform.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH RFC 03/10] media: venus: core: Add msm8939 resource struct
From: Dmitry Baryshkov @ 2026-04-17 23:32 UTC (permalink / raw)
To: Erikas Bitovtas
Cc: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, André Apitzsch, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, linux-media, linux-arm-msm,
devicetree, linux-kernel, linux-clk, ~postmarketos/upstreaming,
phone-devel
In-Reply-To: <20260416-msm8939-venus-rfc-v1-3-a09fcf2c23df@gmail.com>
On Thu, Apr 16, 2026 at 04:43:50PM +0300, Erikas Bitovtas wrote:
> From: André Apitzsch <git@apitzsch.eu>
>
> Add msm8939 configuration data and related compatible.
> Cores on MSM8939 Venus are used for decoding, not encoding. Move them to
> vcodec0 so they can be enabled accordingly.
>
> Signed-off-by: André Apitzsch <git@apitzsch.eu>
> Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
> ---
> drivers/media/platform/qcom/venus/core.c | 39 ++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH RFC 00/10] media: qcom: venus: add MSM8939 support
From: Dmitry Baryshkov @ 2026-04-17 23:37 UTC (permalink / raw)
To: Erikas Bitovtas
Cc: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, André Apitzsch, Bjorn Andersson, Konrad Dybcio,
Michael Turquette, Stephen Boyd, linux-media, linux-arm-msm,
devicetree, linux-kernel, linux-clk, ~postmarketos/upstreaming,
phone-devel
In-Reply-To: <20260416-msm8939-venus-rfc-v1-0-a09fcf2c23df@gmail.com>
On Thu, Apr 16, 2026 at 04:43:47PM +0300, Erikas Bitovtas wrote:
> This patch series adds support for Venus on MSM8939. It is mostly
> similar to MSM8916 Venus, except it needs two additional cores to be
> powered on before it can start decoding.
>
> This patch series is marked as an RFC. Before submitting a non-RFC
> series, I would like to have some details clarified regarding how Venus
> works in order to improve and eventually upstream support for MSM8939.
>
> 1. In downstream, particularly in LA.BR.1.2.9.1_rb1.5, the buses
> for vcodec0 cores have only decoding bits enabled, as depicted
> by qcom,bus-configs property of qcom,msm-bus-clients children
> in qcom,vidc node. Do I understand correctly that these cores
> are only needed for decoding, and not for encoding?
> 2. Currently in device tree there is a video-decoder subnode for Venus
> node, however, for SDM845-v2 (and newer) chipsets, Venus does not use
> subnodes. Does this mean it should be dropped for MSM8939 as well?
> 3. MSM8939 supports HEVC decoding, however, as the patchset is written
> now, it does not work. It can be enabled, however, it will result in
> breakage of Venus for faulty MSM8916 firmwares, because the code
> disabling HEVC for HFI v1 needs to be removed, and as per commit
> c50cc6dc6c48 ("media: venus: hfi_parser: Ignore HEVC encoding for V1"),
> this would break support for some MSM8916 devices. What could be the
> best way to work around this?
> 4. To attach vcodec0 power domain list to dev_{dec,enc}, I had to move
> vdec_get and venc_get later in the probe. Should this be avoided, and
> is there a better way to attach vcodec power domains?
>
> There may be some other issues with this patchset - this is WIP code, so
> feedback is very appreciated. Thank you!
for the next iteration, could you please also include fluster results
for the codecs supported by it (VP8, H.264) and also v4l2-compliance
results?
>
> Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
> ---
> André Apitzsch (4):
> media: dt-bindings: venus: Add qcom,msm8939 schema
> media: venus: core: Add msm8939 resource struct
> arm64: dts: qcom: msm8939: Add venus node
> arm64: dts: qcom: msm8939-longcheer-l9100: Enable venus node
>
> Erikas Bitovtas (6):
> media: venus: add pmdomains to the struct based on the purpose of cores
> arm64: dts: qcom: msm8939-asus-z00t: add Venus
> clk: qcom: gcc-msm8939: mark Venus core GDSCs as hardware controlled
> media: venus: move getting vdec and venc for later
> media: qcom: venus: Move HFI v3 venc and vdec methods to HFI v1
> media: venus: add power domain enable logic for Venus cores
>
> .../bindings/media/qcom,msm8939-venus.yaml | 104 ++++++++++++
> arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 8 +
> .../boot/dts/qcom/msm8939-longcheer-l9100.dts | 8 +
> arch/arm64/boot/dts/qcom/msm8939.dtsi | 24 +++
> drivers/clk/qcom/gcc-msm8939.c | 4 +
> drivers/media/platform/qcom/venus/core.c | 39 +++++
> drivers/media/platform/qcom/venus/core.h | 8 +
> drivers/media/platform/qcom/venus/pm_helpers.c | 187 ++++++++++++++++++---
> drivers/media/platform/qcom/venus/vdec.c | 12 +-
> drivers/media/platform/qcom/venus/venc.c | 12 +-
> 10 files changed, 374 insertions(+), 32 deletions(-)
> ---
> base-commit: 936c21068d7ade00325e40d82bfd2f3f29d9f659
> change-id: 20260416-msm8939-venus-rfc-c025c4c74fae
>
> Best regards,
> --
> Erikas Bitovtas <xerikasxx@gmail.com>
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH RFC 06/10] arm64: dts: qcom: msm8939-asus-z00t: add Venus
From: Dmitry Baryshkov @ 2026-04-17 23:40 UTC (permalink / raw)
To: Erikas Bitovtas
Cc: Konrad Dybcio, Bryan O'Donoghue, Vikash Garodia,
Dikshita Agarwal, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, André Apitzsch,
Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
linux-media, linux-arm-msm, devicetree, linux-kernel, linux-clk,
~postmarketos/upstreaming, phone-devel
In-Reply-To: <ad482bdd-2fb5-432f-be1d-dec25d9cbf5b@gmail.com>
On Thu, Apr 16, 2026 at 07:57:30PM +0300, Erikas Bitovtas wrote:
>
>
> On 4/16/26 6:17 PM, Konrad Dybcio wrote:
> > On 4/16/26 3:43 PM, Erikas Bitovtas wrote:
> >> Enable Venus video encoder/decoder for Asus ZenFone 2 Laser/Selfie.
> >>
> >> Signed-off-by: Erikas Bitovtas <xerikasxx@gmail.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 8 ++++++++
> >> 1 file changed, 8 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
> >> index 90e966242720..231a3e9c1929 100644
> >> --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
> >> +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts
> >> @@ -267,6 +267,14 @@ &usb_hs_phy {
> >> extcon = <&usb_id>;
> >> };
> >>
> >> +&venus {
> >> + status = "okay";
> >
> > You need a firmware path here
>
> When I tested Venus on my device, it loaded without one specified -
> msm-firmware-loader creates a symbolic link from modem partition for
> firmware. Additionally, none of the MSM8916 devices seem to include a
> firmware name. Has something changed since then?
Us becoming more strict? Or more caring? The default file paths are
supposed to be used for unfused devices. So if they don't work with
yours (most likely they don't), please add firmware-name:
firmware-name = "qcom/msm8916/Asus/z00t/venus.mbn";
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 3/4] usb: dwc3: xilinx: Add Versal2 MMI USB 3.2 controller support
From: Thinh Nguyen @ 2026-04-17 23:53 UTC (permalink / raw)
To: Radhey Shyam Pandey
Cc: gregkh@linuxfoundation.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, michal.simek@amd.com, Thinh Nguyen,
p.zabel@pengutronix.de, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@amd.com
In-Reply-To: <20260330190304.1841593-4-radhey.shyam.pandey@amd.com>
On Tue, Mar 31, 2026, Radhey Shyam Pandey wrote:
> Multi-media integrated (MMI) USB3.2 DRD IP is usb3.1 gen2 controller
> which support following speed SSP (10-Gbps), SuperSpeed(5-Gbps),
> high-speed(480-Mbps), full-speed(12-Mbps), and low-speed(1.5-Mbps)
> operation modes.
>
> USB2 and USB3 PHY support Physical connectivity via the Type-C
> connectivity. The MMI USB controller does not have a dedicated wrapper
> register space, so ioremap is skipped via the map_resource config flag.
>
> The driver handles clock and reset initialization. In this initial
> version typec reversibility is not implemented and it is assumed that
> USB3 PHY TCA mux programming is done by MMI configuration data object
> (CDOs) and TI PD controller is configured using external tiva programmer
> on VEK385 evaluation board.
>
> Tested host mode with mass storage device.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> - Introduce xlnx,usb-syscon phandle to access UDH address space
> which is wrapper subsystem IP for USB, DP and HDCP.
Where's xlnx,usb-syscon phandle?
> - Split config struct refactoring into separate patch (2/4).
> - Remove unused regmap/syscon fields and parsing code; defer to
> patch that first consumes them.
> - Fix error message capitalization to lowercase ("reset", "deassert").
> ---
> drivers/usb/dwc3/dwc3-xilinx.c | 50 ++++++++++++++++++++++++++++++----
> 1 file changed, 44 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
> index bb59b56726e7..f2dee28bdc65 100644
> --- a/drivers/usb/dwc3/dwc3-xilinx.c
> +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> @@ -46,6 +46,7 @@ struct dwc3_xlnx;
>
> struct dwc3_xlnx_config {
> int (*pltfm_init)(struct dwc3_xlnx *data);
> + bool map_resource;
Perhaps this property should be inversed since the versal2 is unusual
that it doesn't need mapping of resource. How about no_mem_map?
> };
>
> struct dwc3_xlnx {
> @@ -93,6 +94,29 @@ static void dwc3_xlnx_set_coherency(struct dwc3_xlnx *priv_data, u32 coherency_o
> }
> }
>
> +static int dwc3_xlnx_init_versal2(struct dwc3_xlnx *priv_data)
> +{
> + struct device *dev = priv_data->dev;
> + struct reset_control *crst;
> + int ret;
> +
> + crst = devm_reset_control_get_optional_exclusive(dev, NULL);
> + if (IS_ERR(crst))
> + return dev_err_probe(dev, PTR_ERR(crst),
> + "failed to get reset signal\n");
> +
> + /* assert and deassert reset */
> + ret = reset_control_assert(crst);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "failed to assert reset\n");
Any requirement on how long the reset needs to stay asserted?
> +
> + ret = reset_control_deassert(crst);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "failed to deassert reset\n");
> +
> + return 0;
> +}
> +
> static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
> {
> struct device *dev = priv_data->dev;
> @@ -250,10 +274,16 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
>
> static const struct dwc3_xlnx_config zynqmp_config = {
> .pltfm_init = dwc3_xlnx_init_zynqmp,
> + .map_resource = true,
> };
>
> static const struct dwc3_xlnx_config versal_config = {
> .pltfm_init = dwc3_xlnx_init_versal,
> + .map_resource = true,
> +};
> +
> +static const struct dwc3_xlnx_config versal2_config = {
> + .pltfm_init = dwc3_xlnx_init_versal2,
> };
>
> static const struct of_device_id dwc3_xlnx_of_match[] = {
> @@ -265,6 +295,10 @@ static const struct of_device_id dwc3_xlnx_of_match[] = {
> .compatible = "xlnx,versal-dwc3",
> .data = &versal_config,
> },
> + {
> + .compatible = "xlnx,versal2-mmi-dwc3",
> + .data = &versal2_config,
> + },
> { /* Sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
> @@ -299,19 +333,23 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
> struct dwc3_xlnx *priv_data;
> struct device *dev = &pdev->dev;
> struct device_node *np = dev->of_node;
> - void __iomem *regs;
> int ret;
>
> priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
> if (!priv_data)
> return -ENOMEM;
>
> - regs = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(regs))
> - return dev_err_probe(dev, PTR_ERR(regs), "failed to map registers\n");
> -
> priv_data->dwc3_config = device_get_match_data(dev);
> - priv_data->regs = regs;
> +
> + if (priv_data->dwc3_config->map_resource) {
> + void __iomem *regs;
> +
> + regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(regs))
> + return dev_err_probe(dev, PTR_ERR(regs),
> + "failed to map registers\n");
> + priv_data->regs = regs;
> + }
> priv_data->dev = dev;
>
> platform_set_drvdata(pdev, priv_data);
> --
> 2.43.0
>
BR,
Thinh
^ permalink raw reply
* Re: [PATCH RFC v3 06/11] RISC-V: QoS: add resctrl setup and domain management
From: guo.wenjia23 @ 2026-04-17 10:52 UTC (permalink / raw)
To: fustini
Cc: pjw, palmer, aou, alex, rkrcmar, samuel.holland, aricciardi,
npitre, mindal, atish.patra, atishp, vasu, ved, conor.dooley,
cuiyunhui, cp0613, zhiwei_liu, liwei1518, gong.shuai, gsh517,
liu.qingtao2, reinette.chatre, tony.luck, babu.moger, peternewman,
fenghua.yu, james.morse, ben.horgan, Dave.Martin, robh, conor+dt,
krzk+dt, rafael, lenb, robert.moore, sunilvl, fustini,
linux-kernel, linux-riscv, x86, linux-acpi, acpica-devel,
devicetree, paul.walmsley
In-Reply-To: <20260414-ssqosid-cbqri-rqsc-v7-0-v3-6-b3b2e7e9847a@kernel.org>
Hi Drew,
On Wed, Apr 15, 2026 at 9:57 AM Drew Fustini <fustini@kernel.org> wrote:
> Add the setup and domain management layer: domain allocation
> (qos_new_domain), controller value initialization
> (qos_init_domain_ctrlval), resource struct initialization for cache and
> bandwidth resources, domain registration with the resctrl filesystem
> (qos_resctrl_add_controller_domain), and the top-level setup function
> (qos_resctrl_setup) that probes all controllers and calls resctrl_init().
>
> Also add qos_resctrl_online_cpu() and qos_resctrl_offline_cpu() for CPU
> hotplug integration.
>
> Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
> Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
> Signed-off-by: Drew Fustini <fustini@kernel.org>
> ---
> arch/riscv/kernel/qos/qos_resctrl.c | 295 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 294 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/qos/qos_resctrl.c b/arch/riscv/kernel/qos/qos_resctrl.c
> index a4a120f89840..8d7e3b0abb75 100644
> --- a/arch/riscv/kernel/qos/qos_resctrl.c
> +++ b/arch/riscv/kernel/qos/qos_resctrl.c
> @@ -675,7 +675,23 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_l3_mon_domai
>
> void resctrl_arch_reset_all_ctrls(struct rdt_resource *r)
> {
> - /* not implemented for the RISC-V resctrl implementation */
> + struct cbqri_resctrl_res *hw_res;
> + struct rdt_ctrl_domain *d;
> + enum resctrl_conf_type t;
> + u32 default_ctrl;
> + int i;
> +
> + lockdep_assert_cpus_held();
> +
> + hw_res = container_of(r, struct cbqri_resctrl_res, resctrl_res);
> + default_ctrl = resctrl_get_default_ctrl(r);
> +
> + list_for_each_entry(d, &r->ctrl_domains, hdr.list) {
> + for (i = 0; i < hw_res->max_rcid; i++) {
> + for (t = 0; t < CDP_NUM_TYPES; t++)
> + resctrl_arch_update_one(r, d, i, t, default_ctrl);
For the bw controller, default_ctrl = max_bw, and resctrl_arch_update_one will set the rbwb of all RCIDs to max_bw.
According to the spec: The sum of Rbwb allocated across all rcids must not exceed MRBWB value.
Does this conflict with the spec?
> + }
> + }
> }
>
> void resctrl_arch_pre_mount(void)
> @@ -797,3 +813,280 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain *d,
> spin_unlock(&ctrl->lock);
> return val;
> }
> +
> +static struct rdt_ctrl_domain *qos_new_domain(struct cbqri_controller *ctrl)
> +{
> + struct cbqri_resctrl_dom *hw_dom;
> + struct rdt_ctrl_domain *domain;
> +
> + hw_dom = kzalloc_obj(*hw_dom, GFP_KERNEL);
> + if (!hw_dom)
> + return NULL;
> +
> + /* associate this cbqri_controller with the domain */
> + hw_dom->hw_ctrl = ctrl;
> +
> + /* the rdt_domain struct from inside the cbqri_resctrl_dom struct */
> + domain = &hw_dom->resctrl_ctrl_dom;
> +
> + INIT_LIST_HEAD(&domain->hdr.list);
> +
> + return domain;
> +}
> +
> +static int qos_init_domain_ctrlval(struct rdt_resource *r, struct rdt_ctrl_domain *d)
> +{
> + struct cbqri_resctrl_res *hw_res;
> + int err = 0;
> + int i;
> +
> + hw_res = container_of(r, struct cbqri_resctrl_res, resctrl_res);
> +
> + for (i = 0; i < hw_res->max_rcid; i++) {
> + err = resctrl_arch_update_one(r, d, i, 0, resctrl_get_default_ctrl(r));
Also set rbwb of all RCIDs to max_bw. Does this also conflict with the spec?
> + if (err)
> + return err;
> + }
> + return 0;
> +}
> +
Thanks,
Wenjia
^ permalink raw reply
* Re: [PATCH v2 4/4] usb: dwc3: xilinx: Add support to program MMI USB TX deemphasis
From: Thinh Nguyen @ 2026-04-18 0:28 UTC (permalink / raw)
To: Radhey Shyam Pandey
Cc: gregkh@linuxfoundation.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, michal.simek@amd.com, Thinh Nguyen,
p.zabel@pengutronix.de, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@amd.com
In-Reply-To: <20260330190304.1841593-5-radhey.shyam.pandey@amd.com>
On Tue, Mar 31, 2026, Radhey Shyam Pandey wrote:
> Introduces support for programming the 18-bit TX Deemphasis value that
> drives the pipe_TxDeemph signal, as defined in the PIPE4 specification.
>
> The configured value is recommended by Synopsys and is intended for
> standard (non-compliance) operation. These Gen2 equalization settings
> have been validated through both internal and external compliance
> testing. By applying this setting, the stability of USB 3.2 enumeration
> is improved and now SuperSpeedPlus devices are consistently recognized as
> USB 3.2 Gen 2 by the MMI USB Host controller.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> Changes for v2:
> - Don't use compatible check for deemphasis programming.
> - Rename property "snps,lcsr_tx_deemph" to "snps,lcsr-tx-deemph"
> (hyphens per kernel convention).
> - Fix double space in LCSR_TX_DEEMPH register comment.
> - Add blank line between register offset define and "Bit fields" section.
> ---
> drivers/usb/dwc3/core.c | 17 +++++++++++++++++
> drivers/usb/dwc3/core.h | 8 ++++++++
> drivers/usb/dwc3/dwc3-xilinx.c | 15 ++++++++++++---
> 3 files changed, 37 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 161a4d58b2ce..e678a53a90b3 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -646,6 +646,15 @@ static void dwc3_config_soc_bus(struct dwc3 *dwc)
> reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
> dwc3_writel(dwc, DWC3_GSBUSCFG0, reg);
> }
> +
> + if (dwc->csr_tx_deemph_field_1 != DWC3_LCSR_TX_DEEMPH_UNSPECIFIED) {
> + u32 reg;
> +
> + reg = dwc3_readl(dwc, DWC3_LCSR_TX_DEEMPH);
> + reg &= ~DWC3_LCSR_TX_DEEMPH_MASK(~0);
> + reg |= DWC3_LCSR_TX_DEEMPH_MASK(dwc->csr_tx_deemph_field_1);
> + dwc3_writel(dwc, DWC3_LCSR_TX_DEEMPH, reg);
> + }
> }
>
> static int dwc3_core_ulpi_init(struct dwc3 *dwc)
> @@ -1671,11 +1680,13 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
> static void dwc3_get_software_properties(struct dwc3 *dwc,
> const struct dwc3_properties *properties)
> {
> + u32 csr_tx_deemph_field_1;
> struct device *tmpdev;
> u16 gsbuscfg0_reqinfo;
> int ret;
>
> dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
> + dwc->csr_tx_deemph_field_1 = DWC3_LCSR_TX_DEEMPH_UNSPECIFIED;
>
> if (properties->gsbuscfg0_reqinfo !=
> DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
> @@ -1693,6 +1704,12 @@ static void dwc3_get_software_properties(struct dwc3 *dwc,
> &gsbuscfg0_reqinfo);
> if (!ret)
> dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo;
> +
> + ret = device_property_read_u32(tmpdev,
> + "snps,lcsr-tx-deemph",
> + &csr_tx_deemph_field_1);
> + if (!ret)
> + dwc->csr_tx_deemph_field_1 = csr_tx_deemph_field_1;
> }
> }
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index a35b3db1f9f3..99874ad09730 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -181,6 +181,8 @@
>
> #define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80))
>
> +#define DWC3_LCSR_TX_DEEMPH 0xd060
> +
This should be DWC3_LCSR_TX_DEEMPH(n) where n is the USB3 port number
> /* Bit fields */
>
> /* Global SoC Bus Configuration INCRx Register 0 */
> @@ -198,6 +200,10 @@
> #define DWC3_GSBUSCFG0_REQINFO(n) (((n) & 0xffff) << 16)
> #define DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED 0xffffffff
>
> +/* LCSR_TX_DEEMPH Register: setting TX deemphasis used in normal operation in gen2 */
> +#define DWC3_LCSR_TX_DEEMPH_MASK(n) ((n) & 0x3ffff)
> +#define DWC3_LCSR_TX_DEEMPH_UNSPECIFIED 0xffffffff
> +
> /* Global Debug LSP MUX Select */
> #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
> #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
> @@ -1180,6 +1186,7 @@ struct dwc3_glue_ops {
> * @wakeup_pending_funcs: Indicates whether any interface has requested for
> * function wakeup in bitmap format where bit position
> * represents interface_id.
> + * @csr_tx_deemph_field_1: stores TX deemphasis used in Gen2 operation.
How do you plan to apply this for the case of multiple USB3 ports. Only
to the first USB3 port0 or all of them? Document how you want to handle
this.
> */
> struct dwc3 {
> struct work_struct drd_work;
> @@ -1417,6 +1424,7 @@ struct dwc3 {
> struct dentry *debug_root;
> u32 gsbuscfg0_reqinfo;
> u32 wakeup_pending_funcs;
> + u32 csr_tx_deemph_field_1;
> };
>
> #define INCRX_BURST_MODE 0
> diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
> index f2dee28bdc65..44008856ee73 100644
> --- a/drivers/usb/dwc3/dwc3-xilinx.c
> +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> @@ -41,11 +41,13 @@
> #define PIPE_CLK_SELECT 0
> #define XLNX_USB_FPD_POWER_PRSNT 0x80
> #define FPD_POWER_PRSNT_OPTION BIT(0)
> +#define XLNX_MMI_USB_TX_DEEMPH_DEF 0x8c45
>
> struct dwc3_xlnx;
>
> struct dwc3_xlnx_config {
> int (*pltfm_init)(struct dwc3_xlnx *data);
> + u32 tx_deemph;
> bool map_resource;
> };
>
> @@ -284,6 +286,7 @@ static const struct dwc3_xlnx_config versal_config = {
>
> static const struct dwc3_xlnx_config versal2_config = {
> .pltfm_init = dwc3_xlnx_init_versal2,
> + .tx_deemph = XLNX_MMI_USB_TX_DEEMPH_DEF,
> };
>
> static const struct of_device_id dwc3_xlnx_of_match[] = {
> @@ -303,10 +306,12 @@ static const struct of_device_id dwc3_xlnx_of_match[] = {
> };
> MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
>
> -static int dwc3_set_swnode(struct device *dev)
> +static int dwc3_set_swnode(struct dwc3_xlnx *priv_data)
> {
> + struct device *dev = priv_data->dev;
> + const struct dwc3_xlnx_config *config = priv_data->dwc3_config;
> struct device_node *np = dev->of_node, *dwc3_np;
> - struct property_entry props[2];
> + struct property_entry props[3];
> int prop_idx = 0, ret = 0;
>
> dwc3_np = of_get_compatible_child(np, "snps,dwc3");
> @@ -320,6 +325,10 @@ static int dwc3_set_swnode(struct device *dev)
> if (of_dma_is_coherent(dwc3_np))
> props[prop_idx++] = PROPERTY_ENTRY_U16("snps,gsbuscfg0-reqinfo",
> 0xffff);
> + if (config->tx_deemph)
We should set the tx_deemph to the DWC3_LCSR_TX_DEEMPH_UNSPECIFIED by
default and check against that instead.
> + props[prop_idx++] = PROPERTY_ENTRY_U32("snps,lcsr-tx-deemph",
> + config->tx_deemph);
> +
> of_node_put(dwc3_np);
>
> if (prop_idx)
> @@ -368,7 +377,7 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
> if (ret)
> goto err_clk_put;
>
> - ret = dwc3_set_swnode(dev);
> + ret = dwc3_set_swnode(priv_data);
> if (ret)
> goto err_clk_put;
>
> --
> 2.43.0
>
BR,
Thinh
^ permalink raw reply
* Re: [PATCH v2 2/4] usb: dwc3: xilinx: Introduce dwc3_xlnx_config for per-platform data
From: Thinh Nguyen @ 2026-04-18 0:32 UTC (permalink / raw)
To: Radhey Shyam Pandey
Cc: gregkh@linuxfoundation.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, michal.simek@amd.com, Thinh Nguyen,
p.zabel@pengutronix.de, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@amd.com
In-Reply-To: <20260330190304.1841593-3-radhey.shyam.pandey@amd.com>
On Tue, Mar 31, 2026, Radhey Shyam Pandey wrote:
> Replace the direct pltfm_init function pointer in struct dwc3_xlnx with
> a const pointer to a new struct dwc3_xlnx_config. This groups
> per-platform configuration in one place and allows future patches to add
> platform-specific fields (e.g. tx_deemph) without growing dwc3_xlnx.
>
> While at it, switch from of_match_node() to device_get_match_data() to
> simplify the match data lookup.
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> Changes for v2:
> - New patch, split from "Add Versal2 MMI USB 3.2 controller support".
> - Use device_get_match_data() instead of of_match_node().
> ---
> drivers/usb/dwc3/dwc3-xilinx.c | 28 ++++++++++++++++++++--------
> 1 file changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
> index f41b0da5e89d..bb59b56726e7 100644
> --- a/drivers/usb/dwc3/dwc3-xilinx.c
> +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> @@ -12,6 +12,7 @@
> #include <linux/clk.h>
> #include <linux/of.h>
> #include <linux/platform_device.h>
> +#include <linux/property.h>
> #include <linux/dma-mapping.h>
> #include <linux/gpio/consumer.h>
> #include <linux/of_platform.h>
> @@ -41,12 +42,18 @@
> #define XLNX_USB_FPD_POWER_PRSNT 0x80
> #define FPD_POWER_PRSNT_OPTION BIT(0)
>
> +struct dwc3_xlnx;
> +
> +struct dwc3_xlnx_config {
> + int (*pltfm_init)(struct dwc3_xlnx *data);
> +};
> +
> struct dwc3_xlnx {
> int num_clocks;
> struct clk_bulk_data *clks;
> struct device *dev;
> void __iomem *regs;
> - int (*pltfm_init)(struct dwc3_xlnx *data);
> + const struct dwc3_xlnx_config *dwc3_config;
> struct phy *usb3_phy;
> };
>
> @@ -241,14 +248,22 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
> return ret;
> }
>
> +static const struct dwc3_xlnx_config zynqmp_config = {
> + .pltfm_init = dwc3_xlnx_init_zynqmp,
> +};
> +
> +static const struct dwc3_xlnx_config versal_config = {
> + .pltfm_init = dwc3_xlnx_init_versal,
> +};
> +
> static const struct of_device_id dwc3_xlnx_of_match[] = {
> {
> .compatible = "xlnx,zynqmp-dwc3",
> - .data = &dwc3_xlnx_init_zynqmp,
> + .data = &zynqmp_config,
> },
> {
> .compatible = "xlnx,versal-dwc3",
> - .data = &dwc3_xlnx_init_versal,
> + .data = &versal_config,
> },
> { /* Sentinel */ }
> };
> @@ -284,7 +299,6 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
> struct dwc3_xlnx *priv_data;
> struct device *dev = &pdev->dev;
> struct device_node *np = dev->of_node;
> - const struct of_device_id *match;
> void __iomem *regs;
> int ret;
>
> @@ -296,9 +310,7 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
> if (IS_ERR(regs))
> return dev_err_probe(dev, PTR_ERR(regs), "failed to map registers\n");
>
> - match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
> -
> - priv_data->pltfm_init = match->data;
> + priv_data->dwc3_config = device_get_match_data(dev);
> priv_data->regs = regs;
> priv_data->dev = dev;
>
> @@ -314,7 +326,7 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - ret = priv_data->pltfm_init(priv_data);
> + ret = priv_data->dwc3_config->pltfm_init(priv_data);
Though this won't hit now, but we should check if dwc3_config exists
before accessing it.
BR,
Thinh
> if (ret)
> goto err_clk_put;
>
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH v2 0/4] usb: dwc3: xilinx: Add Versal2 MMI USB 3.2 controller support
From: Thinh Nguyen @ 2026-04-18 0:33 UTC (permalink / raw)
To: Pandey, Radhey Shyam
Cc: Thinh Nguyen, Radhey Shyam Pandey, gregkh@linuxfoundation.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
michal.simek@amd.com, p.zabel@pengutronix.de,
linux-usb@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@amd.com
In-Reply-To: <faf2421e-0d12-424d-abf8-ad490f5421ff@amd.com>
On Mon, Apr 13, 2026, Pandey, Radhey Shyam wrote:
> > On Tue, Mar 31, 2026, Radhey Shyam Pandey wrote:
> > > This series introduces support for the Multi-Media Integrated (MMI) USB
> > > 3.2 Dual-Role Device (DRD) controller on Xilinx Versal2 platforms.
> > >
> > > The controller supports SSP(10-Gbps), SuperSpeed, high-speed, full-speed
> > > and low-speed operation modes.
> > >
> > > USB2 and USB3 PHY support Physical connectivity via the Type-C
> > > connectivity. DWC3 wrapper IP IO space is in SLCR so reg is made
> > > optional.
> > >
> > > The driver is required for the clock, reset and platform specific
> > > initialization (coherency/TX_DEEMPH etc). In this initial version typec
> > > reversibility is not implemented and it is assumed that USB3 PHY TCA mux
> > > programming is done by MMI configuration data object (CDOs) and TI PD
> > > controller is configured using external tiva programmer on VEK385
> > > evaluation board.
> > >
> > > Changes for v2:
> > > - DT binding: fix MHz spacing (SI convention), reorder description
> > > before $ref in xlnx,usb-syscon, restore zynqmp-dwc3 example and add
> > > versal2-mmi-dwc3 example, fix node name for no-reg case, use 1/1
> > > address/size configuration and lowercase hex in syscon offsets.
> > > - Split config struct refactoring (device_get_match_data,dwc3_xlnx_config)
> > > into a separate preparatory patch.
> > > - Fix error message capitalization to lowercase per kernel convention.
> > > - Rename property snps,lcsr_tx_deemph to snps,lcsr-tx-deemph (hyphens).
> > > - Fix double space in comment and missing blank line in core.h.
> > > - Use platform data instead of of_device_is_compatible() check for
> > > deemphasis support.
> > >
> > > Link: https://urldefense.com/v3/__https://lore.kernel.org/all/20251119193036.2666877-1-radhey.shyam.pandey@amd.com/__;!!A4F2R9G_pg!YSeyY-bpQrMLqswAc1cWND5CSHvGFygPGMEMpR9amrRMnRFjYrFZktzbLzEzVZcQmOW34IUAfwRKHwy7B8p_ciUorWGJsA$
> > >
> > > Radhey Shyam Pandey (4):
> > > dt-bindings: usb: dwc3-xilinx: Add MMI USB support on Versal Gen2
> > > platform
> > > usb: dwc3: xilinx: Introduce dwc3_xlnx_config for per-platform data
> > > usb: dwc3: xilinx: Add Versal2 MMI USB 3.2 controller support
> > > usb: dwc3: xilinx: Add support to program MMI USB TX deemphasis
> > >
> > > .../devicetree/bindings/usb/dwc3-xilinx.yaml | 70 ++++++++++++++-
> > > drivers/usb/dwc3/core.c | 17 ++++
> > > drivers/usb/dwc3/core.h | 8 ++
> > > drivers/usb/dwc3/dwc3-xilinx.c | 89 +++++++++++++++----
> > > 4 files changed, 166 insertions(+), 18 deletions(-)
> > >
> > >
> > > base-commit: 46b513250491a7bfc97d98791dbe6a10bcc8129d
> > > --
> > > 2.43.0
> > >
> > Hi Radhey,
> >
> > Do you have plans to convert dwc3-xilinx to using the new flatten model?
> > The change you have here fits better for the new glue model.
> Thanks Thinh for the review.
>
> I have looked into the newly introduced flattened model introduced by
> commit 613a2e655d4d ("usb: dwc3: core: Expose core driver as library").
> Moving to that approach would require switching to the new DT binding
> and doing a large refactor.
>
> Given this series is already implemented and under review,
> I suggest we get it merged first, then evaluate the flattened models
> benefits and limitations and plan a follow‑up migration if it still
> makes sense. If there are no objections, I'll send out v3.
>
Sorry for the delay. I've provided some feedbacks to this series.
Thanks,
Thinh
^ permalink raw reply
* Re: [PATCH v4 3/4] dt-bindings: gpio: describe Waveshare GPIO controller
From: Rob Herring (Arm) @ 2026-04-18 0:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: dri-devel, Jessica Zhang, Conor Dooley, Simona Vetter, linux-gpio,
Conor Dooley, Javier Martinez Canillas, Maxime Ripard, Jagan Teki,
David Airlie, Maarten Lankhorst, Bartosz Golaszewski,
Neil Armstrong, Cong Yang, Jie Gan, Mark Brown, devicetree,
Krzysztof Kozlowski, linux-kernel, Linus Walleij, Ondrej Jirman,
Thomas Zimmermann, Liam Girdwood
In-Reply-To: <20260418-waveshare-dsi-touch-v4-3-b249f3e702bd@oss.qualcomm.com>
On Sat, 18 Apr 2026 02:16:22 +0300, Dmitry Baryshkov wrote:
> The Waveshare DSI TOUCH family of panels has separate on-board GPIO
> controller, which controls power supplies to the panel and the touch
> screen and provides reset pins for both the panel and the touchscreen.
> Also it provides a simple PWM controller for panel backlight.
>
> Add bindings for these GPIO controllers. As overall integration might be
> not very obvious (and it differs significantly from the bindings used by
> the original drivers), provide complete example with the on-board
> regulators and the DSI panel.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> .../bindings/gpio/waveshare,dsi-touch-gpio.yaml | 100 +++++++++++++++++++++
> 1 file changed, 100 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.example.dtb: panel@0 (waveshare,8.0-dsi-touch-a): compatible:0: 'waveshare,8.0-dsi-touch-a' is not one of ['anbernic,rg-ds-display-bottom', 'anbernic,rg-ds-display-top', 'chongzhou,cz101b4001', 'kingdisplay,kd101ne3-40ti', 'melfas,lmfbx101117480', 'radxa,display-10hd-ad001', 'radxa,display-8hd-ad002', 'taiguanck,xti05101-01a']
from schema $id: http://devicetree.org/schemas/display/panel/jadard,jd9365da-h3.yaml
Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.example.dtb: /example-0/dsi/panel@0: failed to match any schema with compatible: ['waveshare,8.0-dsi-touch-a', 'jadard,jd9365da-h3']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260418-waveshare-dsi-touch-v4-3-b249f3e702bd@oss.qualcomm.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH 3/4] arm64: dts: qcom: sdm630: describe adsp_mem region properly
From: Ekansh Gupta @ 2026-04-18 1:17 UTC (permalink / raw)
To: Nickolay Goppen, Konrad Dybcio, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming
In-Reply-To: <760729E8-7CD2-45DE-B3FB-7A28611E5EF6@mainlining.org>
On 17-04-2026 23:06, Nickolay Goppen wrote:
> I'm assigning this region in the fourth patch
Okay, I see. Thanks for pointing it out.
>
> 17 апреля 2026 г. 18:15:45 GMT+03:00, Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> wrote:
>> On 15-04-2026 15:22, Konrad Dybcio wrote:
>>> On 4/15/26 11:40 AM, Nickolay Goppen wrote:
>>>> Downstream [1] this region is marked as shared and reusable so
>>>> describe it that way.
>>>>
>>>> [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L448
>>>>
>>>> Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
>>>> ---
>>>
>>> +Ekansh some insight, please?
>>>
>>> We're giving away that memory via qcom_scm_assign_mem() anyway
>>> and I would assume that making it not-"no-map" could introduce issues
>>> when the OS tries to access that region
>>>
>> With the current version and the upcoming planned enhancements, I don't
>> see any major benefits of making this as not-"no-map".
>>
>> With posted enhancements[1], the plan is to qcom_scm_assign_mem() the
>> entire memory-region to lpass VMIDs. and un-assign it only during
>> fastrpc_rpmsg_remove(). There have been implementation in downstream
>> where this memory is dumped in case of SSR or audio PDR using minidump,
>> so marking it `reusable` might make sense there, but that dump logic is
>> not added upstream.
>>
>> Upon checking the DT, I see a bigger problem here, this memory-region
>> looks to me unused, it's not added under fastrpc adsp node(ref. [2]).
>> Please correct me if I am wrong about this point.
>>
>> [1]
>> https://lore.kernel.org/all/20260409062617.1182-1-jianping.li@oss.qualcomm.com/
>> [2]
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/lemans.dtsi#n7500
>>
>> //Ekansh
>>> Konrad
>>>
>>>
>>>> arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++-
>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
>>>> index 4b47efdb57b2..13094b5e9339 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
>>>> @@ -495,8 +495,9 @@ venus_region: venus@9f800000 {
>>>> };
>>>>
>>>> adsp_mem: adsp-region@f6000000 {
>>>> + compatible = "shared-dma-pool";
>>>> reg = <0x0 0xf6000000 0x0 0x800000>;
>>>> - no-map;
>>>> + reusable;
>>>> };
>>>>
>>>> qseecom_mem: qseecom-region@f6800000 {
>>>>
>
> Best regards
> Nickolay
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: imx8mq: Correct MIPI CSI clocks
From: Sebastian Krzyszkowiak @ 2026-04-18 1:12 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, shawnguo,
martin.kepplinger, Robby Cai
Cc: kernel, devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260417110200.753678-2-robby.cai@nxp.com>
On piątek, 17 kwietnia 2026 13:01:59 czas środkowoeuropejski letni Robby Cai
wrote:
> CSI capture may intermittently fail due to mismatched clock rates. The
> previous configuration violated the timing requirement stated in the
> i.MX8MQ Reference Manual:
>
> "The frequency of clk must be exactly equal to or greater than the RX
> byte clock coming from the RX DPHY."
>
> Update the clock configuration to ensure that the CSI core clock rate is
> equal to or greater than the incoming DPHY byte clock. The updated clock
> ratios are consistent with those used in NXP's downstream BSP.
I believe this is a misreading of the docs.
IMX8MQ_CLK_CSIX_PHY_REF refers to the UI pixel clock (clk_ui), not the RX DPHY
byte clock. All this change would do is to break streaming with more than 100
Mpixels per second / 1064 Mbps per MIPI lane.
As mentioned in the reference manual:
"The frequency of clk_ui must be such that the data received on the data_out
output is greater than or equal to the total bandwidth of the physical MIPI
interface. Clk_ui has no relationship requirement with regards to ‘clk’ other
than the bandwidth requirement mentioned previously."
> Fixes: bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge
> descriptions") Cc: stable@vger.kernel.org
> Signed-off-by: Robby Cai <robby.cai@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index
> 6a25e219832c..165716d08e64 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1377,7 +1377,7 @@ mipi_csi1: csi@30a70000 {
> assigned-clocks = <&clk
IMX8MQ_CLK_CSI1_CORE>,
> <&clk
IMX8MQ_CLK_CSI1_PHY_REF>,
> <&clk IMX8MQ_CLK_CSI1_ESC>;
> - assigned-clock-rates =
<266000000>, <333000000>, <66000000>;
> + assigned-clock-rates =
<133000000>, <100000000>, <66000000>;
> assigned-clock-parents = <&clk
IMX8MQ_SYS1_PLL_266M>,
> <&clk
IMX8MQ_SYS2_PLL_1000M>,
> <&clk
IMX8MQ_SYS1_PLL_800M>;
> @@ -1429,7 +1429,7 @@ mipi_csi2: csi@30b60000 {
> assigned-clocks = <&clk
IMX8MQ_CLK_CSI2_CORE>,
> <&clk
IMX8MQ_CLK_CSI2_PHY_REF>,
> <&clk IMX8MQ_CLK_CSI2_ESC>;
> - assigned-clock-rates =
<266000000>, <333000000>, <66000000>;
> + assigned-clock-rates =
<133000000>, <100000000>, <66000000>;
> assigned-clock-parents = <&clk
IMX8MQ_SYS1_PLL_266M>,
> <&clk
IMX8MQ_SYS2_PLL_1000M>,
> <&clk
IMX8MQ_SYS1_PLL_800M>;
^ permalink raw reply
* Re: [PATCH 4/4] arm64: dts: qcom: sdm630: assign adsp_mem region to ADSP FastRPC node
From: Ekansh Gupta @ 2026-04-18 1:20 UTC (permalink / raw)
To: Nickolay Goppen, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming
In-Reply-To: <20260415-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v1-4-03b475b29554@mainlining.org>
On 15-04-2026 15:10, Nickolay Goppen wrote:
> Downstream [1] ADSP FastRPC node has the adsp_mem region assigned, so
> assign it to the ADSP FastRPC node.
>
> [1]: https://github.com/xiaomi-sdm660/android_kernel_xiaomi_sdm660/blob/11-EAS/arch/arm/boot/dts/qcom/sdm660.dtsi#L1693
>
> Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
> ---
> arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index 13094b5e9339..19d80fbba57d 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -2456,6 +2456,7 @@ fastrpc {
> compatible = "qcom,fastrpc";
> qcom,glink-channels = "fastrpcglink-apps-dsp";
> label = "adsp";
> + memory-region = <&adsp_mem>;
This memory-region won't really be useful without proper VMID
configuration. Please add LPASS and ADSP_HEAP VMIDs.
Ref:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/lemans.dtsi#n7501
//Ekansh
> qcom,non-secure-domain;
> #address-cells = <1>;
> #size-cells = <0>;
>
^ permalink raw reply
* Re: [PATCH] arm: dts: allwinner: t113s mangopi: enable watchdog for reboot
From: Jernej Škrabec @ 2026-04-17 18:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Michal Piekos
Cc: devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
Michal Piekos
In-Reply-To: <20260412-t113-mangopi-reboot-hang-v1-1-5002cfa6e0cc@mmpsystems.pl>
Hi,
Dne nedelja, 12. april 2026 ob 19:42:10 Srednjeevropski poletni čas je Michal Piekos napisal(a):
> Reboot hangs on MangoPi MQ-R T113s because no restart handler is
> available.
>
> Enable the SoC watchdog whose driver registers a restart handler.
>
> Tested on MangoPi MQ-R T113s.
>
> Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> ---
> arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts
> index 8b3a75383816..f0232a5e903b 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts
> +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts
> @@ -33,3 +33,7 @@ rtl8189ftv: wifi@1 {
> interrupt-names = "host-wake";
> };
> };
> +
> +&wdt {
> + status = "okay";
> +};
Move this to sun8i-t113s.dtsi. All t113 boards have the same issue.
Watchdog should be always enabled on ARM.
Best regards,
Jernej
^ permalink raw reply
* [PATCH] arm64: dts: qcom: talos: Add memory-region for audio PD
From: Ekansh Gupta via B4 Relay @ 2026-04-18 5:48 UTC (permalink / raw)
To: konrad.dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, quic_bkumar, quic_chennak
Cc: linux-arm-msm, devicetree, linux-kernel, Ekansh Gupta
From: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Reserve memory region for audio PD dynamic loading and remote heap
requirements. Add the required VMID list for memory ownership
transfers.
Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index ff5afbfce2a4..c36917d6e0a9 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,qcs615-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
@@ -657,6 +658,11 @@ pil_gpu_mem: pil-gpu@97715000 {
reg = <0x0 0x97715000 0x0 0x2000>;
no-map;
};
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@97717000 {
+ reg = <0x0 0x97717000 0x0 0x800000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -5100,6 +5106,9 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
+ memory-region = <&adsp_rpc_remote_heap_mem>;
+ qcom,vmids = <QCOM_SCM_VMID_LPASS
+ QCOM_SCM_VMID_ADSP_HEAP>;
#address-cells = <1>;
#size-cells = <0>;
---
base-commit: c7275b05bc428c7373d97aa2da02d3a7fa6b9f66
change-id: 20260418-talosaudio-b8ecf8b9a1b3
Best regards,
--
Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
^ permalink raw reply related
* [PATCH] arm64: dts: qcom: hamoa: add audio PD remote heap region
From: Ekansh Gupta via B4 Relay @ 2026-04-18 6:08 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Bharath Kumar, Chenna Kesava Raju, linux-arm-msm, devicetree,
linux-kernel, Ekansh Gupta
From: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Reference the reserved memory region for audio PD dynamic loading
and remote heap requirements. Add the required VMID list for memory
ownership transfers.
Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 051dee076416..3a0717d49990 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -4371,6 +4372,9 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
+ memory-region = <&adsp_rpc_remote_heap_mem>;
+ qcom,vmids = <QCOM_SCM_VMID_LPASS
+ QCOM_SCM_VMID_ADSP_HEAP>;
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
---
base-commit: c7275b05bc428c7373d97aa2da02d3a7fa6b9f66
change-id: 20260418-hamoaaudio-914a6369a94d
Best regards,
--
Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: input: Add PixArt PAJ7620 gesture sensor
From: Harpreet Saini @ 2026-04-18 6:22 UTC (permalink / raw)
To: Rob Herring, linux-input, devicetree, linux-kernel
Cc: Dmitry Torokhov, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260418062241.104697-1-sainiharpreet29@yahoo.com>
Add Device Tree bindings for Pixart PAJ7620 gesture sensor.
The sensor supports 9 hand gestures via I2C interface.
The binding include mandatory power supplies (vdd, vbus, vled)
and optional GPIO controller properties to describe the hardware's
ability to repurpose SPI pins opeating in I2C mode.
Signed-off-by: Harpreet Saini <sainiharpreet29@yahoo.com>
---
.../bindings/input/pixart,paj7620.yaml | 79 +++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
2 files changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/pixart,paj7620.yaml
diff --git a/Documentation/devicetree/bindings/input/pixart,paj7620.yaml b/Documentation/devicetree/bindings/input/pixart,paj7620.yaml
new file mode 100644
index 000000000000..ad051cf641a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/pixart,paj7620.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/pixart,paj7620.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PixArt PAJ7620 Gesture Sensor
+
+maintainers:
+ - Harpreet Saini <sainiharpreet29@yahoo.com>
+
+description: |
+ The PixArt PAJ7620 is a gesture recognition sensor with an integrated
+ infrared LED and CMOS array. It communicates over an I2C interface and
+ provides gesture data via a dedicated interrupt pin.
+
+properties:
+ compatible:
+ const: pixart,paj7620
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply:
+ description: Main power supply.
+
+ vbus-supply:
+ description: I/O and I2C bus power supply.
+
+ vled-supply:
+ description: Power for the integrated IR LED.
+
+ linux,keycodes:
+ minItems: 9
+ maxItems: 9
+ description: |
+ List of keycodes mapping to the 9 supported gestures.
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - vdd-supply
+ - vbus-supply
+ - vled-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/input/input.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gesture@73 {
+ compatible = "pixart,paj7620";
+ reg = <0x73>;
+ interrupt-parent = <&gpio>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <®_3v3>;
+ vbus-supply = <®_1v8>;
+ vled-supply = <®_3v3>;
+ linux,keycodes = <KEY_UP KEY_DOWN KEY_LEFT KEY_RIGHT
+ KEY_ENTER KEY_BACK KEY_NEXT KEY_PREVIOUS
+ KEY_MENU>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ee7fd3cfe203..d73a0bf62b62 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1273,6 +1273,8 @@ patternProperties:
description: Pine64
"^pineriver,.*":
description: Shenzhen PineRiver Designs Co., Ltd.
+ "^pixart,.*":
+ description: PixArt Imaging Inc.
"^pixcir,.*":
description: PIXCIR MICROELECTRONICS Co., Ltd
"^plantower,.*":
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/2] Add PixArt PAJ7620 gesture sensor support
From: Harpreet Saini @ 2026-04-18 6:22 UTC (permalink / raw)
To: Rob Herring, linux-input, devicetree, linux-kernel
Cc: Dmitry Torokhov, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260418062241.104697-1-sainiharpreet29.ref@yahoo.com>
This series adds support for the PixArt PAJ7620 gesture sensor.
The first patch provides the DT bindings, and the second patch
implements the input driver.
Changes in v3:
- Moved sensor power-up and paj7620_init() to input open/close
callbacks
- Implemented dynamic keymap support via 'linux,keycodes' DT property
and enabled userspace adjustment via EVIOCSKEYCODE.
- Updated YAML bindings to include mandatory vdd, vbus, and vled
supplies.
- Added gpio-controller properties to YAML for hardware completeness.
- Verified with dt_binding_check and checkpatch.pl --strict.
Harpreet Saini (2):
dt-bindings: input: Add PixArt PAJ7620 gesture sensor
input: misc: Add PixArt PAJ7620 gesture sensor driver
.../bindings/input/pixart,paj7620.yaml | 79 ++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
drivers/input/misc/Kconfig | 12 +
drivers/input/misc/Makefile | 1 +
drivers/input/misc/paj7620.c | 338 ++++++++++++++++++
5 files changed, 432 insertions(+)
create mode 100644 Documentation/devicetree/bindings/input/
pixart,paj7620.yaml
create mode 100644 drivers/input/misc/paj7620.c
--
2.43.0
^ permalink raw reply
* [PATCH v3 2/2] input: misc: Add PixArt PAJ7620 gesture sensor driver
From: Harpreet Saini @ 2026-04-18 6:22 UTC (permalink / raw)
To: Rob Herring, linux-input, devicetree, linux-kernel
Cc: Dmitry Torokhov, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260418062241.104697-1-sainiharpreet29@yahoo.com>
This driver adds support for the PixArt PAJ7620 gesture sensor.
It implements hand gesture recognition (up, down, left, right,
etc.) and reports them as standard input key events. The driver
includes power management support via Runtime PM.
Signed-off-by: Harpreet Saini <sainiharpreet29@yahoo.com>
---
drivers/input/misc/Kconfig | 12 ++
drivers/input/misc/Makefile | 1 +
drivers/input/misc/paj7620.c | 338 +++++++++++++++++++++++++++++++++++
3 files changed, 351 insertions(+)
create mode 100644 drivers/input/misc/paj7620.c
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 94a753fcb64f..de4206c297f2 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -453,6 +453,18 @@ config INPUT_KXTJ9
To compile this driver as a module, choose M here: the module will
be called kxtj9.
+config INPUT_PAJ7620
+ tristate "PixArt PAJ7620 Gesture Sensor"
+ depends on I2C
+ select REGMAP_I2C
+ help
+ Say Y here if you want to support the PixArt PAJ7620 gesture
+ sensor. This sensor supports 9 hand gestures and communicates
+ over the I2C bus.
+
+ To compile this driver as a module, choose M here: the
+ module will be called paj7620.
+
config INPUT_POWERMATE
tristate "Griffin PowerMate and Contour Jog support"
depends on USB_ARCH_HAS_HCD
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 415fc4e2918b..dec8b8d0cdf4 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_INPUT_PF1550_ONKEY) += pf1550-onkey.o
obj-$(CONFIG_INPUT_PM8941_PWRKEY) += pm8941-pwrkey.o
obj-$(CONFIG_INPUT_PM8XXX_VIBRATOR) += pm8xxx-vibrator.o
obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o
+obj-$(CONFIG_INPUT_PAJ7620) += paj7620.o
obj-$(CONFIG_INPUT_POWERMATE) += powermate.o
obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o
obj-$(CONFIG_INPUT_PWM_VIBRA) += pwm-vibra.o
diff --git a/drivers/input/misc/paj7620.c b/drivers/input/misc/paj7620.c
new file mode 100644
index 000000000000..8738c174bcc1
--- /dev/null
+++ b/drivers/input/misc/paj7620.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PixArt PAJ7620 Gesture Sensor - Input driver
+ *
+ * Copyright (C) 2026 Harpreet Saini <sainiharpreet29@yahoo.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+/* Registers */
+#define PAJ7620_REG_BANK_SEL 0xEF
+#define PAJ7620_REG_GES_RESULT1 0x43
+#define PAJ7620_REG_GES_RESULT2 0x44
+#define PAJ7620_REG_SLEEP_BANK0 0x65
+#define PAJ7620_REG_SLEEP_BANK1 0x05
+#define PAJ7620_REG_AUTO_STANDBY 0x073
+
+/* Gesture bits */
+#define PAJ_UP BIT(0)
+#define PAJ_DOWN BIT(1)
+#define PAJ_LEFT BIT(2)
+#define PAJ_RIGHT BIT(3)
+#define PAJ_FORWARD BIT(4)
+#define PAJ_BACKWARD BIT(5)
+#define PAJ_CLOCKWISE BIT(6)
+#define PAJ_ANTICLOCK BIT(7)
+#define PAJ_WAVE BIT(8)
+#define PAJ_MAX_GESTURES 9
+
+struct paj7620_data {
+ struct i2c_client *client;
+ struct regmap *regmap;
+ struct input_dev *idev;
+ struct regulator_bulk_data supplies[3];
+ u32 keymap[PAJ_MAX_GESTURES];
+};
+
+/*
+ * The following arrays contain undocumented register sequences required to
+ * initialize the sensor's internal DSP and gesture engine.
+ * These were derived from vendor reference code and verified via testing.
+ */
+static const struct reg_sequence init_register[] = {
+ { 0xEF, 0x00 }, { 0x37, 0x07 }, { 0x38, 0x17 }, { 0x39, 0x06 },
+ { 0x41, 0x00 }, { 0x42, 0x00 }, { 0x46, 0x2D }, { 0x47, 0x0F },
+ { 0x48, 0x3C }, { 0x49, 0x00 }, { 0x4A, 0x1E }, { 0x4C, 0x20 },
+ { 0x51, 0x10 }, { 0x5E, 0x10 }, { 0x60, 0x27 }, { 0x80, 0x42 },
+ { 0x81, 0x44 }, { 0x82, 0x04 }, { 0x8B, 0x01 }, { 0x90, 0x06 },
+ { 0x95, 0x0A }, { 0x96, 0x0C }, { 0x97, 0x05 }, { 0x9A, 0x14 },
+ { 0x9C, 0x3F }, { 0xA5, 0x19 }, { 0xCC, 0x19 }, { 0xCD, 0x0B },
+ { 0xCE, 0x13 }, { 0xCF, 0x64 }, { 0xD0, 0x21 }, { 0xEF, 0x01 },
+ { 0x02, 0x0F }, { 0x03, 0x10 }, { 0x04, 0x02 }, { 0x25, 0x01 },
+ { 0x27, 0x39 }, { 0x28, 0x7F }, { 0x29, 0x08 }, { 0x3E, 0xFF },
+ { 0x5E, 0x3D }, { 0x65, 0x96 }, { 0x67, 0x97 }, { 0x69, 0xCD },
+ { 0x6A, 0x01 }, { 0x6D, 0x2C }, { 0x6E, 0x01 }, { 0x72, 0x01 },
+ { 0x73, 0x35 }, { 0x74, 0x00 }, { 0x77, 0x01 },
+};
+
+/*
+ * Specific configuration overrides required to enable the internal
+ * 8-gesture state machine.
+ */
+static const struct reg_sequence init_gesture_array[] = {
+ { 0xEF, 0x00 }, { 0x41, 0x00 }, { 0x42, 0x00 }, { 0xEF, 0x00 },
+ { 0x48, 0x3C }, { 0x49, 0x00 }, { 0x51, 0x10 }, { 0x83, 0x20 },
+ { 0x9F, 0xF9 }, { 0xEF, 0x01 }, { 0x01, 0x1E }, { 0x02, 0x0F },
+ { 0x03, 0x10 }, { 0x04, 0x02 }, { 0x41, 0x40 }, { 0x43, 0x30 },
+ { 0x65, 0x96 }, { 0x66, 0x00 }, { 0x67, 0x97 }, { 0x68, 0x01 },
+ { 0x69, 0xCD }, { 0x6A, 0x01 }, { 0x6B, 0xB0 }, { 0x6C, 0x04 },
+ { 0x6D, 0x2C }, { 0x6E, 0x01 }, { 0x74, 0x00 }, { 0xEF, 0x00 },
+ { 0x41, 0xFF }, { 0x42, 0x01 },
+};
+
+static const struct reg_sequence paj7620_suspend_regs[] = {
+ { PAJ7620_REG_BANK_SEL, 0x00 },
+ { PAJ7620_REG_SLEEP_BANK0, 0x01 },
+ { PAJ7620_REG_BANK_SEL, 0x01 },
+ { PAJ7620_REG_SLEEP_BANK1, 0x01 },
+};
+
+static void paj7620_report_keys(struct paj7620_data *data, int gesture)
+{
+ int i;
+
+ for (i = 0; i < PAJ_MAX_GESTURES; i++) {
+ if (gesture & BIT(i)) {
+ int key = data->keymap[i];
+
+ input_report_key(data->idev, key, 1);
+ input_sync(data->idev);
+ input_report_key(data->idev, key, 0);
+ input_sync(data->idev);
+ }
+ }
+}
+
+static irqreturn_t paj7620_irq_thread(int irq, void *ptr)
+{
+ struct paj7620_data *data = ptr;
+ unsigned int g1, g2;
+ int error;
+
+ /* 2. RUNTIME PM: Force awake to read registers */
+ pm_runtime_get_sync(&data->client->dev);
+
+ regmap_write(data->regmap, PAJ7620_REG_BANK_SEL, 0);
+ error = regmap_read(data->regmap, PAJ7620_REG_GES_RESULT1, &g1);
+ error |= regmap_read(data->regmap, PAJ7620_REG_GES_RESULT2, &g2);
+
+ if (!error && (g1 || g2))
+ paj7620_report_keys(data, (g2 << 8) | g1);
+
+ pm_runtime_mark_last_busy(&data->client->dev);
+ pm_runtime_put_autosuspend(&data->client->dev);
+
+ return IRQ_HANDLED;
+}
+
+static int paj7620_init(struct paj7620_data *data)
+{
+ int state = 0, error, i;
+
+ /* 1. Wake-up sequence: Read register 0x00 until it returns 0x20 */
+ for (i = 0; i < 10; i++) {
+ error = regmap_read(data->regmap, 0x00, &state);
+ if (error >= 0 && state == 0x20)
+ break;
+ usleep_range(1000, 2000);
+ }
+
+ if (state != 0x20) {
+ dev_err(&data->client->dev, "Sensor wake-up failed (0x%02x)\n", state);
+ return -ENODEV;
+ }
+
+ /* 2. Blast full register array into PAJ7620 instantly */
+ error = regmap_multi_reg_write(data->regmap, init_register,
+ ARRAY_SIZE(init_register));
+ if (error < 0) {
+ dev_err(&data->client->dev, "Multi-reg write failed (%d)\n", error);
+ return error;
+ }
+
+ error = regmap_write(data->regmap, PAJ7620_REG_BANK_SEL, 0x00);
+ if (error < 0)
+ return error;
+
+ error = regmap_multi_reg_write(data->regmap, init_gesture_array,
+ ARRAY_SIZE(init_gesture_array));
+ if (error < 0) {
+ dev_err(&data->client->dev, "Multi-reg write failed (%d)\n", error);
+ return error;
+ }
+
+ return 0;
+}
+
+static int paj7620_input_open(struct input_dev *idev)
+{
+ int error;
+ struct paj7620_data *data = input_get_drvdata(idev);
+
+ error = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies);
+ if (error)
+ return error;
+
+ error = paj7620_init(data);
+ if (error) {
+ regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
+ return error;
+ }
+
+ return 0;
+}
+
+static void paj7620_input_close(struct input_dev *idev)
+{
+ struct paj7620_data *data = input_get_drvdata(idev);
+
+ regmap_multi_reg_write(data->regmap, paj7620_suspend_regs,
+ ARRAY_SIZE(paj7620_suspend_regs));
+
+ regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
+}
+
+static int paj7620_runtime_suspend(struct device *dev)
+{
+ int error;
+ struct paj7620_data *data = dev_get_drvdata(dev);
+
+ error = regmap_write(data->regmap, PAJ7620_REG_BANK_SEL, 0x01);
+ if (error)
+ return error;
+
+ error = regmap_write(data->regmap, PAJ7620_REG_AUTO_STANDBY, 0x30);
+ if (error)
+ return error;
+
+ return 0;
+}
+
+static int paj7620_runtime_resume(struct device *dev)
+{
+ int error;
+ struct paj7620_data *data = dev_get_drvdata(dev);
+
+ error = regmap_write(data->regmap, PAJ7620_REG_BANK_SEL, 0x01);
+ if (error)
+ return error;
+
+ error = regmap_write(data->regmap, PAJ7620_REG_AUTO_STANDBY, 0x00);
+ if (error)
+ return error;
+
+ error = regmap_write(data->regmap, PAJ7620_REG_BANK_SEL, 0x00);
+ if (error)
+ return error;
+
+ usleep_range(1000, 2000); // Stabilization delay (1ms minimum)
+ return 0;
+}
+
+static const struct dev_pm_ops paj7620_pm_ops = {
+ SET_RUNTIME_PM_OPS(paj7620_runtime_suspend, paj7620_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+};
+
+static const struct regmap_config paj7620_reg_config = {
+ .reg_bits = 8, .val_bits = 8, .max_register = 0xEF,
+};
+
+static void paj7620_disable_pm(void *dev)
+{
+ pm_runtime_disable(dev);
+ pm_runtime_dont_use_autosuspend(dev);
+}
+
+static int paj7620_probe(struct i2c_client *client)
+{
+ struct paj7620_data *data;
+ int error, i;
+
+ data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->client = client;
+ i2c_set_clientdata(client, data);
+
+ data->supplies[0].supply = "vdd";
+ data->supplies[1].supply = "vbus";
+ data->supplies[2].supply = "vled";
+
+ error = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(data->supplies), data->supplies);
+ if (error)
+ return dev_err_probe(&client->dev, error, "Failed to get regulators\n");
+
+ error = device_property_read_u32_array(&client->dev, "linux,keycodes",
+ data->keymap, ARRAY_SIZE(data->keymap));
+
+ if (error) {
+ data->keymap[0] = KEY_UP;
+ data->keymap[1] = KEY_DOWN;
+ data->keymap[2] = KEY_LEFT;
+ data->keymap[3] = KEY_RIGHT;
+ data->keymap[4] = KEY_ENTER;
+ data->keymap[5] = KEY_BACK;
+ data->keymap[6] = KEY_NEXT;
+ data->keymap[7] = KEY_PREVIOUS;
+ data->keymap[8] = KEY_MENU;
+ }
+
+ data->regmap = devm_regmap_init_i2c(client, &paj7620_reg_config);
+ if (IS_ERR(data->regmap))
+ return PTR_ERR(data->regmap);
+
+ data->idev = devm_input_allocate_device(&client->dev);
+ if (!data->idev)
+ return -ENOMEM;
+
+ data->idev->name = "PAJ7620 Gesture Sensor";
+ data->idev->id.bustype = BUS_I2C;
+ data->idev->open = paj7620_input_open;
+ data->idev->close = paj7620_input_close;
+ data->idev->keycode = data->keymap;
+ data->idev->keycodemax = ARRAY_SIZE(data->keymap);
+ data->idev->keycodesize = sizeof(u32);
+
+ for (i = 0; i < ARRAY_SIZE(data->keymap); i++)
+ input_set_capability(data->idev, EV_KEY, data->keymap[i]);
+
+ input_set_drvdata(data->idev, data);
+
+ error = input_register_device(data->idev);
+ if (error)
+ return error;
+
+ pm_runtime_set_active(&client->dev);
+ pm_runtime_enable(&client->dev);
+ pm_runtime_set_autosuspend_delay(&client->dev, 2000);
+ pm_runtime_use_autosuspend(&client->dev);
+
+ error = devm_add_action_or_reset(&client->dev, paj7620_disable_pm, &client->dev);
+ if (error)
+ return error;
+
+ return devm_request_threaded_irq(&client->dev, client->irq,
+ NULL, paj7620_irq_thread,
+ IRQF_ONESHOT, "paj7620",
+ data);
+}
+
+static const struct of_device_id paj7620_of_match[] = {
+ { .compatible = "pixart,paj7620" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, paj7620_of_match);
+
+static struct i2c_driver paj7620_driver = {
+ .driver = {
+ .name = "paj7620",
+ .of_match_table = paj7620_of_match,
+ .pm = &paj7620_pm_ops,
+ },
+ .probe = paj7620_probe,
+};
+module_i2c_driver(paj7620_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Harpreet Saini");
+MODULE_DESCRIPTION("PAJ7620 Gesture Input Driver");
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/3] Describe IMEM on Eliza
From: Alexander Koskovich @ 2026-04-18 10:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: devicetree, linux-kernel, linux-arm-msm, Alexander Koskovich,
Krzysztof Kozlowski, Konrad Dybcio
Add a compatible and describe the IMEM for the Eliza SoC.
Sort nodes by unit address, this can be applied separate of the other two.
I kept the IPA modem tables in eliza.dtsi per Konrad's feedback about the IMEM
containing it regardless of SKU.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
Changes in v3:
- pilreloc-sram -> pil-reloc-sram (Konrad)
- Link to v2: https://lore.kernel.org/r/20260416-eliza-imem-v2-0-fb7a71123451@pm.me
Changes in v2:
- Fix sorting of nodes in eliza.dtsi
- Link to v1: https://lore.kernel.org/r/20260415-eliza-imem-v1-0-4a90e8683799@pm.me
---
Alexander Koskovich (3):
arm64: dts: qcom: eliza: Sort nodes by unit address
dt-bindings: sram: Document qcom,eliza-imem
arm64: dts: qcom: eliza: Add IMEM node
Documentation/devicetree/bindings/sram/sram.yaml | 1 +
arch/arm64/boot/dts/qcom/eliza.dtsi | 94 ++++++++++++++----------
2 files changed, 58 insertions(+), 37 deletions(-)
---
base-commit: 936c21068d7ade00325e40d82bfd2f3f29d9f659
change-id: 20260415-eliza-imem-e791f44abf1b
Best regards,
--
Alexander Koskovich <akoskovich@pm.me>
^ permalink raw reply
* [PATCH v3 1/3] arm64: dts: qcom: eliza: Sort nodes by unit address
From: Alexander Koskovich @ 2026-04-18 10:39 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: devicetree, linux-kernel, linux-arm-msm, Alexander Koskovich,
Krzysztof Kozlowski, Konrad Dybcio
In-Reply-To: <20260418-eliza-imem-v3-0-bfbd499b6e77@pm.me>
Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move
few nodes in Eliza DTSI to fix that.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
arch/arm64/boot/dts/qcom/eliza.dtsi | 74 ++++++++++++++++++-------------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
index 4a7a0ac40ce6..6fa5679c1a62 100644
--- a/arch/arm64/boot/dts/qcom/eliza.dtsi
+++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
@@ -662,16 +662,16 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
};
};
- config_noc: interconnect@1600000 {
- compatible = "qcom,eliza-cnoc-cfg";
- reg = <0x0 0x01600000 0x0 0x5200>;
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,eliza-cnoc-main";
+ reg = <0x0 0x01500000 0x0 0x16080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
- cnoc_main: interconnect@1500000 {
- compatible = "qcom,eliza-cnoc-main";
- reg = <0x0 0x01500000 0x0 0x16080>;
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,eliza-cnoc-cfg";
+ reg = <0x0 0x01600000 0x0 0x5200>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
@@ -862,13 +862,6 @@ tcsr: clock-controller@1fbf000 {
#reset-cells = <1>;
};
- lpass_ag_noc: interconnect@7e40000 {
- compatible = "qcom,eliza-lpass-ag-noc";
- reg = <0x0 0x07e40000 0x0 0xe080>;
- qcom,bcm-voters = <&apps_bcm_voter>;
- #interconnect-cells = <2>;
- };
-
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,eliza-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
@@ -883,6 +876,13 @@ lpass_lpicx_noc: interconnect@7420000 {
#interconnect-cells = <2>;
};
+ lpass_ag_noc: interconnect@7e40000 {
+ compatible = "qcom,eliza-lpass-ag-noc";
+ reg = <0x0 0x07e40000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,eliza-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x40000>,
@@ -1005,6 +1005,30 @@ spmi_bus1: spmi@c432000 {
};
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,eliza-tlmm";
+ reg = <0x0 0x0f100000 0x0 0xf00000>;
+
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 184>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart14_default: qup-uart14-default-state {
+ /* TX, RX */
+ pins = "gpio18", "gpio19";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
@@ -1319,30 +1343,6 @@ cpufreq_hw: cpufreq@17d91000 {
#clock-cells = <1>;
};
- tlmm: pinctrl@f100000 {
- compatible = "qcom,eliza-tlmm";
- reg = <0x0 0x0f100000 0x0 0xf00000>;
-
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- gpio-ranges = <&tlmm 0 0 184>;
- wakeup-parent = <&pdc>;
-
- qup_uart14_default: qup-uart14-default-state {
- /* TX, RX */
- pins = "gpio18", "gpio19";
- function = "qup2_se5";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
gem_noc: interconnect@24100000 {
compatible = "qcom,eliza-gem-noc";
reg = <0x0 0x24100000 0x0 0x163080>;
--
2.53.0
^ permalink raw reply related
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