* Re: [PATCH v2 4/4] arm64: dts: amlogic: t7: Add clk measure support
From: Neil Armstrong @ 2026-04-20 8:52 UTC (permalink / raw)
To: Jian Hu, Ronald Claveau
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
In-Reply-To: <64cde9f6-4f28-4ba7-8362-aac28887ff22@amlogic.com>
On 4/20/26 05:25, Jian Hu wrote:
> Hi Ronald,
>
>
> Thanks for your review.
>
> On 4/17/2026 5:48 PM, Ronald Claveau wrote:
>> [ EXTERNAL EMAIL ]
>>
>> Hello Jian,
>>
>> On 4/15/26 10:33 AM, Jian Hu via B4 Relay wrote:
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the clock measure device to the T7 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> index 7fe72c94ed62..cec2ea74850d 100644
>>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> @@ -701,6 +701,11 @@ pwm_ao_cd: pwm@60000 {
>>> status = "disabled";
>>> };
>>>
>>> + clock-measurer@48000 {
>>> + compatible = "amlogic,t7-clk-measure";
>>> + reg = <0x0 0x48000 0x0 0x1c>;
>>> + };
>>> +
>> Can you please order by reg, it should be between pwm_ao_gh and pwm_ab.
>> Thank you.
>
>
> According to the "Order of Nodes" chapter in Documentation/devicetree/bindings/dts-coding-style.rst,
>
> nodes of the same type should be grouped together, and this takes higher priority.
>
> So I have placed the clock-measure node after all PWM nodes to avoid splitting the PWM group.
This is not something we ever followed in the past, and I don't think it makes sens here.
"""
Alternatively for some subarchitectures, nodes of the same type can be
grouped together, e.g. all I2C controllers one after another even if this
breaks unit address ordering.
"""
This doesn't apply here, so order strictly by address.
Neil
>
>
> Best regards,
>
> Jian
>
^ permalink raw reply
* Re: [PATCH v5 04/13] arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node
From: Bartosz Golaszewski @ 2026-04-20 8:53 UTC (permalink / raw)
To: Harshal Dev
Cc: Brian Masney, Neeraj Soni, Gaurav Kashyap, linux-arm-msm,
linux-crypto, devicetree, linux-kernel, Krzysztof Kozlowski,
Konrad Dybcio, Kuldeep Singh, Krzysztof Kozlowski, Herbert Xu,
David S. Miller, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio, Abel Vesa, Manivannan Sadhasivam,
cros-qcom-dts-watchers, Eric Biggers, Dmitry Baryshkov,
Jingyi Wang, Tengfei Fan, Bartosz Golaszewski, David Wronek,
Luca Weiss, Neil Armstrong, Melody Olvera, Alexander Koskovich,
Abel Vesa
In-Reply-To: <20260416-qcom_ice_power_and_clk_vote-v5-4-5ccf5d7e2846@oss.qualcomm.com>
On Thu, 16 Apr 2026 13:59:21 +0200, Harshal Dev
<harshal.dev@oss.qualcomm.com> said:
> Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
> for its own resources. Before accessing ICE hardware during probe, to
> avoid potential unclocked register access issues (when clk_ignore_unused
> is not passed on the kernel command line), in addition to the 'core' clock
> the 'iface' clock should also be turned on by the driver. This can only be
> done if the UFS_PHY_GDSC power domain is enabled. Specify both the
> UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans.
>
> Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index fe6e76351823..d83cad26a20f 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -2758,7 +2758,11 @@ ice: crypto@1d88000 {
> compatible = "qcom,sa8775p-inline-crypto-engine",
> "qcom,inline-crypto-engine";
> reg = <0x0 0x01d88000 0x0 0x18000>;
> - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>;
> + clock-names = "core",
> + "iface";
> + power-domains = <&gcc UFS_PHY_GDSC>;
> };
>
> cryptobam: dma-controller@1dc4000 {
>
> --
> 2.34.1
>
>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 2/2] iio: adc: hx711: add support for HX710B
From: Andy Shevchenko @ 2026-04-20 9:03 UTC (permalink / raw)
To: Piyush Patle
Cc: jic23, ak, dlechner, nuno.sa, andy, robh, krzk+dt, conor+dt,
linux-iio, devicetree, linux-kernel
In-Reply-To: <20260419174654.683692-3-piyushpatle228@gmail.com>
On Sun, Apr 19, 2026 at 11:16:40PM +0530, Piyush Patle wrote:
> The HX711 uses trailing SCK pulses after each 24-bit conversion to
> select the channel and gain for the next measurement: 1 pulse gives
> channel A at gain 128, 2 pulses give channel B at gain 32, and 3 pulses
> give channel A at gain 64.
>
> The HX710B works differently: gain is fixed at 128 and the trailing
> pulses select only the channel. One trailing pulse selects the
> differential input (channel 0, 10 SPS) and two trailing pulses select
> the DVDD-AVDD supply monitor (channel 1, 40 SPS).
>
> Refactor the driver around a per-chip hx711_chip_info structure so both
> variants can share the same core. Each chip provides its own
> iio_chan_spec array and iio_info pointer. The HX710B stores per-channel
> trailing pulse counts in chan->address (1 for channel 0, 2 for
> channel 1) instead of a separate array. A bool fixed_gain flag and
> fixed_gain_val field in hx711_chip_info distinguish the fixed-gain path
> from the HX711's user-selectable gain path without conflating unrelated
> properties. The HX710B differential input channel is described with
> .differential=1 and .channel2=1 as required by the IIO ABI.
>
> Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
> ---
> Changes in v2:
> - Fix pulse count bug: hx710b values were {25, 26} (total SCK cycles);
> corrected to {1, 2} (trailing-only, hx711_read() clocks 24 data bits)
Which questions how it was tested...
> - Add .differential = 1 and .channel2 = 1 to HX710B channel 0
> - Move trailing pulse counts from a separate array to chan->address
> (1 for ch0, 2 for ch1); remove chan_pulse_count / num_chan_pulses
> - Replace chan_pulse_count != NULL tests with dedicated bool fixed_gain
> flag; add fixed_gain_val field to hx711_chip_info
> - Add const struct iio_info *iio_info to hx711_chip_info; probe sets
> indio_dev->info = chip_info->iio_info directly
> - Remove NULL check after device_get_match_data()
> - Remove reset_channel from hx711_chip_info (always 0; use literal)
> - Change hx711_reset_read() and hx710b_set_channel() to take
> const struct iio_chan_spec * instead of int chan
> - Revert hx711_data struct member alignment noise
> - Restore trailing blank line at end of file (unrelated removal reverted)
> - Sort of_device_id entries alphabetically (hx710b before hx711)
> - Expand commit message to explain HX711 vs HX710B trailing-pulse model
> - Restore file header to mention weight sensor modules
...
> config HX711
> - tristate "AVIA HX711 ADC for weight cells"
> + tristate "AVIA HX711 and HX710B ADC"
This won't scale. Better to put something like "and compatible".
Also use plural "ADCs".
> depends on GPIOLIB
> select IIO_BUFFER
> select IIO_TRIGGERED_BUFFER
> help
> - If you say yes here you get support for AVIA HX711 ADC which is used
> - for weigh cells
> + If you say yes here you get support for AVIA HX711 and HX710B ADCs
> + which are used for bridge sensors such as weigh cells.
Usually for the less churn in the future we list them one per line. This
will give easier understanding of what is supported (keep them also sorted).
If you say Y here you get support for the following AVIA ADCs:
- HX710B
- HX711
which are used for bridge sensors such as weigh cells.
> This driver uses two GPIOs, one acts as the clock and controls the
> channel selection and gain, the other one is used for the measurement
> data
>
> + The HX710B is a variant with fixed gain and a different channel
> + selection scheme.
> +
> Currently the raw value is read from the chip and delivered.
> To get an actual weight one needs to subtract the
> zero offset and multiply by a scale factor.
...
> - * HX711: analog to digital converter for weight sensor module
> + * HX711/HX710B: ADC driver for weight sensor modules
Use same as in Kconfig:
* HX711 and compatible ADCs driver for weight sensor modules
...
> +/**
> + * struct hx711_chip_info - per-variant static configuration
> + * @name: IIO device name
> + * @channels: channel specification
> + * @num_channels: number of channels
> + * @iio_info: IIO info ops for this variant
> + * @fixed_gain: true if the variant has a fixed ADC gain (e.g. HX710B)
> + * @fixed_gain_val: the fixed gain value used to compute scale (when fixed_gain)
> + */
> +struct hx711_chip_info {
> + const char *name;
> + const struct iio_chan_spec *channels;
> + int num_channels;
Why signed?
> + const struct iio_info *iio_info;
> + bool fixed_gain;
> + int fixed_gain_val;
> +};
...
> struct hx711_data {
> struct device *dev;
> struct gpio_desc *gpiod_pd_sck;
> struct gpio_desc *gpiod_dout;
> int gain_set; /* gain set on device */
> int gain_chan_a; /* gain for channel A */
> + int channel_set; /* HX710B current channel */
> + int scale; /* HX710B fixed scale */
Check if those need to be signed.
> + const struct hx711_chip_info *chip_info;
> struct mutex lock;
> }
...
> - for (i = 0; i < hx711_get_gain_to_pulse(hx711_data->gain_set); i++)
> + for (i = 0; i < trailing_pulses; i++)
If 'i' is used only once here, it can be converted to
for (unsigned int i = 0; i < trailing_pulses; i++)
> hx711_cycle(hx711_data);
>
> return value;
...
> + .num_channels = ARRAY_SIZE(hx711_chan_spec),
You also probably want to revisit inclusion block. At least follow IWYU in the
code you added here, exempli gratia include array_size.h and types.h if not yet
included.
...
> hx711_data->clock_frequency = 400000;
Sounds like I2C or SD standard speed :-)
Not sure, but can be also converted to use 400 * HZ_PER_KHZ (from units.h)
in a separate change.
...
> hx711_data->data_ready_delay_ns =
> 1000000000 / hx711_data->clock_frequency;
Side note, in a separate change you can use constants from time.h, id est
NSEC_PER_SEC.
...
> static const struct of_device_id of_hx711_match[] = {
> - { .compatible = "avia,hx711", },
> + { .compatible = "avia,hx710b", .data = &hx710b_chip },
Please, split this to a separate change. So, first introduce the chip_info,
then add your device support using given infrastructure.
That said, you also can convert the driver to use guard()() from cleanup.h
in a separate change.
> + { .compatible = "avia,hx711", .data = &hx711_chip },
> { }
> };
...
> -MODULE_DESCRIPTION("HX711 bitbanging driver - ADC for weight cells");
Ah, this removes crucial information. So, this driver probably just needs to
use i2c_gpio?
> +MODULE_DESCRIPTION("HX711/HX710B GPIO ADC driver");
Use what is written in Kconfig.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: clock: qcom: Add QREF regulator supplies for glymur
From: Rob Herring (Arm) @ 2026-04-20 9:03 UTC (permalink / raw)
To: Qiang Yu
Cc: Konrad Dybcio, linux-clk, devicetree, Bjorn Andersson,
Conor Dooley, Michael Turquette, Krzysztof Kozlowski,
linux-arm-msm, Taniya Das, linux-kernel, Stephen Boyd
In-Reply-To: <20260420-vote_qref_in_tcsrcc-v2-1-589a23ae640a@oss.qualcomm.com>
On Mon, 20 Apr 2026 00:42:52 -0700, Qiang Yu wrote:
> Add regulator supply properties for the Glymur TCSR QREF/REFGEN blocks
> required by clkref clocks.
>
> The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common
> QREF TX/RPT/RX components, while SoC-specific topology and instance count
> differ. Document them here for qcom,glymur-tcsr.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8550-tcsr.yaml | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml: allOf:0: 'then' is a dependency of 'if'
hint: Keywords must be a subset of known json-schema keywords
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml: allOf:0: 'then' is a dependency of 'else'
hint: Keywords must be a subset of known json-schema keywords
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260420-vote_qref_in_tcsrcc-v2-1-589a23ae640a@oss.qualcomm.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH] dts: riscv: spacemit: k3: only keep spacemit,k1-i2c
From: Yixun Lan @ 2026-04-20 9:09 UTC (permalink / raw)
To: Troy Mitchell
Cc: Krzysztof Kozlowski, Sandie Cao, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, spacemit, linux-riscv, devicetree, linux-kernel,
kernel test robot
In-Reply-To: <DHXUQHVK4XRN.3CVZ3GH75L4L4@linux.spacemit.com>
Hi Troy,
On 16:50 Mon 20 Apr , Troy Mitchell wrote:
> On Mon Apr 20, 2026 at 4:44 PM CST, Krzysztof Kozlowski wrote:
> > On 20/04/2026 10:43, Krzysztof Kozlowski wrote:
> >> On 20/04/2026 10:39, Sandie Cao wrote:
> >>> Fix dtcheck issue: compatible:0: 'spacemit,k1-i2c' was expected
> >>
> >> Missing space after main commit msg.
> >>
> >>> Reported-by: kernel test robot <lkp@intel.com>
> >>> Closes: https://lore.kernel.org/r/202604140259.eKDaxKua-lkp@intel.com/
> >>>
> >
> > Also, the file reported in above warning DOES NOT EXIST (I checked
> > next-20260414).
> In Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml:
>
> properties:
> compatible:
> enum:
> - spacemit,k1-pinctrl
> - spacemit,k3-pinctrl
>
I think you refer to wrong file, which should be
Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
> So there's no reason to use k1-i2c. As far as I can tell, while they are the same IP,
> there are subtle differences between them.
>
But yes, the idea is correct, so NAK to this patch
> - Troy
--
Yixun Lan (dlan)
^ permalink raw reply
* [PATCH v4 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support
From: Joe Sandom via B4 Relay @ 2026-04-20 9:13 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Konrad Dybcio, Neil Armstrong, Dmitry Baryshkov,
Krzysztof Kozlowski
This series adds device tree support for the Thundercomm RB5Gen2
development kit, based on the Qualcomm QCS8550 chipset.
Patches 1-3 prepares for the RB5gen2 device tree by adding MHI register
regions and port labels to the PCIe controller nodes, as well as moving
common IPA properties into sm8550.dtsi. Then update the existing HDK
and QRD board files accordingly.
Patches 4-5 add the dt-bindings documentation and the board device tree
for the RB5Gen2. This initial submission covers the main board; the vision
mezzanine will be supported in a follow-up series.
Product page:
https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
Changes in v4:
- Renamed LT9611 regulator nodes from lt9611-regulator-* to
regulator-lt9611-* to follow standard naming convention
- Moved pmic-glink node before regulators to match alphabetical
ordering used by sm8550-hdk.dts
- Reordered sound dai-link sub-nodes: codec before cpu
- Added comma separation between pinctrl-0 phandle references
(lt9611 and tc9563 entries)
- Changed firmware paths from qcom/qcs8550/ to qcom/sm8550/ for
adsp, cdsp, modem, IPA and GPU to keep all firmware in the same
subdirectory
- Link to v3: https://lore.kernel.org/r/20260409-rb5gen2-dts-v3-0-be736355d4b4@axon.com
Changes in v3:
- Reworded MHI commit message to describe actual usage (debugfs
link_transition_count) per Neil's feedback
- Reordered pinctrl-0 before pinctrl-names file-wide per Konrad's
feedback
- Removed output-high from lt9611_rst_pin since the driver handles
reset sequencing
- Reordered tlmm pinctrl entries by GPIO number
- Changed bias-pull-up to bias-disable for regulator enable pins
(upd_1p05_en, upd_3p3_en) since these are active-high enables
- Added comments for gpio-reserved-ranges explaining GPIOs 32-35
are for NFC secure element and 36-39 for fingerprint sensor
- Removed max-sd-hs-hz override since upstream clock driver already
provides the correct 37.5MHz frequency
- Updated msi-map deletion rationale with root cause: Gunyah limits
ITS device mappings to two per root complex on SM8550
- Link to v2: https://lore.kernel.org/r/20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com
Changes in v2:
- Lowercase hex in MHI region definitions for pcie0 and pcie1 nodes +
vertical alignment
- Change pcie0 and pcie1 reg-names for one entry per line
- Ensured pcie port labels + changes to sm8550-hdk.dts and sm8550-qrd.dts
are done in a single commit
- Moved IPA gsi-loader and memory-region to sm8550.dtsi since they are common
properties. Reflect changes in sm8550-hdk.dts and sm8550-qrd.dts
- Removed usbhub_reset since this is not required
- Added swctrl-gpios property to wcn7850-pmu
- Split sw_ctrl_default gpio from bt_default grouping and referenced the
pinctrl separately
- Replaced upd_reset regulator-fixed with pinctrl and vddpe-3v3-supply
on pcie0
- Aligned firmware-name values vertically on the quote mark
- Changed cdsp, adsp and modem remoteprocs to .mbn file type instead of
.mdt
- Added remark in rb5gen2 dts commit explaining the rationale for
deleting msi-map in pcie0 and pcie1 nodes
- Link to v1: https://lore.kernel.org/r/20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com
---
Joe Sandom (5):
arm64: dts: qcom: sm8550: add PCIe MHI register regions
arm64: dts: qcom: sm8550: add PCIe port labels
arm64: dts: qcom: sm8550: move IPA properties to SoC device tree
dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board
arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1573 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 +-
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +-
6 files changed, 1602 insertions(+), 12 deletions(-)
---
base-commit: af241225893ac4933bb8f0615f2dfda8ea2326ce
change-id: 20260404-rb5gen2-dts-180cde0b716c
Best regards,
--
Joe Sandom <jsandom@axon.com>
^ permalink raw reply
* [PATCH v4 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
From: Joe Sandom via B4 Relay @ 2026-04-20 9:13 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Konrad Dybcio
In-Reply-To: <20260420-rb5gen2-dts-v4-0-b461909c2de8@axon.com>
From: Joe Sandom <jsandom@axon.com>
Add the MHI register regions to the pcie0 and pcie1 controller nodes
to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
via debugfs. The PCIe host driver uses this region to read the
link_transition_count from the MHI registers.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..055ca931c04859f3a312eb9921aeb7a8cc676822 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1964,8 +1964,14 @@ pcie0: pcie@1c00000 {
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
- <0 0x60100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
@@ -2138,8 +2144,14 @@ pcie1: pcie@1c08000 {
<0x0 0x40000000 0x0 0xf1d>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
- <0x0 0x40100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c0b000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/5] arm64: dts: qcom: sm8550: add PCIe port labels
From: Joe Sandom via B4 Relay @ 2026-04-20 9:13 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Neil Armstrong, Dmitry Baryshkov
In-Reply-To: <20260420-rb5gen2-dts-v4-0-b461909c2de8@axon.com>
From: Joe Sandom <jsandom@axon.com>
Add labels to the root port nodes (pcie0_port0, pcie1_port0) to
allow board DTS files to reference them for adding endpoint devices
to each pcie root port.
Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and
sm8550-qrd.dts to match the label rename in sm8550.dtsi.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index ee13e6136a8259d28540e718851e094f74ead278..e821b731bdc496c872703723df02ae9b9b0233b5 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1012,7 +1012,7 @@ &pcie0 {
status = "okay";
};
-&pcieport0 {
+&pcie0_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 2fb2e0be5e4c6b597f20f332cdf063daa2664205..cf63109ff7bf7b6fc827f108e22e82b8b04273c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -912,7 +912,7 @@ &pcie0 {
status = "okay";
};
-&pcieport0 {
+&pcie0_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 055ca931c04859f3a312eb9921aeb7a8cc676822..54308cbde40732da072177eab533582c155df590 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2098,7 +2098,7 @@ opp-16000000-3 {
};
};
- pcieport0: pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2300,7 +2300,7 @@ opp-32000000-4 {
};
};
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 3/5] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree
From: Joe Sandom via B4 Relay @ 2026-04-20 9:13 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Dmitry Baryshkov
In-Reply-To: <20260420-rb5gen2-dts-v4-0-b461909c2de8@axon.com>
From: Joe Sandom <jsandom@axon.com>
Move qcom,gsi-loader and memory-region properties from individual board
DTS files into the SoC DTSI, since these are common to all SM8550-based
boards.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index e821b731bdc496c872703723df02ae9b9b0233b5..b795589385520acd74eecc7701cab82f4f7da200 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -939,8 +939,6 @@ &i2c_master_hub_0 {
};
&ipa {
- qcom,gsi-loader = "self";
- memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sm8550/ipa_fws.mbn";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index cf63109ff7bf7b6fc827f108e22e82b8b04273c1..f2effa55d8197819175bfd5a89d2fddb20561548 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -818,8 +818,6 @@ fsa4480_sbu_mux: endpoint {
};
&ipa {
- qcom,gsi-loader = "self";
- memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sm8550/ipa_fws.mbn";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 54308cbde40732da072177eab533582c155df590..d292dfce6b66fff6cff918b8bd6ac0b9cd22c4b3 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2730,6 +2730,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
sram = <&ipa_modem_tables>;
status = "disabled";
--
2.34.1
^ permalink raw reply related
* [PATCH v4 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board
From: Joe Sandom via B4 Relay @ 2026-04-20 9:13 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Krzysztof Kozlowski
In-Reply-To: <20260420-rb5gen2-dts-v4-0-b461909c2de8@axon.com>
From: Joe Sandom <jsandom@axon.com>
Document the Qualcomm RB5gen2 from Thundercomm based on the
QCS8550 chipset from Qualcomm.
[1] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 1335a7bee397c46e8dc62806091531e32b7327d4..f9f8001e3e6b66e3a926255bdb15363f4c7c2b66 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1093,6 +1093,12 @@ properties:
- const: qcom,qcs8550
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,qcs8550-rb5gen2
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- ayaneo,pocket-s2
--
2.34.1
^ permalink raw reply related
* [PATCH v4 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Joe Sandom via B4 Relay @ 2026-04-20 9:13 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260420-rb5gen2-dts-v4-0-b461909c2de8@axon.com>
From: Joe Sandom <jsandom@axon.com>
The RB5gen2 is an embedded development platform for the
QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
This change implements the main board, the vision mezzanine
will be supported in a follow up patch.
The main board has the following features:
- Qualcomm Dragonwing QCS8550 SoC
- Adreno GPU 740
- Spectra ISP
- Adreno VPU 8550
- Adreno DPU 1295
- 1 x 1GbE Ethernet (USB Ethernet)
- WIFI 7 + Bluetooth 5.4
- 1 x USB 2.0 Micro B (Debug)
- 1 x USB 3.0 Type C (ADB, DP out)
- 2 x USB 3.0 Type A
- 1 x HDMI 1.4 Type A
- 1 x DP 1.4 Type C
- 2 x WSA8845 Speaker amplifiers
- 2 x Speaker connectors
- 1 x On Board PDM MIC
- Accelerometer + Gyro Sensor
- 96Boards compatible low-speed and high-speed connectors [1]
- 7 x LED indicators (4 user, 2 radio, 1 power)
- Buttons for power, volume up/down, force USB boot
- 3 x Dip switches
On-Board PMICs:
- PMK8550 2.1
- PM8550 2.0
- PM8550VS 2.0 x4
- PM8550VE 2.0
- PM8550B 2.0
- PMR735D 2.0
- PM8010 1.1 x2
Product Page: [2]
[1] https://www.96boards.org/specifications/
[2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
The default msi-map from sm8550.dtsi is deleted for both pcie0 and
pcie1. The QPS615 PCIe switch on each port exposes more than two
devices (1 USP + 3 DSPs), but Gunyah currently limits ITS device
mappings to two per root complex to save memory. With msi-map
present, the ITS MAPD command times out.
Deleting msi-map causes the DWC controller to fall back to its
internal iMSI-RX module, which handles MSIs without this limitation.
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1573 ++++++++++++++++++++++++++
2 files changed, 1574 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e73064194926096b98b9556a3207e8f24d72..f8c65771f76629d7fafee15ac8d7bb62cd24a20f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-rb5gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
new file mode 100644
index 0000000000000000000000000000000000000000..9df8dcd6c62b680ea7b6180489dddb6c6045486b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
@@ -0,0 +1,1573 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Axon Enterprise, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 RB5Gen2";
+ compatible = "qcom,qcs8550-rb5gen2", "qcom,qcs8550", "qcom,sm8550";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ clk40m: can-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */
+ /* Workaround is to use bit-banged I2C */
+ i2c_hub_3_gpio: i2c {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&tlmm 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "green:status-3";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pm8550_gpios 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "blue:bt-power";
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "yellow:wlan";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_sbu>;
+ };
+ };
+ };
+ };
+ };
+
+ lt9611_1v2: regulator-lt9611-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ vin-supply = <&vreg_l14b_3p2>;
+ };
+
+ lt9611_3v3: regulator-lt9611-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_l14b_3p2>;
+ };
+
+ pcie_upd_1p05: regulator-pcie-upd-1p05 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_UPD_1P05";
+ gpio = <&tlmm 179 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_ntn_0p9>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <5000>;
+ pinctrl-0 = <&upd_1p05_en>;
+ pinctrl-names = "default";
+ };
+
+ pcie_upd_3p3: regulator-pcie-upd-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_UPD_3P3";
+ gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pcie_upd_1p05>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ pinctrl-0 = <&upd_3p3_en>;
+ pinctrl-names = "default";
+ };
+
+ vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_0P9";
+ vin-supply = <&vdd_ntn_1p8>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_1P8";
+ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn0_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN1_0P9";
+ vin-supply = <&vdd_ntn1_1p8>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN1_1P8";
+ gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn1_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ model = "QCS8550-RB5Gen2";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb";
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>,
+ <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>,
+ <&pmk8550_sleep_clk>;
+ pinctrl-names = "default";
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s5g_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p852>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1760000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <835000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p752: ldo2 {
+ regulator-name = "vreg_l2d_0p752";
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <808000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4d_0p628: smps4 {
+ regulator-name = "vreg_s4d_0p628";
+ regulator-min-microvolt = <572000>;
+ regulator-max-microvolt = <988000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5d_0p728: smps5 {
+ regulator-name = "vreg_s5d_0p728";
+ regulator-min-microvolt = <572000>;
+ regulator-max-microvolt = <988000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <831000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1e_0p72: smps1 {
+ regulator-name = "vreg_s1e_0p72";
+ regulator-min-microvolt = <532000>;
+ regulator-max-microvolt = <852000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3e_0p75: smps3 {
+ regulator-name = "vreg_s3e_0p75";
+ regulator-min-microvolt = <716000>;
+ regulator-max-microvolt = <884000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <870100>;
+ regulator-max-microvolt = <1152000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6e_0p728: smps6 {
+ regulator-name = "vreg_s6e_0p728";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <866000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <866000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1f_0p728: smps1 {
+ regulator-name = "vreg_s1f_0p728";
+ regulator-min-microvolt = <516000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3f_0p852: smps3 {
+ regulator-name = "vreg_s3f_0p852";
+ regulator-min-microvolt = <688000>;
+ regulator-max-microvolt = <952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5f_0p752: smps5 {
+ regulator-name = "vreg_s5f_0p752";
+ regulator-min-microvolt = <716000>;
+ regulator-max-microvolt = <884000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_0p628: smps7 {
+ regulator-name = "vreg_s7f_0p628";
+ regulator-min-microvolt = <516000>;
+ regulator-max-microvolt = <812000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1g_1p256: smps1 {
+ regulator-name = "vreg_s1g_1p256";
+ regulator-min-microvolt = <1172000>;
+ regulator-max-microvolt = <1388000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p852: smps2 {
+ regulator-name = "vreg_s2g_0p852";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1053200>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p752: smps3 {
+ regulator-name = "vreg_s3g_0p752";
+ regulator-min-microvolt = <532000>;
+ regulator-max-microvolt = <1148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1172000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1002600>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2192000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_s6g_1p86>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+};
+
+&i2c_hub_2 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ typec-mux@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_usb_con_ss: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_phy_con_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ redriver_usb_con_sbu: endpoint {
+ remote-endpoint = <&pmic_glink_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_3_gpio {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>;
+ pinctrl-names = "default";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_4 {
+ status = "okay";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&ipa {
+ firmware-name = "qcom/sm8550/ipa_fws.mbn";
+
+ status = "okay";
+};
+
+&iris {
+ status = "okay";
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>;
+ pinctrl-names = "default";
+
+ qcom,dmic-sample-rate = <4800000>;
+
+ vdd-micb-supply = <&vreg_l15b_1p8>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ vddpe-3v3-supply = <&pcie_upd_3p3>;
+
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>,
+ <0x208 &apps_smmu 0x1402 0x1>,
+ <0x210 &apps_smmu 0x1403 0x1>,
+ <0x218 &apps_smmu 0x1404 0x1>,
+ <0x300 &apps_smmu 0x1407 0x1>,
+ <0x400 &apps_smmu 0x1408 0x1>,
+ <0x500 &apps_smmu 0x140c 0x1>,
+ <0x501 &apps_smmu 0x140e 0x1>;
+
+ /delete-property/ msi-map;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie0_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c_hub_4 0x77>;
+
+ resx-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_0_rst>, <&upd_ponrst>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
+ <0x100 &apps_smmu 0x1481 0x1>,
+ <0x208 &apps_smmu 0x1482 0x1>,
+ <0x210 &apps_smmu 0x1483 0x1>,
+ <0x218 &apps_smmu 0x1484 0x1>,
+ <0x300 &apps_smmu 0x1487 0x1>,
+ <0x400 &apps_smmu 0x1488 0x1>,
+ <0x500 &apps_smmu 0x148c 0x1>,
+ <0x501 &apps_smmu 0x148e 0x1>;
+
+ /delete-property/ msi-map;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pcie1_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn1_0p9>;
+ vdd18-supply = <&vdd_ntn1_1p8>;
+ vdd09-supply = <&vdd_ntn1_0p9>;
+ vddio1-supply = <&vdd_ntn1_1p8>;
+ vddio2-supply = <&vdd_ntn1_1p8>;
+ vddio18-supply = <&vdd_ntn1_1p8>;
+
+ i2c-parent = <&i2c_hub_3_gpio 0x77>;
+
+ resx-gpios = <&tlmm 65 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_1_rst>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x40000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+ };
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <0>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/adsp.mbn",
+ "qcom/sm8550/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/cdsp.mbn",
+ "qcom/sm8550/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8550/modem.mbn",
+ "qcom/sm8550/modem_dtb.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ no-sdio;
+ no-mmc;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&spi11 {
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk40m>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&vreg_l14b_3p2>;
+ xceiver-supply = <&vreg_l14b_3p2>;
+ };
+};
+
+&swr0 {
+ status = "okay";
+
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&tlmm {
+ /* 32-35 for NFC secure element */
+ /* 36-39 for fingerprint sensor */
+ gpio-reserved-ranges = <32 8>;
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ upd_3p3_en: upd-3p3-en-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio40";
+ function = "gpio";
+ bias-disable;
+ };
+
+ ntn1_en: ntn1-en-state {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tc9563_0_rst: tc9563-0-rst-state {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tc9563_1_rst: tc9563-1-rst-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ntn0_en: ntn0-en-state {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ bt_default: bt-default-state {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ upd_1p05_en: upd-1p05-en-state {
+ pins = "gpio179";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ upd_ponrst: upd-ponrst-state {
+ pins = "gpio182";
+ function = "gpio";
+ drive-strength = <2>;
+ output-high;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_phy_con_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 4/4] arm64: dts: amlogic: t7: Add clk measure support
From: Ronald Claveau @ 2026-04-20 9:16 UTC (permalink / raw)
To: Jian Hu
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
In-Reply-To: <64cde9f6-4f28-4ba7-8362-aac28887ff22@amlogic.com>
Hi Jian,
On 4/20/26 5:25 AM, Jian Hu wrote:
> Hi Ronald,
>
>
> Thanks for your review.
>
> On 4/17/2026 5:48 PM, Ronald Claveau wrote:
>> [ EXTERNAL EMAIL ]
>>
>> Hello Jian,
>>
>> On 4/15/26 10:33 AM, Jian Hu via B4 Relay wrote:
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the clock measure device to the T7 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/
>>> arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> index 7fe72c94ed62..cec2ea74850d 100644
>>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>>> @@ -701,6 +701,11 @@ pwm_ao_cd: pwm@60000 {
>>> status = "disabled";
>>> };
>>>
>>> + clock-measurer@48000 {
>>> + compatible = "amlogic,t7-clk-measure";
>>> + reg = <0x0 0x48000 0x0 0x1c>;
>>> + };
>>> +
>> Can you please order by reg, it should be between pwm_ao_gh and pwm_ab.
>> Thank you.
>
>
> According to the "Order of Nodes" chapter in Documentation/devicetree/
> bindings/dts-coding-style.rst,
>
> nodes of the same type should be grouped together, and this takes higher
> priority.
>
> So I have placed the clock-measure node after all PWM nodes to avoid
> splitting the PWM group.
>
Thanks for your answer.
The documentation says nodes "shall be ordered by unit address" as the
primary rule.
The grouping by type is described as an alternative ("Alternatively"),
applicable to some subarchitectures, not as a rule that takes higher
priority.
So to me, I understand it as, unless your subarchitecture has an
established convention of grouping PWM nodes together, ordering by reg
remains the correct default here. And, in my opinion, sticking to a
single sorting method improves readability.
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH v3 0/5] iio: magnetometer: add driver for QST QMC5883P
From: Andy Shevchenko @ 2026-04-20 9:18 UTC (permalink / raw)
To: Hardik Phalet
Cc: gregkh, jic23, andy, conor+dt, devicetree, dlechner, krzk+dt,
linux-iio, linux-kernel, linux-staging, me, nuno.sa, robh, skhan,
Hardik Phalet
In-Reply-To: <20260420-qmc5883p-driver-v3-0-da1e97088f8b@pm.me>
On Sun, Apr 19, 2026 at 10:32:09PM +0000, Hardik Phalet wrote:
> This series adds an IIO driver for the QST QMC5883P, a 3-axis
> anisotropic magneto-resistive (AMR) magnetometer with a 16-bit ADC,
> communicating over I2C. To my knowledge there is no existing
> upstream driver for this device (see "Prior-art register-map check"
> below).
>
> The driver supports:
> - Raw magnetic field readings on X, Y and Z axes
> - Four full-scale ranges (+/-2 G, +/-8 G, +/-12 G, +/-30 G),
> selectable via IIO_CHAN_INFO_SCALE
> - Four output data rates (10, 50, 100, 200 Hz), selectable via
> IIO_CHAN_INFO_SAMP_FREQ
> - Four oversampling ratios (1, 2, 4, 8), selectable via
> IIO_CHAN_INFO_OVERSAMPLING_RATIO
> - Runtime PM with a 2 s autosuspend delay
> - System suspend/resume delegated to the runtime callbacks
>
> Regmap with an rbtree cache is used throughout. CTRL_1 and CTRL_2
I'm not sure this paragraph answers the question "why not maple tree?"
> bit fields are accessed via regmap_field to avoid read-modify-write
> races. The STATUS register is marked precious so regmap never reads
> it speculatively and clears the DRDY/OVFL bits unexpectedly.
>
> The probe-time init sequence is: soft reset, wait 300 us for POR
> to complete, deassert reset, drop the register cache so subsequent
> RMW writes read fresh values, then enter normal mode. 300 us
> comfortably covers the 250 us POR time given in the datasheet.
>
> Patches:
> 1/5 - dt-bindings: vendor-prefixes: Add QST Corporation
> 2/5 - dt-bindings: iio: magnetometer: QSTCORP QMC5883P
> 3/5 - iio: magnetometer: add driver for QST QMC5883P
> 4/5 - iio: magnetometer: qmc5883p: add oversampling ratio support
> 5/5 - iio: magnetometer: qmc5883p: add PM support
>
> Patches 4 and 5 are split out from the main driver so that the core
> (1-3) can be reviewed and picked independently, per review feedback
> on v2. 4/5 exposes the CTRL_1 OSR field via
> IIO_CHAN_INFO_OVERSAMPLING_RATIO. 5/5 adds runtime PM that puts the
> chip into MODE_SUSPEND when idle and wakes it to MODE_NORMAL on
> demand.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH] dt-bindings: thermal: qcom-tsens: Document Nord Temperature Sensor
From: Pankaj Patil @ 2026-04-20 9:19 UTC (permalink / raw)
To: Shawn Guo, Daniel Lezcano
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Dmitry Baryshkov, Bartosz Golaszewski, Deepti Jaggi, linux-pm,
devicetree, linux-arm-msm, linux-kernel
In-Reply-To: <20260420065409.1249030-1-shengchao.guo@oss.qualcomm.com>
On 4/20/2026 12:24 PM, Shawn Guo wrote:
> From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
>
> Add compatible for Temperature Sensor (TSENS) of Nord SoC with
> a fallback on qcom,tsens-v2.
>
> Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> index 7d34ba00e684..e65ebc6f1698 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> @@ -58,6 +58,7 @@ properties:
> - qcom,glymur-tsens
> - qcom,kaanapali-tsens
> - qcom,milos-tsens
> + - qcom,nord-tsens
> - qcom,msm8953-tsens
> - qcom,msm8996-tsens
> - qcom,msm8998-tsens
^ permalink raw reply
* Re: [PATCH 2/2] regulator: rpmh-regulator: Add RPMH regulator support for Nord
From: Konrad Dybcio @ 2026-04-20 9:21 UTC (permalink / raw)
To: Shawn Guo, Mark Brown
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Dmitry Baryshkov, Kamal Wadhwa, Bartosz Golaszewski, Deepti Jaggi,
devicetree, linux-arm-msm, linux-kernel
In-Reply-To: <20260420072639.1249984-3-shengchao.guo@oss.qualcomm.com>
On 4/20/26 9:26 AM, Shawn Guo wrote:
> From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>
> Add support for PMAU0102 PMIC voltage regulators which are present on
> Nord boards.
>
> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
> drivers/regulator/qcom-rpmh-regulator.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c
> index 6e4cb2871fca..9545300d7b03 100644
> --- a/drivers/regulator/qcom-rpmh-regulator.c
> +++ b/drivers/regulator/qcom-rpmh-regulator.c
> @@ -1100,6 +1100,21 @@ static const struct rpmh_vreg_init_data pm8998_vreg_data[] = {
> {}
> };
>
> +static const struct rpmh_vreg_init_data pmau0102_vreg_data[] = {
> + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps527, "vdd-s1"),
> + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps527, "vdd-s2"),
> + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps527, "vdd-s3"),
> + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps527, "vdd-s4"),
> + RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps527, "vdd-s5"),
> + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps527, "vdd-s6"),
> + RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps527, "vdd-s7"),
> + RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps527, "vdd-s8"),
> + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo515, NULL),
> + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo515, NULL),
> + RPMH_VREG("ldo3", LDO, 3, &pmic5_pldo515_mv, NULL),
Any reason for the NULL supplies?
Konrad
^ permalink raw reply
* Re: [PATCH 2/3] gpio: axiado: add SGPIO controller support
From: Bartosz Golaszewski @ 2026-04-20 9:25 UTC (permalink / raw)
To: Petar Stepanovic
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel,
Tzu-Hao Wei, Swark Yang, Prasad Bolisetty, Linus Walleij,
Bartosz Golaszewski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Harshit Shah, SriNavmani A
In-Reply-To: <20260414-axiado-ax3000-sgpio-controller-v1-2-b5c7e4c2e69b@axiado.com>
On Tue, 14 Apr 2026 15:48:33 +0200, Petar Stepanovic
<pstepanovic@axiado.com> said:
> Add support for the Axiado SGPIO controller.
>
> The controller provides a serialized interface for GPIOs with
> configurable direction and interrupt support.
>
> The driver registers the controller as a gpio_chip and uses
> regmap for register access.
>
> Signed-off-by: Petar Stepanovic <pstepanovic@axiado.com>
> ---
> drivers/gpio/Kconfig | 18 +
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-axiado-sgpio.c | 780 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 799 insertions(+)
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index bd185482a7fd..42c56d157092 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -198,6 +198,24 @@ config GPIO_ATH79
> Select this option to enable GPIO driver for
> Atheros AR71XX/AR724X/AR913X SoC devices.
>
> +config GPIO_AXIADO_SGPIO
> + bool "Axiado SGPIO support"
> + depends on OF_GPIO
You don't need this.
> + depends on ARCH_AXIADO || COMPILE_TEST
> + select GPIO_GENERIC
You don't seem to be using this.
> + select GPIOLIB_IRQCHIP
> + select REGMAP
> + help
> + Enable support for the Axiado Serial GPIO (SGPIO) controller.
> +
> + The SGPIO controller provides a serialized interface for
> + controlling multiple GPIO signals over a limited number of
> + physical lines. It supports configurable data direction and
> + interrupt handling.
> +
> + This driver integrates with the Linux GPIO subsystem and
> + exposes the controller as a standard GPIO provider.
> +
> config GPIO_RASPBERRYPI_EXP
> tristate "Raspberry Pi 3 GPIO Expander"
> default RASPBERRYPI_FIRMWARE
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 2421a8fd3733..909a97551807 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
> obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o
> obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o
> obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o
> +obj-$(CONFIG_GPIO_AXIADO_SGPIO) += gpio-axiado-sgpio.o
> obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
> obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o
> obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o
> diff --git a/drivers/gpio/gpio-axiado-sgpio.c b/drivers/gpio/gpio-axiado-sgpio.c
> new file mode 100644
> index 000000000000..8cd349ec6f53
> --- /dev/null
> +++ b/drivers/gpio/gpio-axiado-sgpio.c
> @@ -0,0 +1,780 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (c) 2022-2026 Axiado Corporation
> + */
Please add a blank line here...
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +
> +#include <linux/gpio/driver.h>
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +
> +#include <linux/regmap.h>
> +
... and keep the includes together as well as ordered alphabetically.
> +struct sgpio_reg_offsets {
> + u32 mux_0;
> + u32 preset_0;
> + u32 count_0;
> + u32 pos_0;
> +
> + u32 mux_1;
> + u32 ld;
> + u32 ld_ss;
> +
> + u32 preset_1;
> + u32 count_1;
> + u32 pos_1;
> +
> + u32 mux_2;
> + u32 dout;
> + u32 dout_ss;
> +
> + u32 preset_2;
> + u32 count_2;
> + u32 pos_2;
> +
> + u32 mux_3;
> + u32 preset_3;
> + u32 count_3;
> + u32 pos_3;
> +
> + u32 mux_4;
> + u32 oe;
> + u32 oe_ss;
> +
> + u32 preset_4;
> + u32 count_4;
> + u32 pos_4;
> +
> + u32 mask;
> + u32 ctrl_en;
> + u32 ctrl_en_pos;
> +
> + u32 din_ss;
> + u32 status;
> +};
> +
> +static const struct sgpio_reg_offsets sgpio_offsets_512 = {
> + .mux_0 = 0x000,
> + .preset_0 = 0x1dc,
> + .count_0 = 0x1f0,
> + .pos_0 = 0x204,
> +
> + .mux_1 = 0x004,
> + .ld = 0x014,
> + .ld_ss = 0x0d8,
> +
> + .preset_1 = 0x1e0,
> + .count_1 = 0x1f4,
> + .pos_1 = 0x208,
> +
> + .mux_2 = 0x008,
> + .dout = 0x054,
> + .dout_ss = 0x158,
> +
> + .preset_2 = 0x1e4,
> + .count_2 = 0x1f8,
> + .pos_2 = 0x20c,
> +
> + .mux_3 = 0x00c,
> + .preset_3 = 0x1e8,
> + .count_3 = 0x1fc,
> + .pos_3 = 0x210,
> +
> + .mux_4 = 0x010,
> + .oe = 0x0d4,
> + .oe_ss = 0x1d8,
> +
> + .preset_4 = 0x1ec,
> + .count_4 = 0x200,
> + .pos_4 = 0x214,
> +
> + .mask = 0x224,
> + .ctrl_en = 0x218,
> + .ctrl_en_pos = 0x21c,
> +
> + .din_ss = 0x198,
> + .status = 0x228,
> +};
> +
> +static const struct sgpio_reg_offsets sgpio_offsets_128 = {
> + .mux_0 = 0x000,
> + .preset_0 = 0x08c,
> + .count_0 = 0x0a0,
> + .pos_0 = 0x0b4,
> +
> + .mux_1 = 0x004,
> + .ld = 0x014,
> + .ld_ss = 0x048,
> +
> + .preset_1 = 0x090,
> + .count_1 = 0x0a4,
> + .pos_1 = 0x0b8,
> +
> + .mux_2 = 0x008,
> + .dout = 0x024,
> + .dout_ss = 0x068,
> +
> + .preset_2 = 0x094,
> + .count_2 = 0x0a8,
> + .pos_2 = 0x0bc,
> +
> + .mux_3 = 0x00c,
> + .preset_3 = 0x098,
> + .count_3 = 0x0ac,
> + .pos_3 = 0x0c0,
> +
> + .mux_4 = 0x010,
> + .oe = 0x044,
> + .oe_ss = 0x088,
> +
> + .preset_4 = 0x09c,
> + .count_4 = 0x0b0,
> + .pos_4 = 0x0c4,
> +
> + .mask = 0x0d4,
> + .ctrl_en = 0x0c8,
> + .ctrl_en_pos = 0x0cc,
> +
> + .din_ss = 0x078,
> + .status = 0x0d8,
> +};
> +
> +#define MAX_SGPIO_PINS 512
> +#define MAX_OFFSET_REG 16
> +#define MAX_SLICE_COUNT 5
> +
> +struct ax3000_slice_info {
> + u32 out_mux;
> + u32 sgpio_mux;
> + u32 slice_mux;
> + u32 reg[MAX_OFFSET_REG];
> + u32 reg_ss[MAX_OFFSET_REG];
> + u32 preset;
> + u32 count;
> + u32 pos;
> +};
> +
> +struct ax3000_sgpio {
> + u32 preset_value;
> + u32 count_value;
> + u32 pos_reg;
> + struct ax3000_slice_info
> + slices[MAX_SLICE_COUNT]; /* 0=clk,1=load,2=out,3=in,4=oe */
> + spinlock_t lock;
> + int ngpios;
> + int max_sgpio_pins;
> + int max_offset_regs;
> + struct gpio_chip chip;
> + u32 irq_unmasked[MAX_SGPIO_PINS];
> + int parent_irq;
> + struct regmap *regmap;
> + u32 regmap_base_offset;
> + struct sgpio_reg_offsets *regs;
> +};
> +
> +static int sgpio_set_irq_type(struct irq_data *d, unsigned int type);
> +static void sgpio_mask_irq(struct irq_data *d);
> +static void sgpio_unmask_irq(struct irq_data *d);
> +static void sgpio_irq_shutdown(struct irq_data *d);
> +
> +static const struct irq_chip axiado_sgpio_irqchip = {
> + .name = "axiado-sgpio",
> + .irq_mask = sgpio_mask_irq,
> + .irq_unmask = sgpio_unmask_irq,
> + .irq_set_type = sgpio_set_irq_type,
> + .irq_shutdown = sgpio_irq_shutdown,
> + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
> +};
> +
> +static void ax3000_sgpio_set(struct gpio_chip *chip, unsigned int offset,
> + int value)
> +{
> + struct ax3000_sgpio *sgpio = gpiochip_get_data(chip);
> + unsigned long flags;
> + u32 bank = (offset / 2) / 32;
> + u32 position = (offset / 2) % 32;
> +
> + spin_lock_irqsave(&sgpio->lock, flags);
Please use guards for locks.
> + if (value)
> + sgpio->slices[2].reg_ss[bank] |= BIT(position);
> + else
> + sgpio->slices[2].reg_ss[bank] &= ~BIT(position);
> +
> + spin_unlock_irqrestore(&sgpio->lock, flags);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout_ss +
> + (bank * 4),
> + sgpio->slices[2].reg_ss[bank]);
> +}
> +
> +static int ax3000_sgpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct ax3000_sgpio *sgpio = gpiochip_get_data(chip);
> + u32 bank = (offset / 2) / 32;
> + u32 position = (offset / 2) % 32;
> +
> + if (offset % 2 == 0)
> + return !!(sgpio->slices[3].reg_ss[bank] & BIT(position));
> + else
> + return !!(sgpio->slices[2].reg_ss[bank] & BIT(position));
> +}
> +
> +static int ax3000_sgpio_dir_in(struct gpio_chip *chip, unsigned int offset)
> +{
> + if (!(offset % 2))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int ax3000_sgpio_dir_out(struct gpio_chip *chip, unsigned int offset,
> + int value)
> +{
> + if (offset % 2) {
> + if (chip->set)
> + chip->set(chip, offset, value);
> + return 0;
> + } else {
> + return -EINVAL;
> + }
> +}
> +
> +static irqreturn_t sgpio_irq_handler(int irq, void *arg)
> +{
> + struct ax3000_sgpio *sgpio = (struct ax3000_sgpio *)arg;
> + unsigned long flags;
> + u32 status, new_value;
> + u32 changed_value;
> + int i, bit, reg_ptr;
> +
> + /* Read-on-clear (ACK) parent cause */
> + regmap_read(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->status, &status);
> + status >>= 16;
> +
> + bool has_shifted_layout = (sgpio->max_offset_regs == MAX_OFFSET_REG);
> +
> + reg_ptr = has_shifted_layout ? 16 - DIV_ROUND_UP(sgpio->ngpios, 32) : 0;
> +
> + for (i = 0; i < DIV_ROUND_UP(sgpio->ngpios, 32); i++, reg_ptr++) {
> + if (status & BIT(reg_ptr)) {
> + regmap_read(sgpio->regmap,
> + sgpio->regmap_base_offset +
> + sgpio->regs->din_ss + (reg_ptr * 4),
> + &new_value);
> + spin_lock_irqsave(&sgpio->lock, flags);
> + changed_value = sgpio->slices[3].reg_ss[i] ^ new_value;
> + sgpio->slices[3].reg_ss[i] = new_value;
> + spin_unlock_irqrestore(&sgpio->lock, flags);
> +
> + while (changed_value) {
> + bit = __ffs(changed_value);
> + changed_value &= ~BIT(bit);
> +
> + irq_hw_number_t hwirq = i * 32 + bit;
> +
> + if (sgpio->irq_unmasked[hwirq]) {
> + unsigned int child_irq;
> +
> + child_irq = irq_find_mapping(sgpio->chip.irq.domain,
> + hwirq);
> +
> + if (child_irq)
> + handle_nested_irq(child_irq);
> + }
> + }
> + }
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void sgpio_hw_init(struct ax3000_sgpio *sgpio)
> +{
> + u32 bank;
> + u32 position;
> + int i = 0;
> + bool has_shifted_layout = (sgpio->max_offset_regs == MAX_OFFSET_REG);
> +
> + /* slice A0, Clock Pin - 0 */
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_0, 0x306);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_0,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_0,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_0, 0x1f001f);
> +
> + /* Slice B1, Data Load Pin - 1 */
> + bank = (sgpio->ngpios - 1) / 32;
> + position = (sgpio->ngpios - 1) % 32;
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_1,
> + has_shifted_layout ? 0x30c : 0x304);
> +
> + for (i = 0; i < bank; i++) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld +
> + (i * 4),
> + 0xffffffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld_ss +
> + (i * 4),
> + 0xffffffff);
> + }
> +
> + if (position) {
> + u32 val;
> +
> + val = sgpio->slices[1].reg_ss[i];
> + val |= GENMASK(position - 1, 0);
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld +
> + (i * 4),
> + val);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ld_ss +
> + (i * 4),
> + val);
> + }
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_1,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_1,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_1,
> + sgpio->pos_reg);
> +
> + /* Slice C2, Data Out Pin - 2 */
> + bank = sgpio->ngpios / 32;
> + position = sgpio->ngpios % 32;
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_2,
> + has_shifted_layout ? 0x30c : 0x304);
> +
> + for (i = 0; i < bank; i++) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout_ss +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + }
> +
> + if (position) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->dout_ss +
> + (i * 4),
> + sgpio->slices[2].reg_ss[i]);
> + }
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_2,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_2,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_2,
> + sgpio->pos_reg);
> +
> + /* Slice D3, Data In Pin - 3 */
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_3, 0x14C);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_3,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_3,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_3,
> + sgpio->pos_reg);
> +
> + /* Slice E4, Output Enable for respective pins */
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mux_4,
> + has_shifted_layout ? 0x10c : 0x104);
> + regmap_write(sgpio->regmap, sgpio->regmap_base_offset + sgpio->regs->oe,
> + 0xffffffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->oe_ss,
> + 0xffffffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->preset_4,
> + sgpio->preset_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->count_4,
> + sgpio->count_value);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->pos_4, 0x1f001f);
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mask, 0xdfff);
> +
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ctrl_en, 0xffff);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ctrl_en_pos,
> + 0xffff);
> +}
> +
> +static int sgpio_set_irq_type(struct irq_data *d, unsigned int type)
> +{
> + switch (type) {
> + case IRQ_TYPE_EDGE_BOTH:
> + case IRQ_TYPE_EDGE_RISING:
> + case IRQ_TYPE_EDGE_FALLING:
> + irq_set_handler_locked(d, handle_edge_irq);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void sgpio_mask_irq(struct irq_data *d)
> +{
> + struct gpio_chip *chip;
> + struct ax3000_sgpio *sgpio;
> + u32 irq_num;
> +
> + chip = irq_data_get_irq_chip_data(d);
> + if (!chip) {
> + pr_err("Unable to get gpio_chip for IRQ\n");
> + return;
> + }
> +
> + sgpio = gpiochip_get_data(chip);
> + if (!sgpio) {
> + pr_err("Unable to get chip data\n");
> + return;
> + }
> +
> + irq_num = irqd_to_hwirq(d);
> + sgpio->irq_unmasked[irq_num / 2] = 0;
> +}
> +
> +static void sgpio_unmask_irq(struct irq_data *d)
> +{
> + struct gpio_chip *chip;
> + struct ax3000_sgpio *sgpio;
> + u32 irq_num;
> +
> + chip = irq_data_get_irq_chip_data(d);
> + if (!chip) {
> + pr_err("Unable to get gpio_chip for IRQ\n");
> + return;
> + }
> +
> + sgpio = gpiochip_get_data(chip);
> + if (!sgpio) {
> + pr_err("Unable to get chip data\n");
> + return;
> + }
> +
> + irq_num = irqd_to_hwirq(d);
> + sgpio->irq_unmasked[irq_num / 2] = 1;
> +}
> +
> +static void sgpio_irq_shutdown(struct irq_data *d)
> +{
> + sgpio_mask_irq(d);
> +}
> +
> +static int sgpio_probe(struct platform_device *pdev)
> +{
> + int rc;
> + int irq;
> + int i;
> + const __be32 *prop;
> + struct gpio_irq_chip *girq;
> + struct ax3000_sgpio *sgpio;
> + u32 variant;
> + u32 dout_value;
> + u32 bus_frequency;
> + u32 apb_frequency;
> + int dout_reverse;
> +
> + void __iomem *base;
> +
> + const struct regmap_config regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + };
> +
> + sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
> + if (!sgpio)
> + return -ENOMEM;
> +
> + spin_lock_init(&sgpio->lock);
> +
> + sgpio->regmap = dev_get_regmap(pdev->dev.parent, NULL);
> +
> + if (sgpio->regmap) {
> + rc = of_property_read_u32(pdev->dev.of_node, "reg",
> + &sgpio->regmap_base_offset);
Why are you mixing of_property_*() with device_property_*()?
> + if (rc) {
> + dev_err(&pdev->dev, "Failed to read reg property: %d\n",
> + rc);
> + return rc;
> + }
> + dev_info(&pdev->dev, "Using regmap with base offset: 0x%x\n",
> + sgpio->regmap_base_offset);
> + } else {
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + sgpio->regmap =
> + devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
> +
> + if (IS_ERR(sgpio->regmap))
> + return PTR_ERR(sgpio->regmap);
> +
> + sgpio->regmap_base_offset = 0;
> +
> + dev_info(&pdev->dev, "Using MMIO regmap\n");
> + }
> +
> + rc = device_property_read_u32(&pdev->dev, "ngpios", &sgpio->ngpios);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not read ngpios property\n");
> + return -EINVAL;
> + }
> +
> + if (device_property_read_u32(&pdev->dev, "design-variant", &variant)) {
> + dev_err(&pdev->dev, "design-variant not specified in DT\n");
> + return -EINVAL;
> + }
> +
> + if (variant == 128) {
> + sgpio->regs = &sgpio_offsets_128;
> + sgpio->max_sgpio_pins = 128;
> + sgpio->max_offset_regs = 4;
> + } else if (variant == 512) {
> + sgpio->regs = &sgpio_offsets_512;
> + sgpio->max_sgpio_pins = 512;
> + sgpio->max_offset_regs = 16;
> + } else {
> + return -EINVAL;
> + }
> +
> + if (sgpio->ngpios > sgpio->max_sgpio_pins) {
> + dev_err(&pdev->dev, "ngpio is greater than 512 pins\n");
> + return -EINVAL;
> + }
> +
> + rc = device_property_read_u32(&pdev->dev, "bus-frequency",
> + &bus_frequency);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not read bus-frequency property\n");
> + return -EINVAL;
> + }
> +
> + rc = device_property_read_u32(&pdev->dev, "apb-frequency",
> + &apb_frequency);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not read apb-frequency property\n");
> + return -EINVAL;
> + }
> +
> + sgpio->preset_value = (apb_frequency / bus_frequency) - 1;
> + sgpio->count_value = sgpio->preset_value;
> +
> + u32 pos;
> +
> + pos = sgpio->ngpios - 1;
> + sgpio->pos_reg = (pos << 16) | pos;
> +
> + prop = of_get_property(pdev->dev.of_node, "dout-init", NULL);
> + if (!prop) {
> + dev_err(&pdev->dev, "Failed to get dout-init\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < sgpio->max_offset_regs; i++) {
> + sgpio->slices[2].reg_ss[i] = 0;
> + dout_value = be32_to_cpu(prop[i]);
> +
> + for (dout_reverse = 0; dout_reverse < 32; ++dout_reverse) {
> + sgpio->slices[2].reg_ss[i] <<= 1;
> + sgpio->slices[2].reg_ss[i] |= (dout_value & 1);
> + dout_value >>= 1;
> + }
> + }
> +
> + sgpio_hw_init(sgpio);
> +
> + irq = platform_get_irq(pdev, 0);
> +
Unnecessary newline.
> + if (irq < 0) {
> + dev_err(&pdev->dev, "Failed to get parent IRQ: %d\n", irq);
> + return irq;
> + }
> + /* Store parent IRQ for cleanup */
> + sgpio->parent_irq = irq;
> +
> + rc = devm_request_threaded_irq(&pdev->dev, irq, NULL, sgpio_irq_handler,
> + IRQF_ONESHOT, "axiado-sgpio", sgpio);
> +
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Failed to request threaded IRQ %d: %d\n",
> + irq, rc);
> + return rc;
> + }
> +
> + sgpio->chip.parent = &pdev->dev;
> + sgpio->chip.ngpio = sgpio->ngpios * 2;
> + sgpio->chip.owner = THIS_MODULE;
> + sgpio->chip.direction_input = ax3000_sgpio_dir_in;
> + sgpio->chip.direction_output = ax3000_sgpio_dir_out;
> + sgpio->chip.get = ax3000_sgpio_get;
> + sgpio->chip.set = ax3000_sgpio_set;
> + sgpio->chip.label = dev_name(&pdev->dev);
> + sgpio->chip.base = -1;
> +
> + girq = &sgpio->chip.irq;
> +
> + girq->chip = &axiado_sgpio_irqchip;
> + girq->handler = handle_edge_irq;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->num_parents = 1;
> + girq->parents =
> + devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
> + if (!girq->parents) {
> + dev_err(&pdev->dev, "Failed to allocate parents array\n");
Drop this message, returning -ENOMEM is enough.
> + return -ENOMEM;
> + }
> + girq->parents[0] = irq;
> +
> + rc = devm_gpiochip_add_data(&pdev->dev, &sgpio->chip, sgpio);
> + if (rc < 0) {
> + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", rc);
> + return rc;
Use return dev_err_probe() here and elsewhere.
> + }
> +
> + /* Store driver data for remove() */
> + platform_set_drvdata(pdev, sgpio);
> + dev_info(&pdev->dev, "SGPIO registered with %d GPIOs\n",
> + sgpio->chip.ngpio);
No need for this info message, please drop it.
> +
> + return 0;
> +}
> +
> +static int sgpio_remove(struct platform_device *pdev)
> +{
> + struct ax3000_sgpio *sgpio = platform_get_drvdata(pdev);
> + int i;
> +
> + if (!sgpio)
> + return 0;
> +
> + /* Disable interrupts in hardware */
> + if (sgpio->regs) {
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->mask,
> + 0x0);
> + regmap_write(sgpio->regmap,
> + sgpio->regmap_base_offset + sgpio->regs->ctrl_en,
> + 0x0);
> + }
> +
> + /* Disable and synchronize parent IRQ to avoid races with handlers */
> + if (sgpio->parent_irq >= 0) {
> + disable_irq(sgpio->parent_irq);
> + synchronize_irq(sgpio->parent_irq);
> + }
> +
> + /* Ensure all GPIO IRQ handlers complete before removal */
> + if (sgpio->chip.irq.domain) {
> + struct irq_domain *domain = sgpio->chip.irq.domain;
> + unsigned int irq;
> + int hwirq;
> +
> + for (hwirq = 0; hwirq < sgpio->chip.ngpio; hwirq++) {
> + irq = irq_find_mapping(domain, hwirq);
> + if (irq) {
> + disable_irq(irq);
> + synchronize_irq(irq);
> + }
> + }
> + }
> +
> + /* Clear internal IRQ state */
> + for (i = 0; i < sgpio->max_sgpio_pins; i++)
> + sgpio->irq_unmasked[i] = 0;
> +
> + return 0;
> +}
> +
> +static const struct of_device_id ax_sgpio_match[] = {
> + { .compatible = "axiado,sgpio" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, ax_sgpio_match);
> +
> +static struct platform_driver sgpio_driver = {
> + .driver = {
> + .name = "sgpio",
> + .owner = THIS_MODULE,
> + .of_match_table = ax_sgpio_match,
> + },
> + .probe = sgpio_probe,
> + .remove = sgpio_remove,
> +};
> +
> +static int __init ax_sgpio_init(void)
> +{
> + int ret;
> +
> + ret = platform_driver_register(&sgpio_driver);
> + if (ret < 0) {
> + pr_err("Failed to register SGPIO driver\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void __exit ax_sgpio_exit(void)
> +{
> + platform_driver_unregister(&sgpio_driver);
> +}
> +
> +module_init(ax_sgpio_init);
> +module_exit(ax_sgpio_exit);
Just use module_platform_driver().
> +
> +MODULE_DESCRIPTION("Axiado Serial GPIO Driver");
> +MODULE_AUTHOR("Axiado Corporation");
> +MODULE_LICENSE("GPL");
>
> --
> 2.34.1
>
>
Bart
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: amlogic: t7: khadas-vim4: Enable Bluetooth
From: Ronald Claveau @ 2026-04-20 9:26 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <c9c3227f-2a46-47b5-963f-e784184f7f31@linaro.org>
On 4/20/26 10:47 AM, Neil Armstrong wrote:
>> Enable UART C on the Khadas VIM4 board and attach the BCM43438
>> compatible Bluetooth controller to it. The node configures the RTS/CTS
>> hardware flow control, the associated pinmux, the power supplies
>> (vddao_3v3
>> and vddao_1v8), the 32 kHz LPO clock shared with the wifi32k fixed
>> clock, and the GPIO lines used for host wakeup, device wakeup and
>> shutdown.
>>
>> Remove clocks and clock-names for UART A, as they are defined in DTSI.
>
> This should be a separate patch.
Thanks for your feedback.
I will then add the remove redundant clocks before that one.
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH] dts: riscv: spacemit: k3: only keep spacemit,k1-i2c
From: Sandie Cao @ 2026-04-20 9:26 UTC (permalink / raw)
To: Yixun Lan
Cc: Troy Mitchell, Krzysztof Kozlowski, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, spacemit, linux-riscv, devicetree, linux-kernel,
kernel test robot
In-Reply-To: <20260420090936-GKB203300@kernel.org>
Hi, Lan & Troy & Krzysztof :
> From: "Yixun Lan"<dlan@kernel.org>
> Date: Mon, Apr 20, 2026, 17:09
> Hi Troy,
>
> On 16:50 Mon 20 Apr , Troy Mitchell wrote:
> > On Mon Apr 20, 2026 at 4:44 PM CST, Krzysztof Kozlowski wrote:
> > > On 20/04/2026 10:43, Krzysztof Kozlowski wrote:
> > >> On 20/04/2026 10:39, Sandie Cao wrote:
> > >>> Fix dtcheck issue: compatible:0: 'spacemit,k1-i2c' was expected
> > >>
> > >> Missing space after main commit msg.
> > >>
> > >>> Reported-by: kernel test robot <lkp@intel.com>
> > >>> Closes: https://lore.kernel.org/r/202604140259.eKDaxKua-lkp@intel.com/
> > >>>
> > >
> > > Also, the file reported in above warning DOES NOT EXIST (I checked
> > > next-20260414).
> > In Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml:
> >
> > properties:
> > compatible:
> > enum:
> > - spacemit,k1-pinctrl
> > - spacemit,k3-pinctrl
> >
> I think you refer to wrong file, which should be
> Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
>
> > So there's no reason to use k1-i2c. As far as I can tell, while they are the same IP,
> > there are subtle differences between them.
> >
> But yes, the idea is correct, so NAK to this patch
> > - Troy
>
> --
> Yixun Lan (dlan)
>
Please know that, I send patch[1] to add DeepComputing FML13V05 board device tree. The patch is based on k1/dt-for-next[2].
And it meets dtscheck issue:
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/r/202604140259.eKDaxKua-lkp@intel.com/
On k1/dt-for-next, it doesn't have spacemit,k3-i2c in Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml.
Or I use the wrong branch?
And what should I do for my patch[1] ?
[1] https://lore.kernel.org/all/20260413060524.1235982-1-sandie.cao@deepcomputing.io/
[2] https://github.com/spacemit-com/linux/tree/k1/for-next#
Best regards
Sandie
^ permalink raw reply
* Re: [PATCH] dts: riscv: spacemit: k3: only keep spacemit,k1-i2c
From: Troy Mitchell @ 2026-04-20 9:27 UTC (permalink / raw)
To: Yixun Lan, Troy Mitchell
Cc: Krzysztof Kozlowski, Sandie Cao, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, spacemit, linux-riscv, devicetree, linux-kernel,
kernel test robot
In-Reply-To: <20260420090936-GKB203300@kernel.org>
On Mon Apr 20, 2026 at 5:09 PM CST, Yixun Lan wrote:
> Hi Troy,
>
> On 16:50 Mon 20 Apr , Troy Mitchell wrote:
>> On Mon Apr 20, 2026 at 4:44 PM CST, Krzysztof Kozlowski wrote:
>> > On 20/04/2026 10:43, Krzysztof Kozlowski wrote:
>> >> On 20/04/2026 10:39, Sandie Cao wrote:
>> >>> Fix dtcheck issue: compatible:0: 'spacemit,k1-i2c' was expected
>> >>
>> >> Missing space after main commit msg.
>> >>
>> >>> Reported-by: kernel test robot <lkp@intel.com>
>> >>> Closes: https://lore.kernel.org/r/202604140259.eKDaxKua-lkp@intel.com/
>> >>>
>> >
>> > Also, the file reported in above warning DOES NOT EXIST (I checked
>> > next-20260414).
>> In Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml:
>>
>> properties:
>> compatible:
>> enum:
>> - spacemit,k1-pinctrl
>> - spacemit,k3-pinctrl
>>
> I think you refer to wrong file, which should be
> Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
My apologies, I overlooked that. The file you mentioned is indeed correct.
Thanks for pointing it out.
- Troy
^ permalink raw reply
* Re: [PATCH V13 02/12] PCI: host-generic: Add common helpers for parsing Root Port properties
From: mani @ 2026-04-20 9:35 UTC (permalink / raw)
To: Sherry Sun
Cc: Bjorn Helgaas, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Frank Li, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, bhelgaas@google.com, Hongxing Zhu,
l.stach@pengutronix.de, imx@lists.linux.dev,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <VI0PR04MB12114304913B6AACF6A206E10922F2@VI0PR04MB12114.eurprd04.prod.outlook.com>
On Mon, Apr 20, 2026 at 08:24:57AM +0000, Sherry Sun wrote:
[...]
> > Even if there are PERST# GPIOs from the host, connected to downstream
> > ports of a PCIe switch, they could be stored in the Root Port's (pci_host_port)
> > struct as a list of PERST#. This is what pcie-qcom driver does.
> >
> > It is too clumsy to handle PERST# individually for each device. We tried it
> > before with pwrctrl, but it always ended up biting us on who gets to control
> > the PERST#. We can't let pwrctrl handle PERST# for a switch port and host
> > controller driver handle it for RP. And we cannot let pwrctrl handle PERST# for
> > all ports, because, host controller drivers also need to control them for RC
> > initialization.
> >
> > That's why it was decided to handle PERST# for all ports in the host controller
> > drivers. So following that pattern, this helper could also be extended to parse
> > the PERST# from all ports defined in DT and store them in the same Root Port
> > struct.
> >
> > It should be trivial to implement this logic in the current helper. @Sherry:
> > Could you please implement this logic?
>
> Hi Mani, do you mean the similar logic in this patch?
> https://lore.kernel.org/all/20251216-pci-pwrctrl-rework-v2-1-745a563b9be6@oss.qualcomm.com/
> If yes, of cause I can do this for current helper functions in pci-host-common.c.
>
Yes!
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH] dts: riscv: spacemit: k3: only keep spacemit,k1-i2c
From: Troy Mitchell @ 2026-04-20 9:35 UTC (permalink / raw)
To: Sandie Cao, Yixun Lan
Cc: Troy Mitchell, Krzysztof Kozlowski, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, spacemit, linux-riscv, devicetree, linux-kernel,
kernel test robot
In-Reply-To: <407ce3d77416bb2522b7906b0df3d5adf02c27ee.5595e961.9ee2.4959.8935.9a8f33812b0c@feishu.cn>
On Mon Apr 20, 2026 at 5:26 PM CST, Sandie Cao wrote:
> Hi, Lan & Troy & Krzysztof :
>
>> From: "Yixun Lan"<dlan@kernel.org>
>> Date: Mon, Apr 20, 2026, 17:09
>
>> Hi Troy,
>>
>> On 16:50 Mon 20 Apr , Troy Mitchell wrote:
>> > On Mon Apr 20, 2026 at 4:44 PM CST, Krzysztof Kozlowski wrote:
>> > > On 20/04/2026 10:43, Krzysztof Kozlowski wrote:
>> > >> On 20/04/2026 10:39, Sandie Cao wrote:
>> > >>> Fix dtcheck issue: compatible:0: 'spacemit,k1-i2c' was expected
>> > >>
>> > >> Missing space after main commit msg.
>> > >>
>> > >>> Reported-by: kernel test robot <lkp@intel.com>
>> > >>> Closes: https://lore.kernel.org/r/202604140259.eKDaxKua-lkp@intel.com/
>> > >>>
>> > >
>> > > Also, the file reported in above warning DOES NOT EXIST (I checked
>> > > next-20260414).
>> > In Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml:
>> >
>> > properties:
>> > compatible:
>> > enum:
>> > - spacemit,k1-pinctrl
>> > - spacemit,k3-pinctrl
>> >
>> I think you refer to wrong file, which should be
>> Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
>>
>> > So there's no reason to use k1-i2c. As far as I can tell, while they are the same IP,
>> > there are subtle differences between them.
>> >
>> But yes, the idea is correct, so NAK to this patch
>> > - Troy
>>
>> --
>> Yixun Lan (dlan)
>>
>
> Please know that, I send patch[1] to add DeepComputing FML13V05 board device tree. The patch is based on k1/dt-for-next[2].
> And it meets dtscheck issue:
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/r/202604140259.eKDaxKua-lkp@intel.com/
>
> On k1/dt-for-next, it doesn't have spacemit,k3-i2c in Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml.
> Or I use the wrong branch?
Yes... You are using a wrong branch I think.
The k1/dt-for-next branch in this repo is Dlan’s tree. Since DT bindings are not within
his purview, they aren't included there. I only mentioned this repository earlier to
show that the UART portion of the pinctrl dtsi has already been merged into it;
it wasn't intended to be used as your development base.
>
> And what should I do for my patch[1] ?
I think you can use next-20260417 as your base commit.
Everything you need is available here.
- Troy
>
> [1] https://lore.kernel.org/all/20260413060524.1235982-1-sandie.cao@deepcomputing.io/
> [2] https://github.com/spacemit-com/linux/tree/k1/for-next#
>
> Best regards
> Sandie
^ permalink raw reply
* [PATCH v2 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator
From: dongxuyang @ 2026-04-20 9:39 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, linux-clk, devicetree,
linux-kernel, p.zabel, huangyifeng, dongxuyang, benoit.monin,
bmasney
Cc: ningyu, linmin, pinkesh.vaghela
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add support for the ESWIN EIC7700 HSP (high-speed peripherals). The drivers
provide basic functionality to manage and control the clock and reset
signals for EIC7700 HSP, including mmc, USB, ethernet, SATA and DMAC.
The clock and reset registers are mapped to overlapping I/O address ranges.
This causes a resource conflict when two drivers attempt to request the
same region. Use the auxiliary device framework: the main driver
allocates the shared register region and passes it to auxiliary
devices, avoiding resource contention and duplicate remapping.
Features:
Implements support for the ESWIN EIC7700 HSP clock and reset controller.
Provide API to manage clock and reset signals for the EIC7700 HSP.
Supported chips:
ESWIN EIC7700 series SoC.
Test:
Test this patch on the Sifive HiFive Premier P550 (which used the EIC7700
SoC), include USB and other peripherals. All the drivers of these modules
use the clock module and reset module.
This patch depends on ESWIN EIC7700 clock controller patch [1], [2] and [3].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260331&id=8add6d87dc69c0620c7e60bdc6be6b3b0092d9fa
[2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260331&id=cd44f127c1d42833a32ba0a0965255ee6184f8c1
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260331&id=858f6273cf003e97c817903a07d8001b483fe40b
Updates:
Changes in v2:
- bindings:
- Remove "hsp_" from clock-names.
- Replace "eswin,eic7700-clock.yaml" and "eswin,eic7700-hspcrg.yaml" with
"eswin,eic7700*".
- Replace "eswin,eic7700-clock.h" and "eswin,eic7700-hspcrg.h" with
"eswin,eic7700*".
- clock driver:
- Use guard(spinlock_irqsave)(gate->lock) instead of spin_lock_irqsave()
and remove spin_unlock_irqrestore().
- Remove the newline in function hsp_clk_gate_is_enabled().
- Use struct clk_init_data init = {}.
- Replace 'static struct clk_parent_data' with
'static const struct clk_parent_data'.
- Change '.fw_name' to '.index', because the function
eswin_clk_register_fixed_factor() uses .index.
- Improve the formatting.
- Create the regmap in the clock driver and remove (__force void*)data->base.
The reset driver uses dev_get_regmap() to get the regmap from the clock.
- Move 'const struct regmap_config eic7700_hsp_regmap_config' from reset
driver to clock driver.
- The USB clock gate (hsp_clk_gate_endisable) and the reset driver both
perform read-modify-write cycles on registers 0x800 and 0x900. Use
custom regmap lock callbacks so that regmap operations hold data->lock
with IRQs disabled, the same lock the clock gate path uses, preventing
concurrent RMW races on those shared registers.
- reset driver:
- Remove 'depends on COMMON_CLK_EIC7700_HSP' and 'default COMMON_CLK_EIC7700_HSP'.
- Use regmap_assign_bits() in assert and deassert functions.
- Remove eic7700_hsp_reset_reset().
- The clock driver creates the regmap, and the reset driver uses dev_get_regmap().
- Remove the setting of_reset_n_cells.
- Link to v1: https://lore.kernel.org/all/20260403093459.612-1-dongxuyang@eswincomputing.com/
Xuyang Dong (3):
dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator
clk: eswin: Add eic7700 HSP clock driver
reset: eswin: Add eic7700 HSP reset driver
.../bindings/clock/eswin,eic7700-hspcrg.yaml | 63 +++
MAINTAINERS | 5 +-
drivers/clk/eswin/Kconfig | 12 +
drivers/clk/eswin/Makefile | 1 +
drivers/clk/eswin/clk-eic7700-hsp.c | 385 ++++++++++++++++++
drivers/reset/Kconfig | 11 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-eic7700-hsp.c | 118 ++++++
.../dt-bindings/clock/eswin,eic7700-hspcrg.h | 33 ++
.../dt-bindings/reset/eswin,eic7700-hspcrg.h | 21 +
10 files changed, 648 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
create mode 100644 drivers/clk/eswin/clk-eic7700-hsp.c
create mode 100644 drivers/reset/reset-eic7700-hsp.c
create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h
--
2.43.0
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator
From: dongxuyang @ 2026-04-20 9:40 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, linux-clk, devicetree,
linux-kernel, p.zabel, huangyifeng, dongxuyang, benoit.monin,
bmasney
Cc: ningyu, linmin, pinkesh.vaghela
In-Reply-To: <20260420093929.1895-1-dongxuyang@eswincomputing.com>
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add bindings for the high-speed peripherals clock and reset generator
on the ESWIN EIC7700 HSP.
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
.../bindings/clock/eswin,eic7700-hspcrg.yaml | 63 +++++++++++++++++++
MAINTAINERS | 5 +-
.../dt-bindings/clock/eswin,eic7700-hspcrg.h | 33 ++++++++++
.../dt-bindings/reset/eswin,eic7700-hspcrg.h | 21 +++++++
4 files changed, 120 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h
diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
new file mode 100644
index 000000000000..43df689ae647
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 HSP Clock and Reset Generator
+
+maintainers:
+ - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+ Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
+
+properties:
+ compatible:
+ const: eswin,eic7700-hspcrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: HSP configuration top clock
+ - description: MMC top clock
+ - description: SATA top clock
+
+ clock-names:
+ items:
+ - const: cfg
+ - const: mmc
+ - const: sata
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@50440000 {
+ compatible = "eswin,eic7700-hspcrg";
+ reg = <0x50440000 0x2000>;
+ clocks = <&clock 171>, <&clock 254>, <&clock 187>;
+ clock-names = "cfg", "mmc", "sata";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index fe81fd3baedc..639fd11ebdd7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9573,9 +9573,10 @@ ESWIN EIC7700 CLOCK DRIVER
M: Yifeng Huang <huangyifeng@eswincomputing.com>
M: Xuyang Dong <dongxuyang@eswincomputing.com>
S: Maintained
-F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
+F: Documentation/devicetree/bindings/clock/eswin,eic7700*
F: drivers/clk/eswin/
-F: include/dt-bindings/clock/eswin,eic7700-clock.h
+F: include/dt-bindings/clock/eswin,eic7700*
+F: include/dt-bindings/reset/eswin,eic7700-hspcrg.h
ET131X NETWORK DRIVER
M: Mark Einon <mark.einon@gmail.com>
diff --git a/include/dt-bindings/clock/eswin,eic7700-hspcrg.h b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..1d1ff15c1154
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP clock controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+
+#define EIC7700_HSP_CLK_FAC_CFG_DIV2 0
+#define EIC7700_HSP_CLK_FAC_CFG_DIV4 1
+#define EIC7700_HSP_CLK_FAC_MMC_DIV10 2
+#define EIC7700_HSP_CLK_MUX_EMMC_3MUX1 3
+#define EIC7700_HSP_CLK_MUX_SD0_3MUX1 4
+#define EIC7700_HSP_CLK_MUX_SD1_3MUX1 5
+#define EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1 6
+#define EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1 7
+#define EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1 8
+#define EIC7700_HSP_CLK_GATE_MSHC0_TMR 9
+#define EIC7700_HSP_CLK_GATE_EMMC 10
+#define EIC7700_HSP_CLK_GATE_MSHC1_TMR 11
+#define EIC7700_HSP_CLK_GATE_SD0 12
+#define EIC7700_HSP_CLK_GATE_MSHC2_TMR 13
+#define EIC7700_HSP_CLK_GATE_SD1 14
+#define EIC7700_HSP_CLK_GATE_USB0 15
+#define EIC7700_HSP_CLK_GATE_USB1 16
+#define EIC7700_HSP_CLK_GATE_SATA 17
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ */
diff --git a/include/dt-bindings/reset/eswin,eic7700-hspcrg.h b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..413fcd08c701
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP reset controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+
+#define EIC7700_HSP_RST_SATA_P0 0
+#define EIC7700_HSP_RST_SATA_PHY 1
+#define EIC7700_HSP_RST_USB0 2
+#define EIC7700_HSP_RST_USB1 3
+#define EIC7700_HSP_RST_USB0_PHY 4
+#define EIC7700_HSP_RST_USB1_PHY 5
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_ */
--
2.43.0
^ permalink raw reply related
* [PATCH v2 1/3] arm64: dts: qcom: sdm660: set cdsp compute-cbs' regs properly
From: Nickolay Goppen @ 2026-04-20 9:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming, Nickolay Goppen, Konrad Dybcio,
Ekansh Gupta, Dmitry Baryshkov
In-Reply-To: <20260420-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v2-0-f6c7ab3c889a@mainlining.org>
Changing FastRPC compute-cbs' reg values to matching iommu streams
solves SMMU translation errors when trying to use FastRPC on CDSP
so change FastRPC compute-cbs' reg values that way
Fixes: c0c32a9e3493 ("arm64: dts: qcom: sdm630/660: Add CDSP-related nodes")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index 3fd6dd82a992..0fca9662c64a 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -350,57 +350,57 @@ fastrpc {
#address-cells = <1>;
#size-cells = <0>;
- compute-cb@5 {
+ compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <5>;
+ reg = <3>;
iommus = <&cdsp_smmu 3>;
};
- compute-cb@6 {
+ compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <6>;
+ reg = <4>;
iommus = <&cdsp_smmu 4>;
};
- compute-cb@7 {
+ compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <7>;
+ reg = <5>;
iommus = <&cdsp_smmu 5>;
};
- compute-cb@8 {
+ compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <8>;
+ reg = <6>;
iommus = <&cdsp_smmu 6>;
};
- compute-cb@9 {
+ compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <9>;
+ reg = <7>;
iommus = <&cdsp_smmu 7>;
};
- compute-cb@10 {
+ compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <10>;
+ reg = <8>;
iommus = <&cdsp_smmu 8>;
};
- compute-cb@11 {
+ compute-cb@9 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <11>;
+ reg = <9>;
iommus = <&cdsp_smmu 9>;
};
- compute-cb@12 {
+ compute-cb@10 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <12>;
+ reg = <10>;
iommus = <&cdsp_smmu 10>;
};
- compute-cb@13 {
+ compute-cb@11 {
compatible = "qcom,fastrpc-compute-cb";
- reg = <13>;
+ reg = <11>;
iommus = <&cdsp_smmu 11>;
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH v2 0/3] arm64: dts: qcom: sdm630/660 FastRPC fixes
From: Nickolay Goppen @ 2026-04-20 9:42 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming, Nickolay Goppen, Konrad Dybcio,
Ekansh Gupta, Dmitry Baryshkov
This series introduces fixes that make FastRPC on SDM660 work properly.
Currently only the calculator_example test passes on both ADSP and
CDSP [1].
Also assign adsp_mem region to the ADSP's FastRPC node.
[1]: https://github.com/qualcomm/fastrpc/issues/269#issuecomment-4232125297
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
---
Changes in v2:
- Dropped patch that changed adsp_mem to reusable
- Added vmids to fastrpc subnode of adsp (Ekansh Gupta)
- Link to v1: https://patch.msgid.link/20260415-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-v1-0-03b475b29554@mainlining.org
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Nickolay Goppen <setotau@mainlining.org>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Nickolay Goppen (3):
arm64: dts: qcom: sdm660: set cdsp compute-cbs' regs properly
arm64: dts: qcom: sdm630: set adsp compute-cbs' regs properly
arm64: dts: qcom: sdm630: assign adsp_mem region to ADSP FastRPC node
arch/arm64/boot/dts/qcom/sdm630.dtsi | 19 +++++++++++--------
arch/arm64/boot/dts/qcom/sdm660.dtsi | 36 ++++++++++++++++++------------------
2 files changed, 29 insertions(+), 26 deletions(-)
---
base-commit: e6efabc0afca02efa263aba533f35d90117ab283
change-id: 20260415-qcom-sdm660-cdsp-adsp-fastrpc-dts-fix-d0ca7632045a
Best regards,
--
Nickolay Goppen <setotau@mainlining.org>
^ permalink raw reply
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