* [PATCH v2 16/37] arm64: dts: qcom: sa8540p-ride: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 44177e9b64b5..702ae4cd3d0c 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -367,7 +367,7 @@ &pcie2a {
<0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
@@ -388,7 +388,7 @@ &pcie3a {
<0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 17/37] arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +-
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
index bf18c4852081..b1ad1d7c346a 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
@@ -546,7 +546,7 @@ &mdss_dp_out {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index bb5a42b038f1..3a9fbef89aff 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -523,7 +523,7 @@ &lpass_va_macro {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@@ -540,7 +540,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index a5ad796cb65d..e0275430ef82 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -685,7 +685,7 @@ &mdss_dsi_phy {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
@@ -704,7 +704,7 @@ &pcie0_phy {
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
index f47efca42d48..681a9ff5ef77 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
@@ -813,7 +813,7 @@ &mdss_dsi_phy {
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
--
2.34.1
^ permalink raw reply related
* [PATCH v2 19/37] arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcieport0 and
pcieport1. Add the missing pcieport1 label to the pcie1 root port
node to allow board-level overrides. Move perst-gpios/wake-gpios from
the &pcie0/&pcie1 controller overrides to the respective &pcieport0/
&pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios
to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 16 ++++++++++------
arch/arm64/boot/dts/qcom/lemans.dtsi | 12 +++++-------
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index fe9a2cd325d4..f492a294ee5b 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -702,15 +702,17 @@ &mdss0_dp1_phy {
};
&pcie0 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
@@ -719,15 +721,17 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcieport1 {
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
index 3a6d73b485a9..d6c5a8b49fa5 100644
--- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
@@ -853,25 +853,29 @@ wake-pins {
};
&pcie0 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "okay";
};
-&pcie1 {
- perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+&pcieport0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
+&pcieport1 {
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index fe6e76351823..48d50a0dc05f 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -8678,9 +8678,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
@@ -8691,6 +8688,8 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -8851,19 +8850,18 @@ pcie1: pcie@1c10000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
status = "disabled";
- pcie@0 {
+ pcieport1: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 18/37] arm64: dts: qcom: talos: Fix PCIe wake GPIO polarity
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio, Manivannan Sadhasivam
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe WAKE# signal is active-low as defined in the PCIe Base
Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW
instead of GPIO_ACTIVE_HIGH.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +-
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 7e05f873194a..d89548a2a3f1 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -445,7 +445,7 @@ &mdss_dsi0_phy {
&pcie {
perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
index 294354c034c3..6eca3791e2b9 100644
--- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
@@ -359,7 +359,7 @@ &mdss_dsi0_phy {
&pcie {
perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related
* [PATCH v2 22/37] arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie0/&pcie1 controller overrides to the
respective &pcieport0/&pcie1_port0 nodes, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
index 5eb4626c6129..579b0a4f34eb 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -335,26 +335,30 @@ &mdss_dsi0_phy {
};
&pcie0 {
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1e_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
};
&pcie1 {
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3c_0p9>;
vdda-pll-supply = <&vreg_l3e_1p2>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 21/37] arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node. Move phys and phy-names from the controller to pcie0_port0,
adding a label to this node to allow board-level overrides. Move
perst-gpios from the &pcie controller override to &pcie0_port0 in
the board file, renaming perst-gpios to reset-gpios to match the
binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 6 ++++--
arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++----
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index a22b4501ce1e..a035546a1b97 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -101,12 +101,14 @@ pms405_s3: s3 {
&pcie {
status = "okay";
- perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&perst_state>;
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 4328c1dda898..8166ab4bf01c 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1517,12 +1517,9 @@ pcie: pcie@10000000 {
"pwr",
"ahb";
- phys = <&pcie_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1530,6 +1527,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie_phy>;
};
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 20/37] arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node. Move phys, phy-names, and perst-gpios from the controller to
pcie0_port0, adding a label to this node to allow board-level
overrides, and renaming perst-gpios to reset-gpios to match the
binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index d41b5c470c48..53e718474db6 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -928,8 +928,6 @@ pcie0: pcie@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <1>;
- phys = <&pcie_phy>;
- phy-names = "pciephy";
status = "disabled";
ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
@@ -969,9 +967,8 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -979,6 +976,9 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie_phy>;
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 23/37] arm64: dts: qcom: sa8295p: Move PCIe GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:58 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller
overrides to the respective &pcie2a_port0, &pcie3a_port0,
&pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index d28d69162427..512de3597581 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -453,15 +453,17 @@ &mdss1_dp3_phy {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -472,15 +474,17 @@ &pcie2a_phy {
&pcie3a {
num-lanes = <2>;
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -489,15 +493,17 @@ &pcie3a_phy {
};
&pcie3b {
- perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie3b_default>;
status = "okay";
};
+&pcie3b_port0 {
+ reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+};
+
&pcie3b_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -506,15 +512,17 @@ &pcie3b_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie4_default>;
status = "okay";
};
+&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+};
+
&pcie4_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 25/37] arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and newly labeled pcie1_port0, allowing
board-level overrides. Move perst-gpios/wake-gpios from the &pcie0
controller override to &pcieport0 in the board file, renaming
perst-gpios to reset-gpios to match the binding used in the root
port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 6 +++---
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 12 +++++-------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
index 71a09e76b359..6e0557f1c14b 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
+++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
@@ -357,9 +357,6 @@ &i2c10 {
};
&pcie0 {
- perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -367,6 +364,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index d65ad0df6865..804ccfbdb091 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -1337,9 +1337,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcieport0: pcie@0 {
@@ -1350,6 +1347,8 @@ pcieport0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
};
};
@@ -1464,12 +1463,9 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1477,6 +1473,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 24/37] arm64: dts: qcom: sa8540p: Move PCIe GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie2a and &pcie3a controller overrides to the
respective &pcie2a_port0 and &pcie3a_port0 nodes, renaming
perst-gpios to reset-gpios to match the binding used in the root
port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 702ae4cd3d0c..6e73fca4e1bf 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -366,15 +366,17 @@ &pcie2a {
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
<0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "disabled";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -387,15 +389,17 @@ &pcie3a {
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
<0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 26/37] arm64: dts: qcom: sc8180x: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding
labels to these nodes to allow board-level overrides. Move
perst-gpios/wake-gpios from the controller overrides to the
respective port nodes in the board files, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 7 +++++--
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 7 +++++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 +++++++++++-----------
3 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 44bf3db01d3a..c2d9dcf8ed64 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -457,14 +457,17 @@ &mdss_edp_out {
};
&pcie3 {
- perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie3_port0 {
+ reset-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
+};
+
&pcie3_phy {
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index a4644ecca536..1b50baf0271b 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -558,14 +558,17 @@ &mdss_edp_out {
};
&pcie1 {
- perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l5e_0p88>;
vdda-pll-supply = <&vreg_l3c_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index f45deb188c6c..b6966ec7790f 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1779,13 +1779,11 @@ pcie0: pcie@1c00000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1793,6 +1791,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
};
};
@@ -1898,13 +1898,11 @@ pcie3: pcie@1c08000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie3_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie3_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1912,6 +1910,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie3_phy>;
};
};
@@ -2018,13 +2018,11 @@ pcie1: pcie@1c10000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2032,6 +2030,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
};
};
@@ -2138,13 +2138,11 @@ pcie2: pcie@1c18000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie2_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2152,6 +2150,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie2_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 27/37] arm64: dts: qcom: sc8280xp: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0,
and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 24 +++++++++++++--------
.../boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 14 ++++++------
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++++++--------
.../boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 22 +++++++++++--------
.../boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 14 ++++++------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++-------------
6 files changed, 67 insertions(+), 54 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index c53e00cae465..4c2700e9b00d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -628,9 +628,6 @@ keyboard@68 {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -639,6 +636,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -647,9 +649,6 @@ &pcie2a_phy {
};
&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@@ -658,6 +657,11 @@ &pcie3a {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -668,9 +672,6 @@ &pcie3a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@@ -679,6 +680,11 @@ &pcie4 {
status = "okay";
};
+&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+};
+
&pcie4_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
index 9819454abe13..1aba18ae301d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
@@ -739,9 +739,6 @@ &mdss0_dp1_out {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -750,6 +747,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -760,9 +762,6 @@ &pcie2a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -772,6 +771,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index d84ca010ab9d..603184a7c06c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -933,9 +933,6 @@ keyboard@68 {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -944,6 +941,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -952,9 +954,6 @@ &pcie2a_phy {
};
&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@@ -963,6 +962,11 @@ &pcie3a {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -973,9 +977,6 @@ &pcie3a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@@ -985,6 +986,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
index f2b4470d4407..4dd287e6fb95 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
@@ -486,9 +486,6 @@ &mdss0_dp1_out {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -497,6 +494,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -505,9 +507,6 @@ &pcie2a_phy {
};
&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie3a_default>;
@@ -516,6 +515,11 @@ &pcie3a {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
@@ -526,9 +530,6 @@ &pcie3a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -538,6 +539,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
index 00bbeeef6f14..21438e638da6 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
@@ -624,9 +624,6 @@ &mdss0_dp2_phy {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -635,6 +632,11 @@ &pcie2a {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l4d>;
vdda-pll-supply = <&vreg_l6d>;
@@ -645,9 +647,6 @@ &pcie2a_phy {
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -657,6 +656,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 761f229e8f47..c59d7b499008 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2220,9 +2220,6 @@ pcie4: pcie@1c00000 {
power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie4_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie4_port0: pcie@0 {
@@ -2233,6 +2230,8 @@ pcie4_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie4_phy>;
};
};
@@ -2331,9 +2330,6 @@ pcie3b: pcie@1c08000 {
power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie3b_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie3b_port0: pcie@0 {
@@ -2344,6 +2340,8 @@ pcie3b_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie3b_phy>;
};
};
@@ -2442,9 +2440,6 @@ pcie3a: pcie@1c10000 {
power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie3a_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie3a_port0: pcie@0 {
@@ -2455,6 +2450,8 @@ pcie3a_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie3a_phy>;
};
};
@@ -2556,9 +2553,6 @@ pcie2b: pcie@1c18000 {
power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie2b_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie2b_port0: pcie@0 {
@@ -2569,6 +2563,8 @@ pcie2b_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie2b_phy>;
};
};
@@ -2667,9 +2663,6 @@ pcie2a: pcie@1c20000 {
power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie2a_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie2a_port0: pcie@0 {
@@ -2680,6 +2673,8 @@ pcie2a_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie2a_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 28/37] arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 13 +++++++++----
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 ++++++++----
arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++--------
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 24c0e97bb122..ad00f436800d 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -618,15 +618,17 @@ &mss_pil {
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
status = "okay";
@@ -636,12 +638,15 @@ &pcie0_phy {
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 091568642faa..c173b870c943 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -510,14 +510,16 @@ &mss_pil {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l26a_1p2>;
@@ -526,14 +528,16 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 4ae8627d6dbc..efaa71a1d13c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2394,12 +2394,9 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2407,6 +2404,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
};
};
@@ -2524,12 +2523,9 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2537,6 +2533,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 29/37] arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to pcie0_port0 and pcie1_port0, adding labels to
these nodes to allow board-level overrides, and renaming perst-gpios
to reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 8da494de4308..f13c67e93db3 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1901,18 +1901,12 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1920,6 +1914,10 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
};
@@ -2019,10 +2017,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -2030,7 +2024,7 @@ pcie1: pcie@1c08000 {
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2038,6 +2032,9 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 30/37] arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to the existing pcieport0 and newly labeled
pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename
perst-gpios to reset-gpios to match the binding used in the root
port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++++++++++++++--------------------
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index eca66d1c1c5b..a5e2a16f6213 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2198,12 +2198,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
dma-coherent;
@@ -2218,6 +2212,10 @@ pcieport0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
+ reset-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>;
};
};
@@ -2325,19 +2323,13 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2345,6 +2337,10 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
+ reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>;
};
};
@@ -2452,19 +2448,13 @@ pcie2: pcie@1c10000 {
power-domains = <&gcc PCIE_2_GDSC>;
- phys = <&pcie2_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2472,6 +2462,10 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie2_phy>;
+ reset-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 31/37] arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board file,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++--------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0897ed1bbc6f..9a14973fd972 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -493,12 +493,14 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
-
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l5b_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
@@ -507,15 +509,17 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index c830953156ec..4515a1ccb930 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1583,12 +1583,9 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1596,6 +1593,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
};
};
@@ -1692,12 +1691,9 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1705,6 +1701,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 32/37] arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to the existing pcieport0 and newly labeled
pcie1_port0, allowing board-level overrides. Rename perst-gpios to
reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index acb36aaaf20b..f5f2c2690311 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2031,12 +2031,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -2080,6 +2074,10 @@ pcieport0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
};
};
@@ -2196,12 +2194,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -2277,7 +2269,7 @@ opp-32000000-4 {
};
};
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2285,6 +2277,10 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 33/37] arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and newly labeled pcie1_port0, allowing
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 14 ++++++++------
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 7 +++++--
.../boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 +++++---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++-------
6 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 4709eb34521d..1488ff8b7bed 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1003,9 +1003,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1013,6 +1010,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1037,15 +1037,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3c_0p9>;
vdda-pll-supply = <&vreg_l3e_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 7703ebfc1b67..e44f6a8877bd 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,15 +739,17 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "okay";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1e_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
@@ -756,15 +758,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3c_0p91>;
vdda-pll-supply = <&vreg_l3e_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 5ce81ac3ab4c..1fe6a8bf0fbc 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -903,9 +903,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -913,6 +910,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
index cf4e4e9d9e26..0ff9f3850b0c 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -510,13 +510,16 @@ &i2c_master_hub_0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1e_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index d23fe714bd27..678e58694b8a 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -584,15 +584,17 @@ cirrus,gpio-ctrl2 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&pm8550vs_2_l1>;
vdda-pll-supply = <&pm8550vs_2_l3>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6..a8eccaebcf2d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2033,9 +2033,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
operating-points-v2 = <&pcie0_opp_table>;
status = "disabled";
@@ -2100,6 +2097,8 @@ pcieport0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
};
};
@@ -2213,9 +2212,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
operating-points-v2 = <&pcie1_opp_table>;
status = "disabled";
@@ -2288,7 +2284,7 @@ opp-32000000-4 {
};
};
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2296,6 +2292,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 34/37] arm64: dts: qcom: talos: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcie_port0, and
move perst-gpios/wake-gpios from the &pcie controller overrides to the
&pcie_port0 node in the board files, renaming perst-gpios to reset-gpios
to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 +++++---
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 8 +++++---
arch/arm64/boot/dts/qcom/talos.dtsi | 5 ++---
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index d89548a2a3f1..94a6849566f8 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -444,15 +444,17 @@ &mdss_dsi0_phy {
};
&pcie {
- perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
index 6eca3791e2b9..619880b0ddc6 100644
--- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
@@ -358,15 +358,17 @@ &mdss_dsi0_phy {
};
&pcie {
- perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index ff5afbfce2a4..6f5f468ca4d6 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -1337,9 +1337,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie_phy>;
- phy-names = "pciephy";
-
max-link-speed = <2>;
operating-points-v2 = <&pcie_opp_table>;
@@ -1371,6 +1368,8 @@ pcie_port0: pcie@0 {
#size-cells = <2>;
ranges;
bus-range = <0x01 0xff>;
+
+ phys = <&pcie_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 35/37] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and pcie1_port0, allowing board-level
overrides. Move perst-gpios/wake-gpios from the controller overrides
to the respective port nodes in the board files, renaming perst-gpios
to reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 14 ++++++++------
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 14 ++++++++------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------
5 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
index 2123312d88f6..74a286bf7696 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
@@ -1074,9 +1074,6 @@ &mdss_dp0_out {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1084,6 +1081,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1108,15 +1108,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_port0 {
/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
usb-controller@0 {
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index 775ce9f2dba0..02f8760212a9 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -942,9 +942,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -952,6 +949,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -976,15 +976,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3e_0p9>;
vdda-pll-supply = <&vreg_l3i_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 8cc0d2cb3515..08107a559292 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -642,15 +642,17 @@ &mdss_dsi0_phy {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1i_0p88>;
vdda-pll-supply = <&vreg_l3i_1p2>;
@@ -659,15 +661,17 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l3e_0p9>;
vdda-pll-supply = <&vreg_l3i_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index c302996a7857..a18c01a48e4f 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -936,9 +936,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -946,6 +943,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 1604bc8cff37..fc6fc4d7e39d 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3644,9 +3644,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
num-lanes = <2>;
bus-range = <0 0xff>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
@@ -3716,6 +3713,8 @@ pcieport0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie0_phy>;
};
};
@@ -3837,9 +3836,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
num-lanes = <2>;
bus-range = <0 0xff>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
dma-coherent;
#address-cells = <3>;
@@ -3925,6 +3921,8 @@ pcie1_port0: pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pcie1_phy>;
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 36/37] arm64: dts: qcom: kodiak: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per-root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcie0_port and
pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1
controller overrides to the respective &pcie0_port/&pcie1_port0 nodes
in the board files, renaming perst-gpios to reset-gpios to match the
binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 10 ++++------
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 15 ++++++++++-----
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 16 ++++++++++------
.../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 4 ++--
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++--
.../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 14 ++++++++------
.../arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++-
9 files changed, 54 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0..52887643e1a4 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -2286,9 +2286,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc GCC_PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_clkreq_n>;
dma-coherent;
@@ -2300,6 +2297,8 @@ pcie0_port: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2416,9 +2415,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc GCC_PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>;
@@ -2434,6 +2430,8 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
index b1ad1d7c346a..92023aac967d 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
@@ -545,15 +545,17 @@ &mdss_dp_out {
};
&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
status = "okay";
};
+&pcie0_port {
+ reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
@@ -562,8 +564,6 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@@ -572,6 +572,11 @@ &pcie1 {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 3a9fbef89aff..d0639eea398e 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -522,15 +522,17 @@ &lpass_va_macro {
};
&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
status = "okay";
};
+&pcie0_port {
+ reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
@@ -539,9 +541,6 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
@@ -559,6 +558,11 @@ &pcie1 {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 83908db335af..8e65a63a533f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -49,8 +49,6 @@ st33htpm0: tpm@0 {
};
&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
@@ -75,6 +73,8 @@ &pcie0_phy {
};
&pcie0_port {
+ reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e393ccf1884a..3a7998f7ca55 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -824,8 +824,6 @@ &mdss_edp_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@@ -850,6 +848,8 @@ &pcie1_phy {
};
&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
index e0275430ef82..65687a6aeb6f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
@@ -684,9 +684,6 @@ &mdss_dsi_phy {
};
&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
<&pcie0_wake_n>;
@@ -695,6 +692,11 @@ &pcie0 {
status = "okay";
};
+&pcie0_port {
+ reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
@@ -703,9 +705,6 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
<&pcie1_wake_n>;
@@ -732,6 +731,9 @@ &pcie1_phy {
};
&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
index 681a9ff5ef77..e5c549c794a9 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
@@ -812,9 +812,6 @@ &mdss_dsi_phy {
};
&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
<&pcie0_wake_n>;
@@ -823,6 +820,11 @@ &pcie0 {
status = "okay";
};
+&pcie0_port {
+ reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
@@ -831,9 +833,6 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
<&pcie1_wake_n>;
@@ -842,6 +841,11 @@ &pcie1 {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index 5c5e4f1dd221..9198377c2a8c 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -472,10 +472,13 @@ &pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&pp3300_ssd>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+};
+
&pm8350c_pwm {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 8cac4ce9c851..655192adbd5d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -418,7 +418,6 @@ &lpass_va_macro {
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>;
@@ -426,6 +425,10 @@ &pcie1 {
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+};
+
&pcie1_phy {
status = "okay";
--
2.34.1
^ permalink raw reply related
* [PATCH v2 37/37] arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node
From: Krishna Chaitanya Chundru @ 2026-06-11 4:59 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
cros-qcom-dts-watchers, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Krishna Chaitanya Chundru
In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com>
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these
nodes to allow board-level overrides. Move perst-gpios/wake-gpios
from the controller overrides to the respective port nodes in the
board files, renaming perst-gpios to reset-gpios to match the binding
used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chaitanya.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 15 ++++++++++++---
.../arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 5 ++++-
.../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 +++-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 21 +++++++++------------
5 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 0c076852b494..ad435a13ba24 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -458,23 +458,32 @@ hdmi_ddc_suspend: hdmi-ddc-suspend-state {
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+};
+
&pcie2 {
status = "okay";
- perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie2_port0 {
+ reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
index a4dcc88bb01f..7a3f8afae22d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
@@ -210,12 +210,15 @@ &mss_pil {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index 5b42c266557a..20b5eeef46e4 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -191,13 +191,16 @@ &mmcc {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>;
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 2abcc733dad8..3c70a9be45d2 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -278,8 +278,10 @@ &pcie0 {
/* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
+};
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2f67e665996f..8db1448e5e61 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1900,9 +1900,6 @@ pcie0: pcie@600000 {
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_0>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
@@ -1951,7 +1948,7 @@ pcie0: pcie@600000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -1959,6 +1956,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pciephy_0>;
};
};
@@ -1977,9 +1976,6 @@ pcie1: pcie@608000 {
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_1>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
@@ -2028,7 +2024,7 @@ pcie1: pcie@608000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2036,6 +2032,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pciephy_1>;
};
};
@@ -2052,9 +2050,6 @@ pcie2: pcie@610000 {
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_2>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
@@ -2102,7 +2097,7 @@ pcie2: pcie@610000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2110,6 +2105,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+
+ phys = <&pciephy_2>;
};
};
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 20/37] arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node
From: sashiko-bot @ 2026-06-11 5:12 UTC (permalink / raw)
To: Krishna Chaitanya Chundru; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260611-wake-v2-20-2744251b1181@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch completely drops `phy-names` instead of moving it to the root port node as claimed by the commit message.
--
commit ed76b5fde29c9cdbab990c6d9d7c1352cdfa8910
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node
This commit updates the device tree for MSM8998 by shifting the PCIe phy
and perst GPIO properties from the root complex controller node to the
root port child node. It also renames perst-gpios to reset-gpios to
align with the root port binding schema.
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
[ ... ]
> @@ -928,8 +928,6 @@ pcie0: pcie@1c00000 {
> #address-cells = <3>;
> #size-cells = <2>;
> num-lanes = <1>;
> - phys = <&pcie_phy>;
> - phy-names = "pciephy";
> status = "disabled";
[ ... ]
> @@ -969,9 +967,8 @@ pcie0: pcie@1c00000 {
>
> power-domains = <&gcc PCIE_0_GDSC>;
> iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
> - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
>
> - pcie@0 {
> + pcie0_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> @@ -979,6 +976,9 @@ pcie@0 {
> #address-cells = <3>;
> #size-cells = <2>;
> ranges;
> +
> + phys = <&pcie_phy>;
> + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
[Severity: Low]
The commit message explicitly states: "Move phys, phy-names, and perst-gpios
from the controller to pcie0_port0". However, it looks like phy-names was
dropped from the parent node and not added to this child node as described.
While the kernel driver's root port parsing might ignore the phy-names
property anyway, does this omission unintentionally violate the behavior
described in the commit message?
> };
> };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260611-wake-v2-0-2744251b1181@oss.qualcomm.com?part=20
^ permalink raw reply
* Re: [PATCH v2 21/37] arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node
From: sashiko-bot @ 2026-06-11 5:13 UTC (permalink / raw)
To: Krishna Chaitanya Chundru; +Cc: conor+dt, robh, devicetree
In-Reply-To: <20260611-wake-v2-21-2744251b1181@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [Medium] The commit message inaccurately claims to move `phy-names` to `pcie0_port0`, but the property is actually removed entirely.
Pre-existing issues:
- [High] Moving to the modern DT layout exposes a `phy_init` leak on `-EPROBE_DEFER` in the PCIe driver.
--
commit 496473598a57288f328fa2236e944d3bb666608e
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node.
> Move phys and phy-names from the controller to pcie0_port0,
> adding a label to this node to allow board-level overrides.
[Severity: Medium]
This isn't a bug, but the commit message states that phy-names is moved to
pcie0_port0, while the patch actually drops the property entirely. Could
the commit message be updated to accurately reflect that phy-names is being
removed?
[ ... ]
> diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> index a22b4501ce1ef..a035546a1b97d 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> @@ -101,12 +101,14 @@ pms405_s3: s3 {
> &pcie {
> status = "okay";
>
> - perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
> -
> pinctrl-names = "default";
> pinctrl-0 = <&perst_state>;
> };
>
> +&pcie0_port0 {
> + reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
[Severity: High]
This isn't a bug introduced by this patch, but does moving to this modern
DT layout expose a resource leak in the PCIe driver?
In drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_parse_port():
ret = phy_init(phy);
if (ret)
return ret;
INIT_LIST_HEAD(&port->perst);
ret = qcom_pcie_parse_perst(pcie, port, node);
if (ret)
return ret;
If qcom_pcie_parse_perst() returns an error like -EPROBE_DEFER when
requesting reset-gpios, does this leak the phy initialization since
phy_exit() isn't called on this failure path?
> +};
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260611-wake-v2-0-2744251b1181@oss.qualcomm.com?part=21
^ permalink raw reply
* Re: [PATCH v2 22/37] arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node
From: sashiko-bot @ 2026-06-11 5:15 UTC (permalink / raw)
To: Krishna Chaitanya Chundru; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260611-wake-v2-22-2744251b1181@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit introduces a build failure by referencing an undefined Device Tree label `&pcie1_port0`.
--
commit 9033bf5c4daddefb447ddf13a1046f9e3fb9d91c
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node
The commit moves PCIe GPIO properties from the Root Complex controller node
to the respective root port nodes in the qcs8550-aim300 device tree. It
also renames the perst-gpios property to reset-gpios to match the bindings
for the root port context.
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
> index 5eb4626c61290..579b0a4f34ebc 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
[ ... ]
> &pcie1 {
> - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie1_default_state>;
> pinctrl-names = "default";
> };
>
> +&pcie1_port0 {
[Severity: Low]
Will this cause a build failure during dtc compilation?
The &pcie1_port0 label does not appear to be defined in sm8550.dtsi or any
included file at this point in the git history.
While this is fixed later in the patch series by commit
0b50a2794d4f364375fa966171b8c7483fa1b1b6 ("arm64: dts: qcom: sm8550: Move
PCIe phy and GPIOs to root port node"), does ordering the board patch before
the base SoC dtsi patch break kernel bisectability?
> + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260611-wake-v2-0-2744251b1181@oss.qualcomm.com?part=22
^ permalink raw reply
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