* [PATCH net-next v7 05/12] net: phylink: support late PCS provider attach
From: Christian Marangi @ 2026-06-15 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm
In-Reply-To: <20260615122950.22281-1-ansuelsmth@gmail.com>
Add support for late PCS provider attachment to a phylink instance.
This works by creating a global notifier for the PCS provider and
making each phylink instance that makes use of fwnode subscribe to
this notifier.
The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time
a new PCS provider is added.
phylink will then react to this event and will call the new function
fwnode_phylink_pcs_get_from_fwnode() that will check if the PCS fwnode
provided by the event is present in the pcs-handle property of the
phylink instance.
If a related PCS is found, then such PCS is added to the phylink
instance PCS list.
Then we link the PCS to the phylink instance and we refresh the supported
interfaces of the phylink instance.
Finally we check if we are in a major_config_failed scenario and trigger
an interface reconfiguration in the next phylink resolve.
In the example scenario where the link was previously torn down due to
removal of PCS, the link will be established again as the PCS came back
and is now available to phylink.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/pcs.c | 49 ++++++++++++++++++++++++++++++++
drivers/net/phy/phylink.c | 57 +++++++++++++++++++++++++++++++++++++
include/linux/pcs/pcs.h | 60 +++++++++++++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
index 67f9716f48fd..713b2ec22c97 100644
--- a/drivers/net/pcs/pcs.c
+++ b/drivers/net/pcs/pcs.c
@@ -22,6 +22,19 @@ struct fwnode_pcs_provider {
static LIST_HEAD(fwnode_pcs_providers);
static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
+
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_unregister(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(unregister_fwnode_pcs_notifier);
struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
void *data)
@@ -55,6 +68,10 @@ int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
fwnode_dev_initialized(fwnode, true);
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_ADD,
+ fwnode);
+
return 0;
}
EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
@@ -150,6 +167,38 @@ struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int in
}
EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ struct fwnode_reference_args pcsspec;
+ int index = 0;
+ int ret;
+
+ /* Loop until we find a matching PCS node or
+ * fwnode_parse_pcsspec() returns error
+ * if we don't have any other PCS reference to check.
+ */
+ while (true) {
+ ret = fwnode_parse_pcsspec(fwnode, index, NULL, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ /* Exit loop if we found the matching PCS node */
+ if (pcsspec.fwnode == pcs_fwnode) {
+ fwnode_handle_put(pcsspec.fwnode);
+ break;
+ }
+
+ /* Check the next PCS reference */
+ fwnode_handle_put(pcsspec.fwnode);
+ index++;
+ }
+
+ return fwnode_pcs_get(fwnode, index);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
{
struct fwnode_reference_args out_args;
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index ca4dad4b140a..0734c98498a9 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/phylink.h>
@@ -62,6 +63,7 @@ struct phylink {
/* List of available PCS */
struct list_head pcs_list;
+ struct notifier_block fwnode_pcs_nb;
/* What interface are supported by the current link.
* Can change on removal or addition of new PCS.
@@ -1997,6 +1999,51 @@ static int phylink_fill_available_pcs(struct phylink *pl,
return ret;
}
+static int pcs_provider_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+ struct fwnode_handle *pcs_fwnode = data;
+ struct phylink_pcs *pcs;
+
+ /* Check if the just added PCS provider is
+ * in the phylink instance pcs-handle property.
+ */
+ pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+ pcs_fwnode);
+ if (IS_ERR(pcs))
+ return NOTIFY_DONE;
+
+ /* Add the PCS */
+ rtnl_lock();
+
+ mutex_lock(&pl->state_mutex);
+
+ /* Link PCS with phylink */
+ list_add(&pcs->list, &pl->pcs_list);
+ pcs->phylink = pl;
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ /* Force an interface reconfig if major config fail */
+ if (pl->major_config_failed)
+ pl->force_major_config = true;
+
+ mutex_unlock(&pl->state_mutex);
+
+ rtnl_unlock();
+
+ phylink_run_resolve(pl);
+
+ return NOTIFY_OK;
+}
+
/**
* phylink_create() - create a phylink instance
* @config: a pointer to the target &struct phylink_config
@@ -2068,6 +2115,12 @@ struct phylink *phylink_create(struct phylink_config *config,
pl->supported_interfaces,
pcs->supported_interfaces);
+ /* Register notifier for late PCS attach */
+ if (!phy_interface_empty(config->pcs_interfaces)) {
+ pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+ register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ }
+
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
@@ -2151,6 +2204,10 @@ void phylink_destroy(struct phylink *pl)
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Unregister notifier for late PCS attach */
+ if (pl->fwnode_pcs_nb.notifier_call)
+ unregister_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+
/* Drop link between PCS and phylink */
list_for_each_entry(pcs, &pl->pcs_list, list)
pcs->phylink = NULL;
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
index df1e6f32cfad..9de3f273428e 100644
--- a/include/linux/pcs/pcs.h
+++ b/include/linux/pcs/pcs.h
@@ -4,7 +4,36 @@
#include <linux/phylink.h>
+enum fwnode_pcs_notify_event {
+ FWNODE_PCS_PROVIDER_ADD,
+};
+
#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns: 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
+/**
+ * unregister_fwnode_pcs_notifier - Unregister a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Unregisters a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain.
+ *
+ * Returns: 0 or a negative error.
+ */
+int unregister_fwnode_pcs_notifier(struct notifier_block *nb);
+
/**
* fwnode_pcs_get - Retrieves a PCS from a firmware node
* @fwnode: firmware node
@@ -20,6 +49,25 @@
struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
unsigned int index);
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ * by the firmware node from a
+ * firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode);
+
/**
* fwnode_phylink_pcs_count - count PCS entries described in firmware node
* @fwnode: firmware node
@@ -53,12 +101,24 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
struct phylink_pcs **available_pcs,
unsigned int num_pcs);
#else
+static inline int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
int index)
{
return ERR_PTR(-ENOENT);
}
+static inline struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ return ERR_PTR(-ENOENT);
+}
+
static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
{
return 0;
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v7 04/12] net: pcs: implement Firmware node support for PCS driver
From: Christian Marangi @ 2026-06-15 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm
Cc: Daniel Golle
In-Reply-To: <20260615122950.22281-1-ansuelsmth@gmail.com>
Implement the foundation of Firmware node support for PCS driver.
To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.
PCS driver will have to call fwnode_pcs_add_provider() and pass the
firmware node pointer and a xlate function to return the correct PCS for
the passed #pcs-cells.
This will register the PCS in a global list of providers so that
consumer can access it.
The consumer will then use fwnode_pcs_get() to get the actual PCS by
passing the firmware node pointer and the index for #pcs-cells.
For a simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function fwnode_pcs_simple_get() is
provided.
For an advanced implementation a custom xlate function is required.
On removal the PCS driver should first delete itself from the provider
list using fwnode_pcs_del_provider() and then call phylink_release_pcs()
on every PCS the driver provides.
Generic functions fwnode_phylink_pcs_count() and fwnode_phylink_pcs_parse()
are provided for MAC driver that will declare PCS in DT (or ACPI).
Function fwnode_phylink_pcs_count() will parse "pcs-handle" property and
will return the number of PCS entries described in the passed firmware
node.
Function fwnode_phylink_pcs_parse() will parse "pcs-handle" property and
fill the passed available_pcs array with the available PCS found up to passed
num_pcs value. It's worth to mention that this function will ignore PCS
that still needs to be probed (returning -ENODEV) and such PCS won't be
added to the available_pcs array.
Co-developed-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/Kconfig | 6 +
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs.c | 208 +++++++++++++++++++++++++++++++
include/linux/pcs/pcs-provider.h | 41 ++++++
include/linux/pcs/pcs.h | 75 +++++++++++
5 files changed, 331 insertions(+)
create mode 100644 drivers/net/pcs/pcs.c
create mode 100644 include/linux/pcs/pcs-provider.h
create mode 100644 include/linux/pcs/pcs.h
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index e417fd66f660..2ce89d4bff6b 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,12 @@
menu "PCS device drivers"
+config FWNODE_PCS
+ bool "PCS Firmware Node"
+ depends on (ACPI || OF)
+ help
+ Firmware node PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..3005cdd89ab7 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_FWNODE_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 000000000000..67f9716f48fd
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+ struct list_head link;
+
+ struct fwnode_handle *fwnode;
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+ void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return 0;
+
+ pp = kzalloc_obj(*pp);
+ if (!pp)
+ return -ENOMEM;
+
+ pp->fwnode = fwnode_handle_get(fwnode);
+ pp->data = data;
+ pp->get = get;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_add(&pp->link, &fwnode_pcs_providers);
+ mutex_unlock(&fwnode_pcs_mutex);
+ pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+ fwnode_dev_initialized(fwnode, true);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+ if (pp->fwnode == fwnode) {
+ list_del(&pp->link);
+ fwnode_dev_initialized(pp->fwnode, false);
+ fwnode_handle_put(pp->fwnode);
+ kfree(pp);
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode,
+ unsigned int index, const char *name,
+ struct fwnode_reference_args *out_args)
+{
+ int ret;
+
+ if (!fwnode)
+ return -EINVAL;
+
+ if (name) {
+ index = fwnode_property_match_string(fwnode, "pcs-names",
+ name);
+ if (index < 0)
+ return index;
+ }
+
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, out_args);
+ if (ret || (name && index < 0))
+ return ret;
+
+ return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+ struct fwnode_pcs_provider *provider;
+ struct phylink_pcs *pcs = ERR_PTR(-ENODEV);
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+ if (provider->fwnode == pcsspec->fwnode) {
+ pcs = provider->get(pcsspec, provider->data);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index, const char *con_id)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+ fwnode_handle_put(pcsspec.fwnode);
+
+ return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, unsigned int index)
+{
+ return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ struct fwnode_reference_args out_args;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, &out_args);
+ /* We expect to reach an -ENOENT error while counting */
+ if (ret)
+ break;
+
+ fwnode_handle_put(out_args.fwnode);
+ index++;
+ }
+
+ return index;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_count);
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ unsigned int i, found = 0;
+
+ if (!available_pcs)
+ return -EINVAL;
+
+ if (!fwnode_property_present(fwnode, "pcs-handle"))
+ return -ENODEV;
+
+ for (i = 0; i < num_pcs; i++) {
+ struct phylink_pcs *pcs;
+
+ pcs = fwnode_pcs_get(fwnode, i);
+ if (IS_ERR(pcs)) {
+ /*
+ * Ignore -ENODEV error for PCS that still
+ * needs to probe.
+ */
+ if (PTR_ERR(pcs) == -ENODEV)
+ continue;
+
+ return PTR_ERR(pcs);
+ }
+
+ available_pcs[found] = pcs;
+ found++;
+ }
+
+ return found;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..ae51c108147e
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns: the PCS pointed by data.
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @fwnode: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns: 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..df1e6f32cfad
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns: a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -ENODEV if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed).
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ unsigned int index);
+
+/**
+ * fwnode_phylink_pcs_count - count PCS entries described in firmware node
+ * @fwnode: firmware node
+ *
+ * Helper function to count the number of PCS entries referenced by the
+ * "pcs-handle" property in a firmware node.
+ *
+ * Note that this function counts all PCS references in the firmware node,
+ * regardless of whether the corresponding PCS devices are already probed.
+ *
+ * Returns: number of PCS entries described in the firmware node.
+ */
+unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode);
+
+/**
+ * fwnode_phylink_pcs_parse - parse available PCS from firmware node
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: maximum number of PCS entries to scan
+ *
+ * Helper function that parses PCS references from the "pcs-handle"
+ * property of a firmware node and fills @available_pcs with PCS that are
+ * currently available up to @num_pcs.
+ *
+ * Only PCS that are currently available are stored in @available_pcs.
+ * PCS that returns -ENODEV are skipped.
+ *
+ * Returns: number of PCS stored in @available_pcs, or negative error code.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs);
+#else
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline unsigned int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode)
+{
+ return 0;
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_pcs)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v7 03/12] net: phylink: add phylink_release_pcs() to externally release a PCS
From: Christian Marangi @ 2026-06-15 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm
In-Reply-To: <20260615122950.22281-1-ansuelsmth@gmail.com>
Add phylink_release_pcs() to externally release a PCS from a phylink
instance. This can be used to handle case when a single PCS needs to be
removed and the phylink instance needs to be refreshed.
On calling phylink_release_pcs(), the PCS will be removed from the
phylink internal PCS list and the phylink supported_interfaces value is
reparsed with the remaining PCS interfaces.
Also a phylink resolve is triggered to handle the PCS removal.
The flag force_major_config is set to make phylink resolve reconfigure
the interface (even if it didn't change).
This is needed to handle the special case when the current PCS used
by phylink is removed and a major_config is needed to propagae the
configuration change. With this option enabled we also force mac_config
even if the PHY link is not up for the in-band case.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 53 +++++++++++++++++++++++++++++++++++++++
include/linux/phylink.h | 2 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index cb07184ce82f..ca4dad4b140a 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -158,6 +158,7 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
static void phylink_run_resolve(struct phylink *pl);
+static void phylink_pcs_disable(struct phylink_pcs *pcs);
/**
* phylink_set_port_modes() - set the port type modes in the ethtool mask
@@ -918,6 +919,58 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)
}
}
+/**
+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list
+ * @pcs: a pointer to the phylink_pcs struct to be released
+ *
+ * This function release a PCS from the phylink PCS available list if
+ * actually in use. It also refreshes the supported interfaces of the
+ * phylink instance by copying the supported interfaces from the phylink
+ * conf and merging the supported interfaces of the remaining available PCS
+ * in the list and trigger a resolve.
+ */
+void phylink_release_pcs(struct phylink_pcs *pcs)
+{
+ struct phylink *pl;
+
+ ASSERT_RTNL();
+
+ pl = pcs->phylink;
+ if (!pl)
+ return;
+
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+
+ mutex_lock(&pl->state_mutex);
+
+ /* Check if we are removing the PCS currently
+ * in use by phylink. If this is the case,
+ * force phylink resolve to reconfigure the interface
+ * mode, disable the current PCS and set the
+ * phylink PCS to NULL.
+ */
+ if (pl->pcs == pcs) {
+ phylink_pcs_disable(pl->pcs);
+
+ pl->force_major_config = true;
+ pl->pcs = NULL;
+ }
+
+ mutex_unlock(&pl->state_mutex);
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ phylink_run_resolve(pl);
+}
+EXPORT_SYMBOL_GPL(phylink_release_pcs);
+
static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
phy_interface_t interface)
{
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index ca9dfc142388..15e6b1a39dfe 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -751,6 +751,8 @@ void phylink_disconnect_phy(struct phylink *);
int phylink_set_fixed_link(struct phylink *,
const struct phylink_link_state *);
+void phylink_release_pcs(struct phylink_pcs *pcs);
+
void phylink_mac_change(struct phylink *, bool up);
void phylink_pcs_change(struct phylink_pcs *, bool up);
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v7 02/12] net: phylink: introduce internal phylink PCS handling
From: Christian Marangi @ 2026-06-15 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm
In-Reply-To: <20260615122950.22281-1-ansuelsmth@gmail.com>
Introduce internal handling of PCS for phylink. This is an alternative
way to .mac_select_pcs that moves the selection logic of the PCS entirely
to phylink with the usage of the supported_interface value in the PCS
struct.
MAC should now provide a callback to fill the available PCS in
phylink_config in .fill_available_pcs and fill the .num_possible_pcs with
the number of elements in the array. MAC should also define a new bitmap,
pcs_interfaces, in phylink_config to define for what interface mode a
dedicated PCS is required.
On phylink_create(), an array of PCS pointer is allocated of size
.num_possible_pcs from phylink_config and .fill_available_pcs from
phylink_config is called passing as args the just allocated array and
the number of possible element in it.
MAC will fill this passed array with all the available PCS.
This array is then parsed and a linked list of PCS is created based on
the allocated PCS array filled by MAC via .fill_available_pcs().
Every PCS in phylink PCS list gets then linked to the phylink instance
by setting the phylink value in phylink_pcs struct to the phylink instance.
Also the supported_interface value in phylink struct is updated with
the new supported_interface from the provided PCS.
On phylink_destroy(), every PCS in phylink PCS list is unlinked from the
phylink instance by setting the phylink value in phylink_pcs struct to NULL
and removed from the PCS list.
phylink_validate_mac_and_pcs(), phylink_major_config() and
phylink_inband_caps() are updated to support this new implementation
with the PCS list stored in phylink.
They will make use of phylink_validate_pcs_interface() that will loop
for every PCS in the phylink PCS available list and find one that supports
the passed interface.
phylink_validate_pcs_interface() applies the same logic of .mac_select_pcs
where if a supported_interface value is not set for the PCS struct, then
it's assumed every interface is supported.
A MAC is required to implement either a .mac_select_pcs or make use of
the PCS list implementation. Implementing both will result in a fail
on phylink_create().
A MAC defining .num_possible_pcs in phylink_config MUST also define a
.fill_available_pcs or phylink_create() will fail with an negative error.
phylink value in phylink_pcs struct with this implementation is used to
track from PCS side when it's attached to a phylink instance. PCS driver
will make use of this information to correctly detach from a phylink
instance if needed.
phylink_pcs_change() is also changed to verify that the PCS that triggered
a link change is the one that is currently used by the phylink instance.
The .mac_select_pcs implementation is not changed but it's expected that
every MAC driver migrates to the new implementation to later deprecate
and remove .mac_select_pcs.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 196 ++++++++++++++++++++++++++++++++++----
include/linux/phylink.h | 16 ++++
2 files changed, 192 insertions(+), 20 deletions(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 4d59c0dd78db..cb07184ce82f 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -60,6 +60,9 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* List of available PCS */
+ struct list_head pcs_list;
+
/* What interface are supported by the current link.
* Can change on removal or addition of new PCS.
*/
@@ -154,6 +157,8 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+static void phylink_run_resolve(struct phylink *pl);
+
/**
* phylink_set_port_modes() - set the port type modes in the ethtool mask
* @mask: ethtool link mode mask
@@ -518,12 +523,29 @@ static void phylink_validate_mask_caps(unsigned long *supported,
linkmode_and(state->advertising, state->advertising, mask);
}
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* If PCS define an empty supported_interfaces value, assume
+ * all interface are supported.
+ */
+ if (phy_interface_empty(pcs->supported_interfaces))
+ return 0;
+
+ /* Ensure that this PCS supports the interface mode */
+ if (!test_bit(interface, pcs->supported_interfaces))
+ return -EINVAL;
+
+ return 0;
+}
+
static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long *supported,
struct phylink_link_state *state)
{
- struct phylink_pcs *pcs = NULL;
unsigned long capabilities;
+ struct phylink_pcs *pcs;
+ bool pcs_found = false;
int ret;
/* Get the PCS for this interface mode */
@@ -531,9 +553,24 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
if (IS_ERR(pcs))
return PTR_ERR(pcs);
+
+ pcs_found = !!pcs;
+ /*
+ * Find a PCS in available PCS list for the requested interface.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs, state->interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
}
- if (pcs) {
+ if (pcs_found) {
/* The PCS, if present, must be setup before phylink_create()
* has been called. If the ops is not initialised, print an
* error and backtrace rather than oopsing the kernel.
@@ -545,13 +582,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
return -EINVAL;
}
- /* Ensure that this PCS supports the interface which the MAC
- * returned it for. It is an error for the MAC to return a PCS
- * that does not support the interface mode.
- */
- if (!phy_interface_empty(pcs->supported_interfaces) &&
- !test_bit(state->interface, pcs->supported_interfaces)) {
- phylink_err(pl, "MAC returned PCS which does not support %s\n",
+ /* Recheck PCS to handle legacy way for .mac_select_pcs */
+ ret = phylink_validate_pcs_interface(pcs, state->interface);
+ if (ret) {
+ phylink_err(pl, "selected PCS does not support %s\n",
phy_modes(state->interface));
return -EINVAL;
}
@@ -965,12 +999,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
phy_interface_t interface)
{
struct phylink_pcs *pcs;
+ bool pcs_found = false;
- if (!pl->mac_ops->mac_select_pcs)
- return 0;
+ if (pl->mac_ops->mac_select_pcs) {
+ pcs = pl->mac_ops->mac_select_pcs(pl->config,
+ interface);
+ pcs_found = !!pcs;
+ } else if (test_bit(interface, pl->config->pcs_interfaces)) {
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs, interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
+ }
- pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
- if (!pcs)
+ if (!pcs_found)
return 0;
return phylink_pcs_inband_caps(pcs, interface);
@@ -1265,10 +1309,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
pl->major_config_failed = true;
return;
}
+ /* Find a PCS in available PCS list for the requested interface.
+ * This doesn't overwrite the previous .mac_select_pcs as either
+ * .mac_select_pcs or PCS list implementation are permitted.
+ *
+ * Skip searching if the MAC doesn't require a dedicated PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ bool pcs_found = false;
+
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs,
+ state->interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
- pcs_changed = pl->pcs != pcs;
+ if (!pcs_found) {
+ phylink_err(pl,
+ "couldn't find a PCS for %s\n",
+ phy_modes(state->interface));
+
+ pl->major_config_failed = true;
+ return;
+ }
}
+ pcs_changed = pl->pcs != pcs;
+
phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1295,11 +1365,13 @@ static void phylink_major_config(struct phylink *pl, bool restart,
if (pcs_changed) {
phylink_pcs_disable(pl->pcs);
- if (pl->pcs)
- pl->pcs->phylink = NULL;
+ if (pl->mac_ops->mac_select_pcs) {
+ if (pl->pcs)
+ pl->pcs->phylink = NULL;
- if (pcs)
- pcs->phylink = pl;
+ if (pcs)
+ pcs->phylink = pl;
+ }
pl->pcs = pcs;
}
@@ -1834,6 +1906,44 @@ int phylink_set_fixed_link(struct phylink *pl,
}
EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
+static int phylink_fill_available_pcs(struct phylink *pl,
+ struct phylink_config *config)
+{
+ struct phylink_pcs **pcss;
+ int i, ret;
+
+ if (!config->num_possible_pcs)
+ return 0;
+
+ if (!config->fill_available_pcs) {
+ dev_err(config->dev,
+ "phylink: error: num_possible_pcs defined but no fill_available_pcs\n");
+ return -EINVAL;
+ }
+
+ pcss = kzalloc_objs(*pcss, config->num_possible_pcs);
+ if (!pcss)
+ return -ENOMEM;
+
+ ret = config->fill_available_pcs(config, pcss, config->num_possible_pcs);
+ if (ret < 0)
+ goto out;
+
+ for (i = 0; i < config->num_possible_pcs; i++) {
+ struct phylink_pcs *pcs = pcss[i];
+
+ if (!pcs)
+ continue;
+
+ list_add(&pcs->list, &pl->pcs_list);
+ }
+
+out:
+ kfree(pcss);
+
+ return ret;
+}
+
/**
* phylink_create() - create a phylink instance
* @config: a pointer to the target &struct phylink_config
@@ -1855,6 +1965,7 @@ struct phylink *phylink_create(struct phylink_config *config,
phy_interface_t iface,
const struct phylink_mac_ops *mac_ops)
{
+ struct phylink_pcs *pcs;
struct phylink *pl;
int ret;
@@ -1865,6 +1976,16 @@ struct phylink *phylink_create(struct phylink_config *config,
return ERR_PTR(-EINVAL);
}
+ /*
+ * Make sure either PCS internal validation or .mac_select_pcs
+ * is used. Return error if both are defined.
+ */
+ if (config->num_possible_pcs && pl->mac_ops->mac_select_pcs) {
+ dev_err(config->dev,
+ "phylink: error: either phylink_config .num_possible_pcs or .mac_select_pcs must be used\n");
+ return ERR_PTR(-EINVAL);
+ }
+
pl = kzalloc_obj(*pl);
if (!pl)
return ERR_PTR(-ENOMEM);
@@ -1872,10 +1993,28 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->phydev_mutex);
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ INIT_LIST_HEAD(&pl->pcs_list);
+
+ /* Fill the PCS list with available PCS from phylink config */
+ ret = phylink_fill_available_pcs(pl, config);
+ if (ret < 0) {
+ kfree(pl);
+ return ERR_PTR(ret);
+ }
+
+ /* Link available PCS to phylink */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ pcs->phylink = pl;
phy_interface_copy(pl->supported_interfaces,
config->supported_interfaces);
+ /* Update supported interfaces */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
@@ -1953,10 +2092,20 @@ EXPORT_SYMBOL_GPL(phylink_create);
*/
void phylink_destroy(struct phylink *pl)
{
+ struct phylink_pcs *pcs, *tmp;
+
sfp_bus_del_upstream(pl->sfp_bus);
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Drop link between PCS and phylink */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ pcs->phylink = NULL;
+
+ /* Remove every PCS from phylink PCS list */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list)
+ list_del(&pcs->list);
+
cancel_work_sync(&pl->resolve);
kfree(pl);
}
@@ -2413,8 +2562,15 @@ void phylink_pcs_change(struct phylink_pcs *pcs, bool up)
{
struct phylink *pl = pcs->phylink;
- if (pl)
- phylink_link_changed(pl, up, "pcs");
+ /*
+ * Ignore PCS link state change if the PCS is not
+ * attached to a phylink instance or the phylink
+ * instance is not currently using this PCS.
+ */
+ if (!pl || pl->pcs != pcs)
+ return;
+
+ phylink_link_changed(pl, up, "pcs");
}
EXPORT_SYMBOL_GPL(phylink_pcs_change);
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 2bc0db3d52ac..ca9dfc142388 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -12,6 +12,7 @@ struct ethtool_cmd;
struct fwnode_handle;
struct net_device;
struct phylink;
+struct phylink_pcs;
enum {
MLO_PAUSE_NONE,
@@ -151,6 +152,8 @@ enum phylink_op_type {
* if MAC link is at %MLO_AN_FIXED mode.
* @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
* are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ * dedicated PCS is required.
* @lpi_interfaces: bitmap describing which PHY interface modes can support
* LPI signalling.
* @mac_capabilities: MAC pause/speed/duplex capabilities.
@@ -160,6 +163,10 @@ enum phylink_op_type {
* @wol_phy_legacy: Use Wake-on-Lan with PHY even if phy_can_wakeup() is false
* @wol_phy_speed_ctrl: Use phy speed control on suspend/resume
* @wol_mac_support: Bitmask of MAC supported %WAKE_* options
+ * @num_possible_pcs: num of possible phylink_pcs PCS
+ * @fill_available_pcs: callback to fill the available PCS in the passed
+ * array struct of phylink_pcs PCS available_pcs up to
+ * num_possible_pcs.
*/
struct phylink_config {
struct device *dev;
@@ -172,6 +179,7 @@ struct phylink_config {
void (*get_fixed_state)(struct phylink_config *config,
struct phylink_link_state *state);
DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+ DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
unsigned long mac_capabilities;
unsigned long lpi_capabilities;
@@ -182,6 +190,11 @@ struct phylink_config {
bool wol_phy_legacy;
bool wol_phy_speed_ctrl;
u32 wol_mac_support;
+
+ unsigned int num_possible_pcs;
+ int (*fill_available_pcs)(struct phylink_config *config,
+ struct phylink_pcs **available_pcs,
+ unsigned int num_possible_pcs);
};
void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -497,6 +510,9 @@ struct phylink_pcs {
struct phylink *phylink;
bool poll;
bool rxc_always_on;
+
+ /* private: */
+ struct list_head list;
};
/**
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v7 01/12] net: phylink: keep and use MAC supported_interfaces in phylink struct
From: Christian Marangi @ 2026-06-15 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm
In-Reply-To: <20260615122950.22281-1-ansuelsmth@gmail.com>
Add in phylink struct a copy of supported_interfaces from phylink_config
and make use of that instead of relying on phylink_config value.
This in preparation for support of PCS handling internally to phylink
where a PCS can be removed or added after the phylink is created and we
need both a reference of the supported_interfaces value from
phylink_config and an internal value that can be updated with the new
PCS info.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 087ac63f9193..4d59c0dd78db 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -60,6 +60,11 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* What interface are supported by the current link.
+ * Can change on removal or addition of new PCS.
+ */
+ DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
/* The current settings */
phy_interface_t cur_interface;
@@ -629,7 +634,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
static int phylink_validate(struct phylink *pl, unsigned long *supported,
struct phylink_link_state *state)
{
- const unsigned long *interfaces = pl->config->supported_interfaces;
+ const unsigned long *interfaces = pl->supported_interfaces;
if (state->interface == PHY_INTERFACE_MODE_NA)
return phylink_validate_mask(pl, NULL, supported, state,
@@ -1868,6 +1873,9 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ phy_interface_copy(pl->supported_interfaces,
+ config->supported_interfaces);
+
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
@@ -2026,7 +2034,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
* those which the host supports.
*/
phy_interface_and(interfaces, phy->possible_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
if (phy_interface_empty(interfaces)) {
phylink_err(pl, "PHY has no common interfaces\n");
@@ -2828,12 +2836,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
return interface;
}
- if (!test_bit(interface, pl->config->supported_interfaces)) {
+ if (!test_bit(interface, pl->supported_interfaces)) {
phylink_err(pl,
"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
phy_modes(interface), interface,
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
return PHY_INTERFACE_MODE_NA;
}
@@ -3761,14 +3769,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces,
+ pl->supported_interfaces,
(int)PHY_INTERFACE_MODE_MAX,
pl->sfp_interfaces);
/* Find the union of the supported interfaces by the PCS/MAC and
* the SFP module.
*/
- phy_interface_and(pl->sfp_interfaces, pl->config->supported_interfaces,
+ phy_interface_and(pl->sfp_interfaces, pl->supported_interfaces,
pl->sfp_interfaces);
if (phy_interface_empty(pl->sfp_interfaces)) {
phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -3939,7 +3947,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
/* Set the PHY's host supported interfaces */
phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
/* Do the initial configuration */
return phylink_sfp_config_phy(pl, phy);
--
2.53.0
^ permalink raw reply related
* [PATCH net-next v7 00/12] net: pcs: Introduce support for fwnode PCS
From: Christian Marangi @ 2026-06-15 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Simon Horman, Jonathan Corbet, Shuah Khan, Christian Marangi,
Lorenzo Bianconi, Heiner Kallweit, Russell King, Saravana Kannan,
Philipp Zabel, Nathan Chancellor, Nick Desaulniers, Bill Wendling,
Justin Stitt, netdev, devicetree, linux-kernel, linux-doc,
linux-arm-kernel, linux-mediatek, llvm
This series introduce a most awaited feature that is correctly
provide PCS with fwnode without having to use specific export symbol
and additional handling of PCS in phylink.
At times there were 2 different implementation (this and the one
from Sean) but Sean agreed that this can be picked and used in favor
of his implementation as long as his case with race condition is
correctly handled.
---
First the PCS fwnode:
The concept is to implement a producer-consumer API similar to other
subsystem like clock or PHY.
That seems to be the best solution to the problem as PCS driver needs
to be detached from phylink and implement a simple way to provide a
PCS while maintaining support for probe defer or driver removal.
To keep the implementation simple, the PCS driver devs needs some
collaboration to correctly implement this. This is O.K. as helper
to correctly implement this are provided hence it's really a matter
of following a pattern to correct follow removal of a PCS driver.
A PCS provider have to implement and call fwnode_pcs_add_provider() in
probe function and define an xlate function to define how the PCS
should be provided based on the requested interface and phandle spec
defined in fwnode (based on the #pcs-cells)
fwnode_pcs_get() is provided to provide a specific PCS declared in
fwnode at index.
A simple xlate function is provided for simple single PCS
implementation, fwnode_pcs_simple_get.
A PCS provider on driver removal should first call
fwnode_pcs_del_provider() to delete itself as a provider and then
release the PCS from phylink with phylink_release_pcs() under rtnl
lock.
---
Second PCS handling in phylink:
We have the PCS problem for the only reason that in initial
implementation, we permitted way too much flexibility to MAC driver
and things started to deviate. At times we couldn't think SoC
would start to put PCS outside the MAC hence it was OK to assume
they would live in the same driver. With the introduction of
10g in more consumer devices, we are observing a rapid growth
of this pattern with multiple PCS external to MAC.
To put a stop on this, the only solution is to give back to phylink
control on PCS handling and enforce more robust supported interface
definition from both MAC and PCS side.
It's suggested to read patch 0003 of this series for more info, here
a brief explaination of the idea:
This series introduce handling of PCS in phylink and try to deprecate
.mac_select_pcs.
Phylink now might contain a linked list of available PCS and
those will be used for PCS selection on phylink_major_config.
MAC driver needs to define pcs_interfaces mask in phylink_config
for every interface that needs a dedicated PCS.
These PCS needs to be provided to phylink at phylink_create time
by setting the .fill_available_pcs and .num_possible_pcs in phylink_config.
Helpers to parse PCS from fwnode are provided
fwnode_phylink_pcs_count() that will return the count of PCS entries
described in the firmware node and fwnode_phylink_pcs_parse() that will
fill a preallocated array of PCS pointer with the actual available PCS
(ignoring the one that still needs to be probed).
phylink_create() will fill the internal PCS list with the passed
array of PCS. phylink_major_config and other user of .mac_select_pcs
are adapted to make use of this new PCS list.
The supported interface value is also moved internally to phylink
struct. This is to handle late removal and addition of PCS.
(the bonus effect to this is giving phylink a clear idea of what
is actually supported by the MAC and his constraint with PCS)
The supported interface mask in phylink is done by OR the
supported_interfaces in phylink_config with every PCS in PCS list.
PCS removal is supported by forcing a mac_config, refresh the
supported interfaces and run a phy_resolve().
PCS late addition is supported by introducing a global notifier
for PCS provider. If a phylink have the pcs_interfaces mask not
zero, it's registered to this notifier.
PCS provider will emit a global PCS add event to signal any
interface that a new PCS might be available.
The function will then check if the PCS is related to the MAC
fwnode and add it accordingly.
A user for this new implementation is provided as an Airoha PCS
driver. This was also tested downstream with the IPQ95xx QCOM SoC
and with the help of Daniel also on the various Mediatek MT7988
SoC with both SFP cage implementation and DSA attached.
Lots of tests were done with driver unbind/bind and with interface
up/down also by adding print to make sure major_config_fail gets
correctly triggered and reset once the PCS comes back.
The dedicated commits have longer description on the implementation
so it's suggested to also check there for additional info.
It's worth to mention that OpenWrt is currently using this on
Mediatek SoC and QCOM ipq807x/ipq60xx/ipq50xx and Airoha are
already ported in staging tree for testing.
---
Changes v7:
- Address all the bug from the Sashiko bot
- Rename .num_available_pcs to .num_possible_pcs
- Link PCS in phylink_create()
- Correctly unregister the notifier on phylink_destroy()
- Introduce fwnode_phylink_pcs_count()
- Better handle locking in phylink for PCS handling
- Better handle unavailable PCS at phylink_create() time
- Improve Documentation file
- Other minor fixes to address suggestion from bot
- Rebase on top of net-next
Changes v6:
- Rebase on top of net-next
- Add Documentation files
- Add fw_devlink patch
- Fix some comments typo
- Rework the airoha_eth.c implementation with new multi serdes code
- Extend PCS code with PCIe and USB support
- Align schema to new property
Changes v5:
- Rebase on top of net-next
- Use the new force_major_config
- Reword some comments and commit description
- Return -ENODEV instead of -EPROBE_DEFER to perevent race condition
- Drop phy_interface_copy patch (Russell pushed an equivalent version)
Changes v4:
- Move patch 0002 phy_interface_copy to 0002 (fix bisectability
problem)
- Address review from Lorenzo for Airoha ethernet driver
- Fix kdoc error with missing Return (actually missing : before Return)
- Fix UNMET dependency reported error for CONFIG_FWNODE_PCS
- Revert to pcs.c instead of core.c (due to name conflict with other kmod)
- Fix clang compilation error for Airoha PCS driver
- Add missing inline function to pcs.h function
Changes v3:
- Out of RFC
- Fix various spelling mistake
- Drop circular dependency patch
- Complete Airoha Ethernet phylink integration
- Introduce .pcs_link_down PCS OP
Changes v2:
- Switch to fwnode
- Implement PCS provider notifier
- Better split changes
- Move supported_interfaces to phylink
- Add circular dependency patch
- Rework handling with indirect addition/removal and
trigger of phylink_resolve()
Christian Marangi (12):
net: phylink: keep and use MAC supported_interfaces in phylink struct
net: phylink: introduce internal phylink PCS handling
net: phylink: add phylink_release_pcs() to externally release a PCS
net: pcs: implement Firmware node support for PCS driver
net: phylink: support late PCS provider attach
net: Document PCS subsystem
MAINTAINERS: add myself as PCS subsystem maintainer
of: property: fw_devlink: Add support for "pcs-handle"
net: phylink: add .pcs_link_down PCS OP
dt-bindings: net: pcs: Document support for Airoha Ethernet PCS
net: pcs: airoha: add PCS driver for Airoha AN7581 SoC
net: airoha: add phylink support
.../bindings/net/pcs/airoha,pcs.yaml | 261 ++
Documentation/networking/index.rst | 1 +
Documentation/networking/pcs.rst | 229 ++
MAINTAINERS | 9 +
drivers/net/ethernet/airoha/Kconfig | 1 +
drivers/net/ethernet/airoha/airoha_eth.c | 161 +-
drivers/net/ethernet/airoha/airoha_eth.h | 3 +
drivers/net/ethernet/airoha/airoha_regs.h | 12 +
drivers/net/pcs/Kconfig | 8 +
drivers/net/pcs/Makefile | 3 +
drivers/net/pcs/airoha/Kconfig | 12 +
drivers/net/pcs/airoha/Makefile | 7 +
drivers/net/pcs/airoha/pcs-airoha-common.c | 1318 +++++++++++
drivers/net/pcs/airoha/pcs-airoha.h | 1309 +++++++++++
drivers/net/pcs/airoha/pcs-an7581.c | 2093 +++++++++++++++++
drivers/net/pcs/pcs.c | 257 ++
drivers/net/phy/phylink.c | 337 ++-
drivers/of/property.c | 2 +
include/linux/pcs/pcs-provider.h | 41 +
include/linux/pcs/pcs.h | 135 ++
include/linux/phylink.h | 20 +
21 files changed, 6191 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
create mode 100644 Documentation/networking/pcs.rst
create mode 100644 drivers/net/pcs/airoha/Kconfig
create mode 100644 drivers/net/pcs/airoha/Makefile
create mode 100644 drivers/net/pcs/airoha/pcs-airoha-common.c
create mode 100644 drivers/net/pcs/airoha/pcs-airoha.h
create mode 100644 drivers/net/pcs/airoha/pcs-an7581.c
create mode 100644 drivers/net/pcs/pcs.c
create mode 100644 include/linux/pcs/pcs-provider.h
create mode 100644 include/linux/pcs/pcs.h
--
2.53.0
^ permalink raw reply
* Re: [PATCH v3 2/2] clk: amlogic: Add A9 peripherals clock controller driver
From: Jerome Brunet @ 2026-06-15 12:29 UTC (permalink / raw)
To: Jian Hu
Cc: Jian Hu via B4 Relay, Neil Armstrong, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Xianwei Zhao, Kevin Hilman, Martin Blumenstingl, linux-amlogic,
linux-clk, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <bfe92bbe-5325-4497-b79f-10c7a6e1ed5b@amlogic.com>
On lun. 15 juin 2026 at 19:25, Jian Hu <jian.hu@amlogic.com> wrote:
> On 6/10/2026 8:49 PM, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On mer. 10 juin 2026 at 16:14, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel.org> wrote:
>>
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the peripherals clock controller driver for the Amlogic A9 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>> drivers/clk/meson/Kconfig | 15 +
>>> drivers/clk/meson/Makefile | 1 +
>>> drivers/clk/meson/a9-peripherals.c | 1925 ++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 1941 insertions(+)
>>>
>
> [ ... ]
>
>>> +
>>> +/* Channel 6 is unconnected. */
>>> +static u32 a9_glb_parents_val_table[] = { 0, 1, 2, 3, 4, 5, 7 };
>>> +static struct clk_regmap a9_dspa;
>> What is this ?
>
>
> The peripheral clock definitions are ordered by register offset.
>
> dspa is one of the parents of the glb clock, while the dsp clock registers
> are located after the GLB clock registers.
>
> Since glb references a9_dspa before its full definition appears, the
> declaration
>
> static struct clk_regmap a9_dspa;
>
> is added as a forward declaration to satisfy the compiler.
>
>
> Would it make sense to relax the register-offset ordering in this case?
>
I don't think we ever enforced such ordering (or any other ordering) in
the clock driver, so yes please.
> By defining the DSP clock before the GLB clock, we could remove the forward
> declaration of a9_dspa.
Unless it is absolutely necessary, please avoid forward declaration.
Declare what is needed first, keep related things together and use your
best judgement ... IOW, make it easy for me to review ;)
>
>>> +
>>> +static const struct clk_parent_data a9_glb_parents[] = {
>>> +};
[...]
>>> +
>>> +static struct clk_regmap a9_vclk_div2_en = {
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = VID_CLK_CTRL,
>>> + .bit_idx = 1,
>>> + },
>>> + .hw.init = CLK_HW_INIT_HW("vclk_div2_en", &a9_vclk.hw,
>>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>>> +};
>> Looks to me all this div_en / div repeating pattern would be easier to review
>> with tiny macro .
>
>
> Good point.
>
> I tried to reduce the repeated div_en/div pattern using a helper macro.
>
> It keeps the relationship between gate and fixed-factor clock more compact
> and easier to review.
>
> After using the helper macro, the div_en/div code can be simplified to the
> following:
>
> #define A9_VCLK(_name, _reg, _bit, _div, _parent) \
> struct clk_regmap a9_##_name##_en = { \
^- not strictly necessary, a touch too agressive
> .data = &(struct clk_regmap_gate_data){ \
> .offset = _reg, \
> .bit_idx = _bit, \
> }, \
> .hw.init = &(struct clk_init_data) { \
> .name = #_name "_en", \
> .ops = &clk_regmap_gate_ops, \
> .parent_hws = (const struct clk_hw *[]) { _parent }, \
> .num_parents = 1, \
> .flags = CLK_SET_RATE_PARENT, \
> }, \
> }; \
> \
> struct clk_fixed_factor a9_##_name = { \
> .mult = 1, \
> .div = _div, \
> .hw.init = &(struct clk_init_data){ \
> .name = #_name, \
> .ops = &clk_fixed_factor_ops, \
> .parent_hws = (const struct clk_hw *[]) { \
> &a9_##_name##_en.hw \
> }, \
> .num_parents = 1, \
> .flags = CLK_SET_RATE_PARENT, \
> }, \
> }; \
>
> static A9_VCLK(vclk_div2, VID_CLK_CTRL, 1, 2, &a9_vclk.hw);
> static A9_VCLK(vclk_div4, VID_CLK_CTRL, 2, 4, &a9_vclk.hw);
> static A9_VCLK(vclk_div6, VID_CLK_CTRL, 3, 6, &a9_vclk.hw);
> static A9_VCLK(vclk_div6, VID_CLK_CTRL, 4, 12, &a9_vclk.hw);
> static A9_VCLK(vclk2_div2, VIID_CLK_CTRL, 1, 2, &a9_vclk2.hw);
> static A9_VCLK(vclk2_div4, VIID_CLK_CTRL, 2, 4, &a9_vclk2.hw);
> static A9_VCLK(vclk2_div6, VIID_CLK_CTRL, 3, 6, &a9_vclk2.hw);
> static A9_VCLK(vclk2_div6, VIID_CLK_CTRL, 4, 12, &a9_vclk2.hw);
>
>
> If you think splitting it further into separate helper macros would improve
> readability.
One clock per macro please. Hidding 2 declaration is recipe for
disaster. For ex, here the first one is static, the 2nd is not
>
> I can do that as well.
>
^ permalink raw reply
* Re: [PATCH 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC
From: sashiko-bot @ 2026-06-15 12:27 UTC (permalink / raw)
To: Pinkesh Vaghela; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260615122016.1110206-3-pinkesh.vaghela@einfochips.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The fixed-clock node name 'oscillator' triggers a deprecated fallback in the fixed-clock schema.
--
commit cde88bbabc7fa6624be08081caf3200c1a962c33
Author: Pritesh Patel <pritesh.patel@einfochips.com>
riscv: dts: eswin: add clock generator for EIC7700 SoC
This commit adds a clock generator node for the EIC7700 SoC. It also adds a
fixed-clock node representing the 24MHz crystal oscillator on HiFive Premier
P550 boards.
> diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> index 430a210f01e66..a7ebb11159580 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
[ ... ]
> @@ -203,6 +204,11 @@ pmu {
> <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
> };
>
> + xtal: oscillator {
[Severity: Low]
Does this node name trigger a deprecation warning during dtbs_check?
The fixed-clock device tree binding schema dictates that the preferred node
name should match the pattern ^clock-([0-9]+|[a-z0-9-]+)$. Naming the node
oscillator falls into the deprecated fallback branch.
Should this be named something like clock-xtal or clock-24m instead to avoid
warnings?
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> };
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260615122016.1110206-1-pinkesh.vaghela@einfochips.com?part=2
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: phy: qcom,usb-hs-phy: add qcom,vendor-init-seq
From: me @ 2026-06-15 12:17 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, github.com, linux-phy, devicetree, linux-arm-msm,
Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
In-Reply-To: <tknuizddyhfcyywmm36v4ok6idgpxridgur5qbowvmwhcbve5o@bp3z46gsfvlk>
On 2026-06-12 02:25, Dmitry Baryshkov wrote:
> On Thu, Jun 11, 2026 at 12:39:45PM +0200, Konrad Dybcio wrote:
>> On 6/4/26 1:02 AM, Dmitry Baryshkov wrote:
>> > On Wed, Jun 03, 2026 at 06:09:18PM +0200, me@herrie.org wrote:
>> >> On 2026-06-03 15:57, Dmitry Baryshkov wrote:
>> >>> On Wed, Jun 03, 2026 at 07:48:08AM +0200, Herman van Hazendonk wrote:
>> >>>> Add an optional "qcom,vendor-init-seq" property carrying raw ULPI
>> >>>> (address, value) pairs that are written after PHY reset.
>> >>>>
>> >>>> Unlike the existing "qcom,init-seq" property, the address field is
>> >>>> NOT offset by ULPI_EXT_VENDOR_SPECIFIC, so the new property can
>> >>>> reach the standard ULPI vendor register range (0x30-0x3f). MSM8x60-
>> >>>> class hardware needs this range to programme pre-emphasis, HS driver
>> >>>> slope and CDR auto-reset bits the legacy msm_otg driver used to set
>> >>>> via platform data.
>> >>>
>> >>> Are those register writes specific to the device or to the whole
>> >>> platform? In the latter case please extend the driver to write them.
>> >>
>> >> Looking at every MSM8x60 reference kernel I could find (Qualcomm's own
>> >> msm8x60 board, HP TouchPad / APQ8060, and some HTC/Saumsung MSM8660
>> >> devices), the writes split into two groups:
>> >>
>> >> Platform-level (same across all MSM8x60 hardware):
>> >> - reg 0x36 bits 1+2: CDR auto-reset disabled, SE1 gating disabled
>> >> - reg 0x32 bits [5:4]: pre-emphasis at 20%
>> >>
>> >> Board-specific:
>> >> - reg 0x32 bits [3:0]: HS driver slope — HP TouchPad uses 5, HTC
>> >> devices use 1. This clearly depends on board layout (trace length,
>> >> connector loading, etc.).
>> >>
>> >> So the platform-level writes should move unconditionally into the driver
>> >> behind a match-data flag for the MSM8x60-class compatible, and only the
>> >> HS driver slope value belongs in DT.
>> >
>> > Looks like it. Please hardcode the value for your platform in the driver
>> > (with the comment), meanwhile we can try looking up the actual values.
>>
>> Do we have the values for a MTP/QRD (or whatever they used to be
>> called
>> back then..), like we would usually put in there?
>
> As far as I can understand msm-3.0 and msm-3.4 most of the boards were
> writing 0 here (although it might have been unexpected). None of the
> board files set the hsdrvslope value (which means 0).
>
> Please correct me if I'm wrong. I see that for tenderloin kernels
> change
> that to 0x5, but I can't find a sensible commit message.
>
> I could not find the documentation for vendor ULPI registers for those
> chips, so I don't think we can identify, how to make sense of those
> values. In such a case and having different board-specific values, we
> don't have a better option than having a qcom,hsdrvslope (or similarly
> named) property in DT.
Dmitry/Konrad,
The bit-level meaning *is* documented byte-for-byte across
every MSM8x60 downstream tree I could find: Code Aurora is the
canonical source:
arch/arm/mach-msm/include/mach/msm_hsusb_hw.h
#define ULPI_CONFIG_REG3 0x32
#define ULPI_DIGOUT_CTRL 0x36 /* on MSM7x30 /
MSM8x60 */
#define ULPI_CDR_AUTORESET (1 << 1)
#define ULPI_SE1_GATE (1 << 2)
#define ULPI_PRE_EMPHASIS_MASK (3 << 4)
#define ULPI_HSDRVSLOPE_MASK (0x0F)
reg 0x32 [5:4]: pre-emphasis level (00 disabled, 11 = 20%, 10 = 10%)
reg 0x32 [3:0]: HS driver slope
reg 0x36 bit 1: CDR auto-reset enable
reg 0x36 bit 2: SE1 gating enable
The legacy `msm72k_otg.c` semantics for the 0x36 bits are inverted:
setting the bit disables the function (see set_cdr_auto_reset() and
set_se1_gating()). Every MSM8x60 reference board sets both bits,
i.e. CDR auto-reset disabled + SE1 gating disabled.
Surveying every MSM8x60-class board file I can reach: Qualcomm's own
reference, Samsung, Sony, HTC, and HP: the platform-level values
are unanimous:
pre-emphasis = 20%
CDR auto-reset = disabled
SE1 gating = disabled
| Vendor / board | hsdrvslope |
| -----------------------------------------------|------------|
| Qualcomm reference (SURF / FFA / Fluid / | |
| Dragon / Fusion -- board-msm8x60.c) | unset (0) |
| Samsung Galaxy S2 family (Q1 / Celox / Dali / | |
| generic 8x60 MTP) | unset (0) |
| Sony MSM8660 (sony-kernel-msm8660) | unset (0) |
| HTC MSM8660 (shooter / holiday / pyramid / | |
| doubleshot / shooter_u / ruby) | 1 |
| HP TouchPad (board-tenderloin.c) | 5 |
So Qualcomm's own MTP, the closest thing to a reference platform we
have, leaves hsdrvslope at the silicon default (0). Two OEMs (HTC,
HP) override it to non-zero values that match their board layout.
Neither override has a commit message. HTC's value is buried in an
init_seq array, HP's appears as `.hsdrvslope = 0x05` in
board-tenderloin.c with no comment. I've kept TouchPad's 5 because
that's the value the device shipped with and our HS link is happy
with it; changing it risks regressing eye margin on the silicon we
still have to test against.
So the plan is exactly what you both already converged on:
1. Drop qcom,vendor-init-seq from the binding (this patch goes away
entirely).
2. In the driver, hardcode the three platform-level writes behind
the qcom,usb-hs-phy-msm8660 compatible match-data, with a
comment citing msm_hsusb_hw.h as the source for the bit names.
3. Add a single qcom,hs-drv-slope property (u8, 0..15) for the
board-varying value. TouchPad DT sets 5. Absent ⇒ leave silicon
default in place, matching Qualcomm/Samsung/Sony reference
behaviour.
I'll send the new v in that shape: single dt-bindings patch
(qcom,hs-drv-slope) plus the driver patch that hardcodes the platform
writes and consumes the new property.
Unless you have other suggestions?
Thanks,
Herman
^ permalink raw reply
* Re: [PATCH 2/2] spi: qcom-geni: Add property to force GSI mode
From: Dmitry Baryshkov @ 2026-06-15 12:23 UTC (permalink / raw)
To: Pengyu Luo
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andy Gross, Bjorn Andersson, linux-arm-msm, linux-spi, devicetree,
linux-kernel
In-Reply-To: <CAH2e8h5Swn2mWoz+t_nrSw1=hQttwi1Hx=dg=cd9S3QRnHjpSQ@mail.gmail.com>
On Mon, Jun 15, 2026 at 12:25:32PM +0800, Pengyu Luo wrote:
> On Mon, Jun 15, 2026 at 5:18 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
> >
> > On Sun, Jun 14, 2026 at 04:34:24PM +0800, Pengyu Luo wrote:
> > > Some devices (such as gaokun3) do not disable FIFO mode, causing the
> > > driver to fallback to FIFO mode by default. However, these platforms
> > > also support GSI mode, which is highly preferred for certain
> > > peripherals like SPI touchscreens to improve performance.
> > >
> > > Introduce the "qcom,force-gsi-mode" device property to hint and force
> > > the controller into GSI mode during initialization.
> >
> > Ideally, this should be decided by the SPI controller based on the
> > requirements. Another option would be to prefer GSI for all transfers if
> > it is available, ignoring the FIFO even if it is not disabled.
> >
>
> I have read reviews. Can we check if the compatible
> "qcom,sm6350-gpi-dma" is in DT? If the gpi dma controller is
> presented, then we enable GSI mode.
Can we just check for the dmas property? If it is present and if we
could get DMA channels, then GSI DMA is available.
>
> Best wishes,
> Pengyu
>
> > >
> > > Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> > > ---
> > > drivers/spi/spi-geni-qcom.c | 7 +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH 4/7] dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
Document ESWIN EIC7700 SoC compatible for syscon registers.
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index e22867088063..7d3365601249 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -62,6 +62,7 @@ select:
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
- econet,en751221-chip-scu
+ - eswin,eic7700-syscfg
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
@@ -175,6 +176,7 @@ properties:
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
- econet,en751221-chip-scu
+ - eswin,eic7700-syscfg
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
--
2.34.1
^ permalink raw reply related
* [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
From: Yulin Lu <luyulin@eswincomputing.com>
Add pinctrl node and related pin configuration for EIC7700 SoC
Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 5 +
3 files changed, 1002 insertions(+)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 1fb92f0e7c55..e7bb96e14958 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "eic7700.dtsi"
+#include "eic7700-pinctrl.dtsi"
/ {
compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
@@ -18,6 +19,15 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vcc_1v8: vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
&xtal {
@@ -25,6 +35,105 @@ &xtal {
clock-output-names = "xtal24m";
};
+&gpio0_pins {
+ bias-disable;
+ input-enable;
+};
+
+&gpio5_pins {
+ bias-disable;
+ input-enable;
+};
+
+&gpio11_pins {
+ bias-disable;
+ input-enable;
+};
+
+&gpio14_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio15_pins {
+ bias-disable;
+ input-enable;
+};
+
+&gpio28_pins {
+ bias-disable;
+ input-enable;
+};
+
+&gpio43_pins {
+ bias-disable;
+ input-disable;
+};
+
+&gpio71_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio74_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio76_pins {
+ bias-disable;
+ input-disable;
+};
+
+&gpio77_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio79_pins {
+ bias-disable;
+ input-disable;
+};
+
+&gpio80_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio82_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio84_pins {
+ bias-disable;
+ input-disable;
+};
+
+&gpio85_pins {
+ bias-pull-up;
+ input-disable;
+};
+
+&gpio94_pins {
+ bias-disable;
+ input-disable;
+};
+
+&gpio106_pins {
+ bias-disable;
+ input-disable;
+};
+
+&gpio111_pins {
+ bias-disable;
+ input-disable;
+};
+
+&pinctrl {
+ vrgmii-supply = <&vcc_1v8>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
new file mode 100644
index 000000000000..7293df146aa7
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -0,0 +1,888 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
+ *
+ * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+&pinctrl{
+ default-pins-grp {
+ sata_act_led_pins: sata-act-led-pins{
+ pins = "gpio27";
+ function = "sata";
+ };
+
+ emmc_led_ctrl_pins: emmc-led-ctrl-pins {
+ pins = "gpio29";
+ function = "emmc";
+ };
+
+ sd0_led_ctrl_pins: sd0-led-ctrl-pins {
+ pins = "gpio34";
+ function = "sdio";
+ };
+
+ sd1_led_ctrl_pins: sd1-led-ctrl-pins {
+ pins = "spi1_d2";
+ function = "sdio";
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins = "uart1_cts", "uart1_rts";
+ function = "i2c";
+ };
+
+ i2c7_pins: i2c7-pins {
+ pins = "uart2_tx", "uart2_rx";
+ function = "i2c";
+ };
+
+ i2c9_pins: i2c9-pins {
+ pins = "spi1_d0", "spi1_d1";
+ function = "i2c";
+ };
+
+ pwm1_pins: pwm1-pins {
+ pins = "spi1_d3";
+ function = "pwm";
+ };
+
+ pwm2_pins: pwm2-pins {
+ pins = "spi1_cs1_n";
+ function = "pwm";
+ };
+
+ mipi_csi_xtrig0_pins: mipi-csi-xtrig0-pins {
+ pins = "gpio92";
+ function = "mipi_csi";
+ };
+
+ mipi_csi_xtrig1_pins: mipi-csi-xtrig1-pins {
+ pins = "gpio93";
+ function = "mipi_csi";
+ };
+
+ dual_spi2_pins: dual-spi2-pins {
+ pins = "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi";
+ function = "spi";
+ };
+
+ quad_spi2_pins: quad-spi2-pins {
+ pins = "spi2_cs0_n", "spi2_cs1_n", "jtag0_tck", "jtag0_tms",
+ "jtag0_tdi", "jtag0_tdo", "gpio5";
+ function = "spi";
+ };
+
+ gpio1_pins: gpio1-pins {
+ pins = "jtag0_tck";
+ function = "gpio";
+ };
+
+ gpio2_pins: gpio2-pins {
+ pins = "jtag0_tms";
+ function = "gpio";
+ };
+
+ gpio3_pins: gpio3-pins {
+ pins = "jtag0_tdi";
+ function = "gpio";
+ };
+
+ gpio4_pins: gpio4-pins {
+ pins = "jtag0_tdo";
+ function = "gpio";
+ };
+
+ gpio6_pins: gpio6-pins {
+ pins = "spi2_cs0_n";
+ function = "gpio";
+ };
+
+ gpio7_pins: gpio7-pins {
+ pins = "jtag1_tck";
+ function = "gpio";
+ };
+
+ gpio8_pins: gpio8-pins {
+ pins = "jtag1_tms";
+ function = "gpio";
+ };
+
+ gpio9_pins: gpio9-pins {
+ pins = "jtag1_tdi";
+ function = "gpio";
+ };
+
+ gpio10_pins: gpio10-pins {
+ pins = "jtag1_tdo";
+ function = "gpio";
+ };
+
+ gpio12_pins: gpio12-pins {
+ pins = "spi2_cs1_n";
+ function = "gpio";
+ };
+
+ gpio13_pins: gpio13-pins {
+ pins = "mode_set0";
+ function = "gpio";
+ };
+
+ gpio14_pins: gpio14-pins {
+ pins = "mode_set1";
+ function = "gpio";
+ };
+
+ gpio15_pins: gpio15-pins {
+ pins = "mode_set2";
+ function = "gpio";
+ };
+
+ gpio16_pins: gpio16-pins {
+ pins = "mode_set3";
+ function = "gpio";
+ };
+
+ gpio17_pins: gpio17-pins {
+ pins = "jtag2_trst";
+ function = "gpio";
+ };
+
+ gpio18_pins: gpio18-pins {
+ pins = "i2s0_bclk";
+ function = "gpio";
+ };
+
+ gpio19_pins: gpio19-pins {
+ pins = "i2s0_wclk";
+ function = "gpio";
+ };
+
+ gpio20_pins: gpio20-pins {
+ pins = "i2s0_sdi";
+ function = "gpio";
+ };
+
+ gpio21_pins: gpio21-pins {
+ pins = "i2s0_sdo";
+ function = "gpio";
+ };
+
+ gpio22_pins: gpio22-pins {
+ pins = "i2s_mclk";
+ function = "gpio";
+ };
+
+ gpio23_pins: gpio23-pins {
+ pins = "i2s2_bclk";
+ function = "gpio";
+ };
+
+ gpio24_pins: gpio24-pins {
+ pins = "i2s2_wclk";
+ function = "gpio";
+ };
+
+ gpio25_pins: gpio25-pins {
+ pins = "i2s2_sdi";
+ function = "gpio";
+ };
+
+ gpio26_pins: gpio26-pins {
+ pins = "i2s2_sdo";
+ function = "gpio";
+ };
+
+ gpio29_pins: gpio29-pins {
+ pins = "gpio29";
+ function = "gpio";
+ };
+
+ gpio30_pins: gpio30-pins {
+ pins = "i2s1_bclk";
+ function = "gpio";
+ };
+
+ gpio31_pins: gpio31-pins {
+ pins = "i2s1_wclk";
+ function = "gpio";
+ };
+
+ gpio32_pins: gpio32-pins {
+ pins = "i2s1_sdi";
+ function = "gpio";
+ };
+
+ gpio33_pins: gpio33-pins {
+ pins = "i2s1_sdo";
+ function = "gpio";
+ };
+
+ gpio34_pins: gpio34-pins {
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ gpio35_pins: gpio35-pins {
+ pins = "spi1_cs0_n";
+ function = "gpio";
+ };
+
+ gpio36_pins: gpio36-pins {
+ pins = "spi1_clk";
+ function = "gpio";
+ };
+
+ gpio37_pins: gpio37-pins {
+ pins = "spi1_d0";
+ function = "gpio";
+ };
+
+ gpio38_pins: gpio38-pins {
+ pins = "spi1_d1";
+ function = "gpio";
+ };
+
+ gpio39_pins: gpio39-pins {
+ pins = "spi1_d2";
+ function = "gpio";
+ };
+
+ gpio40_pins: gpio40-pins {
+ pins = "spi1_d3";
+ function = "gpio";
+ };
+
+ gpio41_pins: gpio41-pins {
+ pins = "spi1_cs1_n";
+ function = "gpio";
+ };
+
+ gpio42_pins: gpio42-pins {
+ pins = "usb0_pwren";
+ function = "gpio";
+ };
+
+ gpio43_pins: gpio43-pins {
+ pins = "usb1_pwren";
+ function = "gpio";
+ };
+
+ gpio44_pins: gpio44-pins {
+ pins = "i2c0_scl";
+ function = "gpio";
+ };
+
+ gpio45_pins: gpio45-pins {
+ pins = "i2c0_sda";
+ function = "gpio";
+ };
+
+ gpio46_pins: gpio46-pins {
+ pins = "i2c1_scl";
+ function = "gpio";
+ };
+
+ gpio47_pins: gpio47-pins {
+ pins = "i2c1_sda";
+ function = "gpio";
+ };
+
+ gpio48_pins: gpio48-pins {
+ pins = "i2c2_scl";
+ function = "gpio";
+ };
+
+ gpio49_pins: gpio49-pins {
+ pins = "i2c2_sda";
+ function = "gpio";
+ };
+
+ gpio50_pins: gpio50-pins {
+ pins = "i2c3_scl";
+ function = "gpio";
+ };
+
+ gpio51_pins: gpio51-pins {
+ pins = "i2c3_sda";
+ function = "gpio";
+ };
+
+ gpio52_pins: gpio52-pins {
+ pins = "i2c4_scl";
+ function = "gpio";
+ };
+
+ gpio53_pins: gpio53-pins {
+ pins = "i2c4_sda";
+ function = "gpio";
+ };
+
+ gpio54_pins: gpio54-pins {
+ pins = "i2c5_scl";
+ function = "gpio";
+ };
+
+ gpio55_pins: gpio55-pins {
+ pins = "i2c5_sda";
+ function = "gpio";
+ };
+
+ gpio56_pins: gpio56-pins {
+ pins = "uart0_tx";
+ function = "gpio";
+ };
+
+ gpio57_pins: gpio57-pins {
+ pins = "uart0_rx";
+ function = "gpio";
+ };
+
+ gpio58_pins: gpio58-pins {
+ pins = "uart1_tx";
+ function = "gpio";
+ };
+
+ gpio59_pins: gpio59-pins {
+ pins = "uart1_rx";
+ function = "gpio";
+ };
+
+ gpio60_pins: gpio60-pins {
+ pins = "uart1_cts";
+ function = "gpio";
+ };
+
+ gpio61_pins: gpio61-pins {
+ pins = "uart1_rts";
+ function = "gpio";
+ };
+
+ gpio62_pins: gpio62-pins {
+ pins = "uart2_tx";
+ function = "gpio";
+ };
+
+ gpio63_pins: gpio63-pins {
+ pins = "uart2_rx";
+ function = "gpio";
+ };
+
+ gpio64_pins: gpio64-pins {
+ pins = "jtag2_tck";
+ function = "gpio";
+ };
+
+ gpio65_pins: gpio65-pins {
+ pins = "jtag2_tms";
+ function = "gpio";
+ };
+
+ gpio66_pins: gpio66-pins {
+ pins = "jtag2_tdi";
+ function = "gpio";
+ };
+
+ gpio67_pins: gpio67-pins {
+ pins = "jtag2_tdo";
+ function = "gpio";
+ };
+
+ gpio68_pins: gpio68-pins {
+ pins = "fan_pwm";
+ function = "gpio";
+ };
+
+ gpio69_pins: gpio69-pins {
+ pins = "fan_tach";
+ function = "gpio";
+ };
+
+ gpio70_pins: gpio70-pins {
+ pins = "mipi_csi0_xvs";
+ function = "gpio";
+ };
+
+ gpio71_pins: gpio71-pins {
+ pins = "mipi_csi0_xhs";
+ function = "gpio";
+ };
+
+ gpio72_pins: gpio72-pins {
+ pins = "mipi_csi0_mclk";
+ function = "gpio";
+ };
+
+ gpio73_pins: gpio73-pins {
+ pins = "mipi_csi1_xvs";
+ function = "gpio";
+ };
+
+ gpio74_pins: gpio74-pins {
+ pins = "mipi_csi1_xhs";
+ function = "gpio";
+ };
+
+ gpio75_pins: gpio75-pins {
+ pins = "mipi_csi1_mclk";
+ function = "gpio";
+ };
+
+ gpio76_pins: gpio76-pins {
+ pins = "mipi_csi2_xvs";
+ function = "gpio";
+ };
+
+ gpio77_pins: gpio77-pins {
+ pins = "mipi_csi2_xhs";
+ function = "gpio";
+ };
+
+ gpio78_pins: gpio78-pins {
+ pins = "mipi_csi2_mclk";
+ function = "gpio";
+ };
+
+ gpio79_pins: gpio79-pins {
+ pins = "mipi_csi3_xvs";
+ function = "gpio";
+ };
+
+ gpio80_pins: gpio80-pins {
+ pins = "mipi_csi3_xhs";
+ function = "gpio";
+ };
+
+ gpio81_pins: gpio81-pins {
+ pins = "mipi_csi3_mclk";
+ function = "gpio";
+ };
+
+ gpio82_pins: gpio82-pins {
+ pins = "mipi_csi4_xvs";
+ function = "gpio";
+ };
+
+ gpio83_pins: gpio83-pins {
+ pins = "mipi_csi4_xhs";
+ function = "gpio";
+ };
+
+ gpio84_pins: gpio84-pins {
+ pins = "mipi_csi4_mclk";
+ function = "gpio";
+ };
+
+ gpio85_pins: gpio85-pins {
+ pins = "mipi_csi5_xvs";
+ function = "gpio";
+ };
+
+ gpio86_pins: gpio86-pins {
+ pins = "mipi_csi5_xhs";
+ function = "gpio";
+ };
+
+ gpio87_pins: gpio87-pins {
+ pins = "mipi_csi5_mclk";
+ function = "gpio";
+ };
+
+ gpio88_pins: gpio88-pins {
+ pins = "spi3_cs_n";
+ function = "gpio";
+ };
+
+ gpio89_pins: gpio89-pins {
+ pins = "spi3_clk";
+ function = "gpio";
+ };
+
+ gpio90_pins: gpio90-pins {
+ pins = "spi3_di";
+ function = "gpio";
+ };
+
+ gpio91_pins: gpio91-pins {
+ pins = "spi3_do";
+ function = "gpio";
+ };
+
+ gpio92_pins: gpio92-pins {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ gpio93_pins: gpio93-pins {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ gpio94_pins: gpio94-pins {
+ pins = "s_mode";
+ function = "gpio";
+ };
+
+ gpio95_pins: gpio95-pins {
+ pins = "gpio95";
+ function = "gpio";
+ };
+
+ gpio96_pins: gpio96-pins {
+ pins = "spi0_cs_n";
+ function = "gpio";
+ };
+
+ gpio97_pins: gpio97-pins {
+ pins = "spi0_clk";
+ function = "gpio";
+ };
+
+ gpio98_pins: gpio98-pins {
+ pins = "spi0_d0";
+ function = "gpio";
+ };
+
+ gpio99_pins: gpio99-pins {
+ pins = "spi0_d1";
+ function = "gpio";
+ };
+
+ gpio100_pins: gpio100-pins {
+ pins = "spi0_d2";
+ function = "gpio";
+ };
+
+ gpio101_pins: gpio101-pins {
+ pins = "spi0_d3";
+ function = "gpio";
+ };
+
+ gpio102_pins: gpio102-pins {
+ pins = "i2c10_scl";
+ function = "gpio";
+ };
+
+ gpio103_pins: gpio103-pins {
+ pins = "i2c10_sda";
+ function = "gpio";
+ };
+
+ gpio104_pins: gpio104-pins {
+ pins = "i2c11_scl";
+ function = "gpio";
+ };
+
+ gpio105_pins: gpio105-pins {
+ pins = "i2c11_sda";
+ function = "gpio";
+ };
+
+ gpio107_pins: gpio107-pins {
+ pins = "boot_sel0";
+ function = "gpio";
+ };
+
+ gpio108_pins: gpio108-pins {
+ pins = "boot_sel1";
+ function = "gpio";
+ };
+
+ gpio109_pins: gpio109-pins {
+ pins = "boot_sel2";
+ function = "gpio";
+ };
+
+ gpio110_pins: gpio110-pins {
+ pins = "boot_sel3";
+ function = "gpio";
+ };
+
+ uart3_pins: uart3-pins {
+ pins = "gpio92", "gpio93";
+ function = "uart";
+ };
+
+ uart4_pins: uart4-pins {
+ pins = "spi1_d0", "spi1_d1";
+ function = "uart";
+ };
+
+ gpio0_pins: gpio0-pins {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ gpio5_pins: gpio5-pins {
+ pins = "gpio5";
+ function = "gpio";
+ };
+
+ gpio11_pins: gpio11-pins {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ gpio27_pins: gpio27-pins {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ gpio28_pins: gpio28-pins {
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ gpio106_pins: gpio106-pins {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ gpio111_pins: gpio111-pins {
+ pins = "gpio111";
+ function = "gpio";
+ };
+
+ chip_mode_pins: chip-mode-pins {
+ pins = "chip_mode";
+ function = "chip_mode";
+ };
+
+ sdio0_pins: sdio0-pins {
+ pins = "mode_set0", "mode_set1";
+ function = "sdio";
+ };
+
+ sdio1_pins: sdio1-pins {
+ pins = "mode_set2", "mode_set3";
+ function = "sdio";
+ };
+
+ jtag0_pins: jtag0-pins {
+ pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
+ function = "jtag";
+ };
+
+ jtag1_pins: jtag1-pins {
+ pins = "jtag1_tck", "jtag1_tms", "jtag1_tdi", "jtag1_tdo";
+ function = "jtag";
+ };
+
+ jtag2_pins: jtag2-pins {
+ pins = "jtag2_trst", "jtag2_tck", "jtag2_tms", "jtag2_tdi",
+ "jtag2_tdo";
+ function = "jtag";
+ };
+
+ pcie_pins: pcie-pins {
+ pins = "pcie_clkreq_n", "pcie_wake_n", "pcie_perst_n";
+ function = "pcie";
+ };
+
+ hdmi_pins: hdmi-pins {
+ pins = "hdmi_scl", "hdmi_sda", "hdmi_cec";
+ function = "hdmi";
+ };
+
+ rgmii0_pins: rgmii0-pins {
+ pins = "rgmii0_clk_125", "rgmii0_txen", "rgmii0_txclk", "rgmii0_txd0",
+ "rgmii0_txd1", "rgmii0_txd2", "rgmii0_txd3", "rgmii0_rxclk",
+ "rgmii0_rxdv", "rgmii0_rxd0", "rgmii0_rxd1", "rgmii0_rxd2",
+ "rgmii0_rxd3", "rgmii0_mdc", "rgmii0_mdio", "rgmii0_intb";
+ function = "hdmi";
+ };
+
+ rgmii1_pins: rgmii1-pins {
+ pins = "rgmii1_clk_125", "rgmii1_txen", "rgmii1_txclk", "rgmii1_txd0",
+ "rgmii1_txd1", "rgmii1_txd2", "rgmii1_txd3", "rgmii1_rxclk",
+ "rgmii1_rxdv", "rgmii1_rxd0", "rgmii1_rxd1", "rgmii1_rxd2",
+ "rgmii1_rxd3", "rgmii1_mdc", "rgmii1_mdio", "rgmii1_intb";
+ function = "hdmi";
+ };
+
+ i2s0_pins: i2s0-pins {
+ pins = "i2s0_bclk", "i2s0_wclk", "i2s0_sdi", "i2s0_sdo", "i2s_mclk";
+ function = "hdmi";
+ };
+
+ i2s1_pins: i2s1-pins {
+ pins = "i2s1_bclk", "i2s1_wclk", "i2s1_sdi", "i2s1_sdo", "i2s_mclk";
+ function = "hdmi";
+ };
+
+ i2s2_pins: i2s2-pins {
+ pins = "i2s2_bclk", "i2s2_wclk", "i2s2_sdi", "i2s2_sdo", "i2s_mclk";
+ function = "hdmi";
+ };
+
+ usb0_pwren_pins: usb0-pwren-pins {
+ pins = "usb0_pwren";
+ function = "usb";
+ };
+
+ usb1_pwren_pins: usb1-pwren-pins {
+ pins = "usb1_pwren";
+ function = "usb";
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins = "i2c0_scl", "i2c0_sda";
+ function = "i2c";
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins = "i2c1_scl", "i2c1_sda";
+ function = "i2c";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "i2c2_scl", "i2c2_sda";
+ function = "i2c";
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins = "i2c3_scl", "i2c3_sda";
+ function = "i2c";
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins = "i2c4_scl", "i2c4_sda";
+ function = "i2c";
+ };
+
+ i2c5_pins: i2c5-pins {
+ pins = "i2c5_scl", "i2c5_sda";
+ function = "i2c";
+ };
+
+ i2c8_pins: i2c8-pins {
+ pins = "gpio92", "gpio93";
+ function = "i2c";
+ };
+
+ i2c10_pins: i2c10-pins {
+ pins = "i2c10_scl", "i2c10_sda";
+ function = "i2c";
+ };
+
+ i2c11_pins: i2c11-pins {
+ pins = "i2c11_scl", "i2c11_sda";
+ function = "i2c";
+ };
+
+ uart0_pins: uart0-pins {
+ pins = "uart0_tx", "uart0_rx";
+ function = "uart";
+ };
+
+ uart1_pins: uart1-pins {
+ pins = "uart1_tx", "uart1_rx", "uart1_cts", "uart1_rts";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "uart2_tx", "uart2_rx";
+ function = "uart";
+ };
+
+ fan_pwm_pins: fan-pwm-pins {
+ pins = "fan_pwm";
+ function = "pwm";
+ };
+
+ fan_tach_pins: fan-tach-pins {
+ pins = "fan_tach";
+ function = "fan_tach";
+ };
+
+ mipi_csi0_pins: mipi-csi0-pins {
+ pins = "mipi_csi0_xvs", "mipi_csi0_xhs", "mipi_csi0_mclk";
+ function = "mipi_csi";
+ };
+
+ mipi_csi1_pins: mipi-csi1-pins {
+ pins = "mipi_csi1_xvs", "mipi_csi1_xhs", "mipi_csi1_mclk";
+ function = "mipi_csi";
+ };
+
+ mipi_csi2_pins: mipi-csi2-pins {
+ pins = "mipi_csi2_xvs", "mipi_csi2_xhs", "mipi_csi2_mclk";
+ function = "mipi_csi";
+ };
+
+ mipi_csi3_pins: mipi-csi3-pins {
+ pins = "mipi_csi3_xvs", "mipi_csi3_xhs", "mipi_csi3_mclk";
+ function = "mipi_csi";
+ };
+
+ mipi_csi4_pins: mipi-csi4-pins {
+ pins = "mipi_csi4_xvs", "mipi_csi4_xhs", "mipi_csi4_mclk";
+ function = "mipi_csi";
+ };
+
+ mipi_csi5_pins: mipi-csi5-pins {
+ pins = "mipi_csi5_xvs", "mipi_csi5_xhs", "mipi_csi5_mclk";
+ function = "mipi_csi";
+ };
+
+ s_mode_pins: s-mode-pins {
+ pins = "s_mode";
+ function = "s_mode";
+ };
+
+ boot_sel0_pins: boot-sel0-pins {
+ pins = "boot_sel0";
+ function = "boot_sel";
+ };
+
+ boot_sel1_pins: boot-sel1-pins {
+ pins = "boot_sel1";
+ function = "boot_sel";
+ };
+
+ boot_sel2_pins: boot-sel2-pins {
+ pins = "boot_sel2";
+ function = "boot_sel";
+ };
+
+ boot_sel3_pins: boot-sel3-pins {
+ pins = "boot_sel3";
+ function = "boot_sel";
+ };
+
+ ddr_ref_clk_sel_pins: ddr-ref-clk-sel-pins {
+ pins = "gpio95";
+ function = "ddr_ref_clk_sel";
+ };
+
+ lpddr_ref_clk_pins: lpddr-ref-clk-pins {
+ pins = "lpddr_ref_clk";
+ function = "lpddr_ref_clk";
+ };
+
+ spi0_pins: spi0-pins {
+ pins = "spi0_cs_n", "spi0_clk", "spi0_d0", "spi0_d1", "spi0_d2",
+ "spi0_d3";
+ function = "spi";
+ };
+
+ dual_spi1_pins: dual-spi1-pins {
+ pins = "spi1_cs0_n", "spi1_clk", "spi1_d0", "spi1_d1";
+ function = "spi";
+ };
+
+ quad_spi1_pins: quad-spi1-pins {
+ pins = "spi1_cs0_n", "spi1_cs1_n", "spi1_clk", "spi1_d0", "spi1_d1",
+ "spi1_d2", "spi1_d3";
+ function = "spi";
+ };
+
+ spi3_pins: spi3-pins {
+ pins = "spi3_cs_n", "spi3_clk", "spi3_di", "spi3_do";
+ function = "spi";
+ };
+ };
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index a7ebb1115958..8798c50f7584 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -349,6 +349,11 @@ gpioD: gpio-port@3 {
};
};
+ pinctrl: pinctrl@51600080 {
+ compatible = "eswin,eic7700-pinctrl";
+ reg = <0x0 0x51600080 0x0 0x1fff80>;
+ };
+
clk: clock-controller@51828000 {
compatible = "eswin,eic7700-clock";
reg = <0x0 0x51828000 0x0 0x300>;
--
2.34.1
^ permalink raw reply related
* [PATCH 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add clock generator node for EIC7700 SoC.
HiFive Premier P550 boards have 24MHz crystal oscillator to provide
the input clock.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../boot/dts/eswin/eic7700-hifive-premier-p550.dts | 5 +++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..1fb92f0e7c55 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -20,6 +20,11 @@ chosen {
};
};
+&xtal {
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal24m";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 430a210f01e6..a7ebb1115958 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/eswin,eic7700-clock.h>
#include <dt-bindings/reset/eswin,eic7700-reset.h>
/ {
@@ -203,6 +204,11 @@ pmu {
<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
};
+ xtal: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges;
@@ -343,6 +349,13 @@ gpioD: gpio-port@3 {
};
};
+ clk: clock-controller@51828000 {
+ compatible = "eswin,eic7700-clock";
+ reg = <0x0 0x51828000 0x0 0x300>;
+ clocks = <&xtal>;
+ #clock-cells = <1>;
+ };
+
reset: reset-controller@51828300 {
compatible = "eswin,eic7700-reset";
reg = <0x0 0x51828300 0x0 0x200>;
--
2.34.1
^ permalink raw reply related
* [PATCH 1/7] riscv: dts: eswin: add reset generator for EIC7700 SoC
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add reset generator node for EIC7700 SoC
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..430a210f01e6 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/reset/eswin,eic7700-reset.h>
/ {
#address-cells = <2>;
@@ -341,5 +342,11 @@ gpioD: gpio-port@3 {
#gpio-cells = <2>;
};
};
+
+ reset: reset-controller@51828300 {
+ compatible = "eswin,eic7700-reset";
+ reg = <0x0 0x51828300 0x0 0x200>;
+ #reset-cells = <1>;
+ };
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH 0/7] riscv: eswin: eic7700: Add support for clocks, resets, pinctrl, HSP power domain, I2C and watchdog
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
This series extends the ESWIN's EIC7700 SoC support beyond the
already upstreamed basic DTS and DTSI files. It introduces DT nodes
for reset, clock, pinctrl, HSP power domain, I2C and Watchdog.
As support for boot media is yet to be upstreamed, we have
boot-tested this series with initramfs on HiFive Premier P550 board
using Linux 7.1, U-Boot 2024.01 and OpenSBI 1.8.1.
[1]: https://lore.kernel.org/lkml/20251113014656.2605447-1-samuel.holland@sifive.com/
Pinkesh Vaghela (2):
dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible
riscv: dts: eswin: add hsp power domain
Pritesh Patel (4):
riscv: dts: eswin: add reset generator for EIC7700 SoC
riscv: dts: eswin: add clock generator for EIC7700 SoC
riscv: dts: eswin: add I2C controller support
riscv: dts: eswin: add watchdog support
Yulin Lu (1):
riscv: dts: eswin: eic7700: add pinctrl support
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../dts/eswin/eic7700-hifive-premier-p550.dts | 182 ++++
.../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 234 +++++
4 files changed, 1306 insertions(+)
create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
--
2.34.1
^ permalink raw reply
* Re: [PATCH v6 1/3] arm64: dts: sophgo: add initial Milk-V Duo S board support
From: sashiko-bot @ 2026-06-15 12:20 UTC (permalink / raw)
To: Joshua Milas; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260615120324.1527881-2-josh.milas@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `no-1-8-v` property in the `&emmc` node artificially restricts eMMC performance, contradicting the 1.8V pinctrl pad configuration.
--
commit 16f792133b8071df278eace7bc1ca7b6e4b52d31
Author: Joshua Milas <josh.milas@gmail.com>
arm64: dts: sophgo: add initial Milk-V Duo S board support
Adds initial arm64 support for the Milk-V Duo S board making it possible
to boot Linux to the command line.
Link: https://milkv.io/duo-s [1]
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts
> new file mode 100644
> index 0000000000000..f56bfddeacc40
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts
[ ... ]
> + emmc_cfg: emmc-cfg {
> + emmc-rstn-pins {
> + pinmux = <PINMUX(PIN_EMMC_RSTN, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <10800>;
> + power-source = <1800>;
> + };
> +
> + emmc-clk-pins {
> + pinmux = <PINMUX(PIN_EMMC_CLK, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <10800>;
> + power-source = <1800>;
> + };
[ ... ]
> +&emmc {
> + bus-width = <4>;
> + no-1-8-v;
[Severity: Medium]
The emmc node specifies no-1-8-v, but the emmc_cfg pinctrl configures the
eMMC pins for 1.8V logic using power-source = <1800>. Is the board
physically wired to operate the eMMC at 1.8V?
If the hardware supports 1.8V, is it possible that setting no-1-8-v
artificially restricts the eMMC from utilizing high-speed capabilities
like HS200 and HS400?
> + cap-mmc-hw-reset;
> + no-sd;
> + no-sdio;
> + non-removable;
> + pinctrl-0 = <&emmc_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260615120324.1527881-1-josh.milas@gmail.com?part=1
^ permalink raw reply
* [PATCH 7/7] riscv: dts: eswin: add watchdog support
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add watchdog node for ESWIN EIC7700 SoC and enable them for HiFive
Premier P550 board
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 16 ++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 40 +++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 0f0c98474c62..a188a5e1d526 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -193,3 +193,19 @@ &uart0 {
&uart2 {
status = "okay";
};
+
+&wdt0 {
+ status = "okay";
+};
+
+&wdt1 {
+ status = "okay";
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&wdt3 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 28706431b2c0..a59a9932be0b 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -265,6 +265,46 @@ hsp_sp_csr: hsp-sp-top-csr@50440000 {
};
};
+ wdt0: watchdog@50800000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50800000 0x0 0x4000>;
+ interrupts = <87>;
+ clocks =<&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT0>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@50804000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50804000 0x0 0x4000>;
+ interrupts = <88>;
+ clocks =<&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT1>;
+ status = "disabled";
+ };
+
+ wdt2: watchdog@50808000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x50808000 0x0 0x4000>;
+ interrupts = <89>;
+ clocks =<&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT2>;
+ status = "disabled";
+ };
+
+ wdt3: watchdog@5080c000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x5080c000 0x0 0x4000>;
+ interrupts = <90>;
+ clocks =<&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
+ clock-names = "tclk";
+ resets = <&reset EIC7700_RESET_WDT3>;
+ status = "disabled";
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related
* [PATCH 6/7] riscv: dts: eswin: add I2C controller support
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
From: Pritesh Patel <pritesh.patel@einfochips.com>
Add I2C nodes for EIC7700 SoC.
Also add nodes for corresponding slave devices in dts file and
enable them for HiFive Premier P550 board
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 52 ++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 156 ++++++++++++++++++
2 files changed, 208 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index e7bb96e14958..0f0c98474c62 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -130,6 +130,58 @@ &gpio111_pins {
input-disable;
};
+&aon_i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+};
+
+&aon_i2c1 {
+ status = "okay";
+
+ pac1934@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <0x1>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_SOM";
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_SOC";
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_CPU";
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ shunt-resistor-micro-ohms = <1000>;
+ label = "VDD_LPDDR";
+ };
+ };
+
+ ina226@44 {
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ #io-channel-cells = <1>;
+ label = "sys_power";
+ shunt-resistor = <1000>;
+ };
+};
+
&pinctrl {
vrgmii-supply = <&vcc_1v8>;
};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index f8caf39616b2..28706431b2c0 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -315,6 +315,162 @@ uart4: serial@50940000 {
status = "disabled";
};
+ i2c0: i2c@50950000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x50950000 0x0 0x8000>;
+ interrupts = <105>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C0_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@50960000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x50960000 0x0 0x8000>;
+ interrupts = <106>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C1_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@50970000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x50970000 0x0 0x8000>;
+ interrupts = <107>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C2_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@50980000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x50980000 0x0 0x8000>;
+ interrupts = <108>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C3_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@50990000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x50990000 0x0 0x8000>;
+ interrupts = <109>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C4_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@509a0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x509a0000 0x0 0x8000>;
+ interrupts = <110>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C5_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@509b0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x509b0000 0x0 0x8000>;
+ interrupts = <111>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C6_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@509c0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x509c0000 0x0 0x8000>;
+ interrupts = <112>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C7_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@509d0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x509d0000 0x0 0x8000>;
+ interrupts = <113>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C8_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@509e0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x509e0000 0x0 0x8000>;
+ interrupts = <114>;
+ clocks = <&clk EIC7700_CLK_GATE_LSP_I2C9_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_I2C9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ aon_i2c0: i2c@51830000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x51830000 0x0 0x8000>;
+ interrupts = <290>;
+ clocks = <&clk EIC7700_CLK_GATE_AON_I2C0_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_ANO0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ aon_i2c1: i2c@51838000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x51838000 0x0 0x8000>;
+ interrupts = <291>;
+ clocks = <&clk EIC7700_CLK_GATE_AON_I2C1_PCLK>;
+ clock-names = "ref";
+ clock-frequency = <100000>;
+ resets = <&reset EIC7700_RESET_ANO1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gpio@51600000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x51600000 0x0 0x80>;
--
2.34.1
^ permalink raw reply related
* [PATCH 5/7] riscv: dts: eswin: add hsp power domain
From: Pinkesh Vaghela @ 2026-06-15 12:20 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
devicetree, linux-kernel, linux-riscv, Min Lin
Cc: Yulin Lu, Samuel Holland, Darshan Prajapati, Pinkesh Vaghela,
Pritesh Patel
In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com>
HSP CSR is inside the HSP power domain. HSP CFG clock must be enabled
to access the HSP CSR registers.
Add HSP power domain node to manage hsp cfg clock
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 8798c50f7584..f8caf39616b2 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
};
+ hsp_power_domain: bus@50400000 {
+ compatible = "simple-pm-bus";
+ ranges = <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>;
+ clocks = <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ hsp_sp_csr: hsp-sp-top-csr@50440000 {
+ compatible = "eswin,eic7700-syscfg", "syscon";
+ reg = <0x0 0x50440000 0x0 0x2000>;
+ };
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v13 17/22] media: i2c: maxim-serdes: add MAX96724 driver
From: Dan Carpenter @ 2026-06-15 12:19 UTC (permalink / raw)
To: Niklas Söderlund
Cc: dumitru.ceclan, Tomi Valkeinen, Mauro Carvalho Chehab,
Sakari Ailus, Laurent Pinchart, Julien Massot, Rob Herring,
Greg Kroah-Hartman, mitrutzceclan, linux-media, linux-kernel,
devicetree, linux-staging, linux-gpio, Martin Hecht,
Cosmin Tanislav, Cory Keitz
In-Reply-To: <ail9bHXL_NV2DZK5@stanley.mountain>
On Wed, Jun 10, 2026 at 06:06:20PM +0300, Dan Carpenter wrote:
> On Wed, Jun 10, 2026 at 04:42:42PM +0200, Niklas Söderlund wrote:
> > Hi,
> >
> > Thanks for your work.
> >
> > This patch gives me new compiler warnings, can they be avoided?
> >
> > .../max96724.c:402 max96724_log_phy_status() warn: subtract is higher precedence than shift
> > .../max96724.c:409 max96724_log_phy_status() warn: subtract is higher precedence than shift
> > .../max96724.c:588 max96724_init_phy() warn: subtract is higher precedence than shift
> > .../max96724.c:756 max96724_set_pipe_remap() warn: subtract is higher precedence than shift
> > .../max96724.c:796 max96724_set_pipe_phy() warn: subtract is higher precedence than shift
> > .../max96724.c:818 max96724_set_pipe_stream_id() warn: subtract is higher precedence than shift
> > .../max96724.c:830 max96724_set_pipe_link() warn: subtract is higher precedence than shift
> > .../max96724.c:942 max96724_set_link_version() warn: subtract is higher precedence than shift
> >
>
> These are Smatch warnings. I appologize for them. I know about them
> but I haven't looked at them. I'll fix them by the end of the week.
I've pushed a fix for these to the devel branch of Smatch.
regards,
dan carpenter
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: glymur: fix PCIe SMMU interrupts
From: Konrad Dybcio @ 2026-06-15 12:19 UTC (permalink / raw)
To: Bjorn Andersson, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Qiang Yu, Raviteja Laggyshetty,
Jyothi Kumar Seerapu, Jishnu Prakash
Cc: Dmitry Baryshkov, Taniya Das, Sibi Sankar, linux-arm-msm,
devicetree, linux-kernel
In-Reply-To: <20260611-glymur-pcie-smmu-espi-v1-1-5effbaa3e1af@oss.qualcomm.com>
On 6/11/26 9:00 PM, Bjorn Andersson wrote:
> The PCIe SMMUv3 wired interrupts are routed to GIC extended SPI INTIDs
> 4100, 4098 and 4096. Describe them as ESPIs with the ESPI-relative
> interrupt numbers instead of regular SPIs 964, 962 and 960.
>
> Assisted-by: Codex:GPT-5.5
> Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
> Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH 3/3] backlight: lp8864: Convert from LED to backlight class driver
From: sashiko-bot @ 2026-06-15 12:16 UTC (permalink / raw)
To: A. Sverdlin; +Cc: devicetree, robh, dri-devel, conor+dt
In-Reply-To: <20260615120353.3409035-4-alexander.sverdlin@siemens.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Hardcoded backlight device name prevents probing multiple device instances.
- [High] Unclamped device tree brightness properties bypass limits and cause hardware wraparound.
- [High] The LED class interface completely ignores DT backlight limits, allowing userspace to overdrive the display.
- [Medium] Concurrent sysfs writes from the backlight and LED subsystems cause a data race on `priv->led_status_mask`.
--
commit 3a876b5316e78acf44b2217cdc076c3285471e8a
Author: Alexander Sverdlin <alexander.sverdlin@gmail.com>
backlight: lp8864: Convert from LED to backlight class driver
Move the TI LP8864/LP8866 driver from drivers/leds/ to drivers/video/backlight/
and convert it to register a backlight class device. The driver preserves
backward-compatible LED class device registration if the "led" child node is
present.
> diff --git a/drivers/video/backlight/lp8864_bl.c b/drivers/video/backlight/lp8864_bl.c
> index d05211b970c94..67b28f7daedd2 100644
> --- a/drivers/leds/leds-lp8864.c
> +++ b/drivers/video/backlight/lp8864_bl.c
[ ... ]
> @@ -157,28 +162,59 @@ static int lp8864_fault_check(struct lp8864 *priv)
> return ret;
> }
>
> -static int lp8864_brightness_set(struct led_classdev *led_cdev,
> - enum led_brightness brt_val)
> +static int lp8864_brightness_set(struct lp8864 *priv, unsigned int brightness)
> {
> - struct lp8864 *priv = container_of(led_cdev, struct lp8864, led_dev);
> - /* Scale 0..LED_FULL into 16-bit HW brightness */
> - unsigned int val = brt_val * 0xffff / LED_FULL;
> int ret;
>
> ret = lp8864_fault_check(priv);
[Severity: Medium]
Since the driver registers both a backlight device and an LED class
device, can concurrent sysfs writes to both interfaces cause a data race?
The LED and Backlight subsystems use independent locks (led_access mutex
and update_lock mutex). Parallel writes will result in concurrent calls to
lp8864_brightness_set(), which calls lp8864_fault_check().
Inside lp8864_fault_check(), the driver performs an unprotected
read-modify-write on priv->led_status_mask. Could this concurrent access
cause fault status updates to be lost?
> if (ret)
> return ret;
[ ... ]
> +static int lp8864_led_brightness_set(struct led_classdev *led_cdev,
> + enum led_brightness brt_val)
> +{
> + struct lp8864 *priv = dev_get_drvdata(led_cdev->dev->parent);
> +
> + /* Scale 0..LED_FULL into 16-bit HW brightness */
> + return lp8864_brightness_set(priv, brt_val * 0xffff / LED_FULL);
> +}
[Severity: High]
Does the LED class interface ignore the device tree backlight limits?
The backlight device respects props.max_brightness, but the parallel LED
interface scales the requested brightness using a hardcoded LED_FULL divisor
(brt_val * 0xffff / LED_FULL).
If a custom max-brightness is specified in the device tree, writing to
the LED sysfs interface could bypass this limit and write arbitrary high
values to the hardware. Could this overdrive and potentially damage the
display?
[ ... ]
> @@ -258,11 +290,46 @@ static int lp8864_probe(struct i2c_client *client)
> if (ret)
> return ret;
>
> + /* Register backlight class device */
> + memset(&props, 0, sizeof(props));
> + props.type = BACKLIGHT_RAW;
> + props.max_brightness = LP8864_MAX_BRIGHTNESS;
> + props.brightness = LP8864_MAX_BRIGHTNESS;
> + props.scale = BACKLIGHT_SCALE_LINEAR;
> +
> + if (!device_property_read_u32(&client->dev, "max-brightness", &val))
> + props.max_brightness = val;
> +
> + if (!device_property_read_u32(&client->dev, "default-brightness", &val))
> + props.brightness = val;
[Severity: High]
Could reading max-brightness without default-brightness bypass the
protective limits during boot?
If max-brightness is provided in the device tree but default-brightness
is not, props.brightness retains its initial 0xFFFF value. When
backlight_update_status() is called shortly after, it will write this
unconstrained 0xFFFF to the hardware.
Additionally, since device_property_read_u32() is used without upper bound
checks, would values greater than 65535 in the device tree wrap around
when passed to the 16-bit regmap_write() in lp8864_brightness_set()?
> +
> + bl = devm_backlight_device_register(&client->dev, "lp8864-backlight",
> + &client->dev, priv,
> + &lp8864_backlight_ops, &props);
[Severity: High]
Will using a fixed string for the backlight device name prevent probing
multiple instances?
The commit message mentions a use case on a hot-pluggable segment of an
I2C bus. If there are multiple LP8864 instances on the same system, the
second instance will fail to probe because the sysfs core mandates unique
names for devices in the same class.
Should this use a dynamically unique name, such as dev_name(&client->dev),
to avoid device_add() returning -EEXIST?
> + if (IS_ERR(bl))
> + return dev_err_probe(&client->dev, PTR_ERR(bl),
> + "Failed to register backlight device\n");
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260615120353.3409035-1-alexander.sverdlin@siemens.com?part=3
^ permalink raw reply
* Re: [PATCH v2 2/5] arm64: dts: renesas: r9a09g077: Add DU node
From: sashiko-bot @ 2026-06-15 12:16 UTC (permalink / raw)
To: Prabhakar; +Cc: robh, wsa+renesas, devicetree, conor+dt
In-Reply-To: <20260615115455.1412098-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Missing mandatory `resets` property in du, fcpvd, and vspd nodes
- [High] Unregistered CPG_MOD 1204 clock referenced in du, fcpvd, and vspd nodes
- [Medium] Incomplete device tree implementation without driver support or fallback compatible string for du node
- [Low] Undefined macro R9A09G077_LCDC_CLKD causes build failure
--
commit 00c766c42ba26d88fa78760fe26949b97a0f53f2
Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
arm64: dts: renesas: r9a09g077: Add DU node
Add Display Unit (DU) node to SoC DTSI.
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -1269,6 +1269,30 @@ sdhi1_vqmmc: vqmmc-regulator {
> };
> };
>
> + du: display@920c0000 {
> + compatible = "renesas,r9a09g077-du";
[Severity: Medium]
Does this compatible string need a generic fallback?
Without a fallback like "renesas,r9a09g057-du", and with no driver currently
matching "renesas,r9a09g077-du" in the tree, won't this regression prevent the
node from binding to a driver and cause a schema validation failure?
> + reg = <0 0x920c0000 0 0x10000>;
> + interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
> + <&cpg CPG_MOD 1204>,
[Severity: High]
Is module clock ID 1204 registered in the r9a09g077_mod_clks array in
drivers/clk/renesas/r9a09g077-cpg.c?
When the Renesas CPG-MSSR PM domain governor attempts to attach the du, fcpvd,
and vspd devices, won't of_clk_get_from_provider() fail and return -ENOENT
because the clock is missing? Could this regression prevent the devices from
being attached to the power domain?
> + <&cpg CPG_CORE R9A09G077_LCDC_CLKD>;
[Severity: Low]
Where is R9A09G077_LCDC_CLKD defined?
Since it doesn't appear to be defined in the device tree bindings headers for
the du, fcpvd, and vspd nodes, won't this regression cause the device tree
compiler to fail with a syntax error and break the build?
[Severity: High]
Do the du, fcpvd, and vspd nodes also need a resets property?
The DT bindings for the Renesas Display Unit, Frame Compression Processor,
and VSP Video Processing Engine mandate the resets property. Their respective
drivers call devm_reset_control_get_shared() without the _optional flag.
Without it, won't reset_control_get() return -ENOENT and cause this regression
where the driver probes fail?
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260615115455.1412098-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=2
^ permalink raw reply
* Re: [PATCH v4 4/7] drm/rcar-du: dsi: Support DSC in the pipeline
From: Tomi Valkeinen @ 2026-06-15 12:15 UTC (permalink / raw)
To: Laurent Pinchart, Tomi Valkeinen
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
Andrzej Hajda, Neil Armstrong, Robert Foss, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, Marek Vasut,
Kieran Bingham, Philipp Zabel, linux-renesas-soc, linux-clk,
linux-kernel, dri-devel, devicetree
In-Reply-To: <20260615091911.GB2821720@killaraus.ideasonboard.com>
Hi,
On 15/06/2026 12:19, Laurent Pinchart wrote:
> Hi Tomi,
>
> Thank you for the patch.
>
> On Mon, Jun 15, 2026 at 09:28:09AM +0300, Tomi Valkeinen wrote:
>> Enabling DSI clocks on rcar-du needs some tricks as the DU dot clock is
>> provided by the DSI. Thus, we call rcar_mipi_dsi_pclk_enable() from the
>> crtc, when enabling the crtc.
>>
>> With DSC (added in upcoming patch) in the pipeline, between the DU and
>> the DSI, the above call path is broken as the crtc tries to call
>> rcar_mipi_dsi_pclk_enable() on the DSC.
>>
>> To solve this problem, add checks to rcar_du_crtc_atomic_enable() and
>> rcar_du_crtc_atomic_disable() to detect the DSC via the bridge type, and
>> skip the DCS bridge when needed.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
>> ---
>> drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c | 18 ++++++++++++++++++
>> drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 1 +
>> 2 files changed, 19 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c
>> index 6c07c406f725..f14fd89f9104 100644
>> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c
>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c
>> @@ -754,6 +754,15 @@ static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
>> (BIT(RCAR_DU_OUTPUT_DSI0) | BIT(RCAR_DU_OUTPUT_DSI1)))) {
>> struct drm_bridge *bridge = rcdu->dsi[rcrtc->index];
>>
>> + /*
>> + * When we have a DSC block between the DU and the DSI,
>> + * the "bridge" points to the DSC. Detect the DSC by looking
>> + * at the bridge type, and skip the DSC if the bridge is not
>> + * the DSI bridge.
>> + */
>> + if (bridge->type != DRM_MODE_CONNECTOR_DSI)
>> + bridge = bridge->next_bridge;
>> +
>
> Is there a reason you don't do this in rcar_du_encoder_init() instead ?
> It would avoid running this code on every enable/disable.
That works too.
Both options feel a bit confusing, in different ways. Your suggestion is
less code and, I think, more correct as rcdu->dsi[] will always point to
a DSI bridge (although that itself is a bit confusing, as one could
expect it to point to a neighboring bridge from DU...), so I'll switch
to that.
Tomi
^ permalink raw reply
* Re: [PATCH v6 3/3] riscv64: dts: sophgo: add initial Milk-V Duo S board support
From: sashiko-bot @ 2026-06-15 12:14 UTC (permalink / raw)
To: Joshua Milas; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260615120324.1527881-4-josh.milas@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Contradictory eMMC voltage configuration artificially restricts eMMC speed capabilities
--
commit 9d652e59c7623b46a5dd7a0a5954061467e5aea7
Author: Joshua Milas <josh.milas@gmail.com>
riscv64: dts: sophgo: add initial Milk-V Duo S board support
This adds initial riscv support for the Milk-V Duo S board
making it possible to boot Linux to the command line.
Link: https://milkv.io/duo-s [1]
> diff --git a/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts b/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts
> new file mode 100644
> index 0000000000000..f56bfddeacc40
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts
[ ... ]
> +&pinctrl {
> + emmc_cfg: emmc-cfg {
> + emmc-rstn-pins {
> + pinmux = <PINMUX(PIN_EMMC_RSTN, 0)>;
> + bias-pull-up;
> + drive-strength-microamp = <10800>;
> + power-source = <1800>;
> + };
[ ... ]
> +&emmc {
> + bus-width = <4>;
> + no-1-8-v;
[Severity: Medium]
Is this contradictory eMMC voltage configuration intentional?
The pinctrl node emmc_cfg explicitly configures the eMMC pins to
operate at 1.8V (power-source = <1800>), but the &emmc node here
specifies the no-1-8-v property.
Since the hardware pads are physically configured for 1.8V, the interface
actually does support 1.8V signaling. Specifying no-1-8-v here artificially
restricts the eMMC to legacy, slower modes instead of negotiating
faster modes like HS200.
> + cap-mmc-hw-reset;
> + no-sd;
> + no-sdio;
> + non-removable;
> + pinctrl-0 = <&emmc_cfg>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260615120324.1527881-1-josh.milas@gmail.com?part=3
^ permalink raw reply
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