* Re: [PATCH 2/2] arm64: dts: qcom: lemans-evk: Describe the PCIe M.2 Key E connector
From: Wei Deng @ 2026-06-22 6:02 UTC (permalink / raw)
To: konrad.dybcio
Cc: andersson, robh, krzk+dt, conor+dt, mani, brgl, linux-arm-msm,
devicetree, linux-kernel, linux-pci, linux-pm, quic_chezhou,
cheng.jiang, shuai.zhang, jinwang.li, xiuzhuo.shang, mengshi.wu
In-Reply-To: <580db7de-321d-4f4e-99f9-3c9a1cc5a3f9@oss.qualcomm.com>
Hi Konrad,
On Thu, Jun 18, 2026 at 11:49:05AM +0200, Konrad Dybcio wrote:
> On 6/8/26 11:17 AM, Wei Deng wrote:
> > The lemans EVK has the PCIe M.2 Mechanical Key E connector to connect
> > wireless connectivity cards over PCIe and UART interfaces. Hence,
> > describe the connector node and link it with the PCIe 0 Root Port and
> > UART17 nodes through graph port/endpoint.
> >
> > Also add 'compatible = "pciclass,0604"' to the pcieport0 node in
> > lemans.dtsi to allow the PCI subsystem to associate the DT node with
> > the PCI-to-PCI bridge device.
>
> Ideally this would be a separate change
>
> Also, b4 can't grab this patch since there's something wrong with the
> threading (multiple series in a single thread) - please switch to using
> b4 for submissions yourself to avoid such mistakes.
>
> https://b4.docs.kernel.org/en/latest/
>
> Konrad
Thanks for the review. Agreed. Posting shortly.
--
Best Regards,
Wei Deng
^ permalink raw reply
* [PATCH 0/2] interconnect: qcom: Add support for upcoming Maili SoC
From: Raviteja Laggyshetty @ 2026-06-22 6:06 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jingyi Wang
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel,
Raviteja Laggyshetty, Odelu Kukatla
Add interconnect bindings and RPMh-based interconnect driver support for
the upcoming Qualcomm Maili SoC.
Device tree changes are not part of this series, they will be posted
separately.
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
Raviteja Laggyshetty (2):
dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
interconnect: qcom: add Maili interconnect provider driver
.../bindings/interconnect/qcom,maili-rpmh.yaml | 127 ++
drivers/interconnect/qcom/Kconfig | 10 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/maili.c | 2091 ++++++++++++++++++++
include/dt-bindings/interconnect/qcom,maili-rpmh.h | 172 ++
5 files changed, 2402 insertions(+)
---
base-commit: 3ce97bd3c4f18608335e709c24d6a40e7036cab8
change-id: 20260622-maili_icc-94001df2a4d3
Best regards,
--
Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
From: Raviteja Laggyshetty @ 2026-06-22 6:06 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jingyi Wang
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel,
Raviteja Laggyshetty, Odelu Kukatla
In-Reply-To: <20260622-maili_icc-v1-0-0aa8286e6748@oss.qualcomm.com>
Document the RPMh Network-On-Chip interconnect for the Qualcomm Maili
SoC.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
.../bindings/interconnect/qcom,maili-rpmh.yaml | 127 +++++++++++++++
include/dt-bindings/interconnect/qcom,maili-rpmh.h | 172 +++++++++++++++++++++
2 files changed, 299 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml
new file mode 100644
index 000000000000..3db8d8b23219
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,maili-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on Maili SoC
+
+maintainers:
+ - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also: include/dt-bindings/interconnect/qcom,maili-rpmh.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,maili-aggre-noc
+ - qcom,maili-clk-virt
+ - qcom,maili-cnoc-main
+ - qcom,maili-gem-noc
+ - qcom,maili-llclpi-noc
+ - qcom,maili-lpass-ag-noc
+ - qcom,maili-lpass-lpiaon-noc
+ - qcom,maili-lpass-lpicx-noc
+ - qcom,maili-mc-virt
+ - qcom,maili-mmss-noc
+ - qcom,maili-nsp-noc
+ - qcom,maili-pcie-anoc
+ - qcom,maili-stdst-cfg
+ - qcom,maili-stdst-main
+ - qcom,maili-system-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-clk-virt
+ - qcom,maili-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-aggre-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB3 PRIM AXI clock
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-pcie-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre-NOC PCIe AXI clock
+ - description: cfg-NOC PCIe a-NOC AHB clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-aggre-noc
+ - qcom,maili-pcie-anoc
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ gem_noc: interconnect@31100000 {
+ compatible = "qcom,maili-gem-noc";
+ reg = <0x31100000 0x160200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre_noc: interconnect@f00000 {
+ compatible = "qcom,maili-aggre-noc";
+ reg = <0x00f00000 0x56200>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc_phy_axi_clk>,
+ <&gcc_prim_axi_clk>,
+ <&rpmhcc_ipa_clk>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,maili-rpmh.h b/include/dt-bindings/interconnect/qcom,maili-rpmh.h
new file mode 100644
index 000000000000..e7a957a9d0f0
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,maili-rpmh.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_2 1
+#define MASTER_QUP_3 2
+#define MASTER_QUP_4 3
+#define MASTER_QUP_5 4
+#define MASTER_CRYPTO 5
+#define MASTER_IPA 6
+#define MASTER_QUP_1 7
+#define MASTER_SOCCP_PROC 8
+#define MASTER_QDSS_ETR 9
+#define MASTER_QDSS_ETR_1 10
+#define MASTER_SDCC_2 11
+#define MASTER_SDCC_4 12
+#define MASTER_UFS_MEM 13
+#define MASTER_USB3 14
+#define SLAVE_A1NOC_SNOC 15
+
+#define MASTER_DDR_EFF_VETO 0
+#define MASTER_QUP_CORE_0 1
+#define MASTER_QUP_CORE_1 2
+#define MASTER_QUP_CORE_2 3
+#define MASTER_QUP_CORE_3 4
+#define MASTER_QUP_CORE_4 5
+#define MASTER_QUP_CORE_5 6
+#define SLAVE_DDR_EFF_VETO 7
+#define SLAVE_QUP_CORE_0 8
+#define SLAVE_QUP_CORE_1 9
+#define SLAVE_QUP_CORE_2 10
+#define SLAVE_QUP_CORE_3 11
+#define SLAVE_QUP_CORE_4 12
+#define SLAVE_QUP_CORE_5 13
+
+#define MASTER_GEM_NOC_CNOC 0
+#define MASTER_GEM_NOC_PCIE_SNOC 1
+#define SLAVE_AOSS 2
+#define SLAVE_IPA_CFG 3
+#define SLAVE_IPC_ROUTER_FENCE 4
+#define SLAVE_SOCCP 5
+#define SLAVE_TME_CFG 6
+#define SLAVE_CNOC_CFG 7
+#define SLAVE_DDRSS_CFG 8
+#define SLAVE_IMEM 9
+#define SLAVE_PCIE_0 10
+#define SLAVE_PCIE_1 11
+
+#define MASTER_GIC 0
+#define MASTER_GPU_TCU 1
+#define MASTER_SYS_TCU 2
+#define MASTER_APPSS_PROC 3
+#define MASTER_GFX3D 4
+#define MASTER_LPASS_GEM_NOC 5
+#define MASTER_MSS_PROC 6
+#define MASTER_MNOC_HF_MEM_NOC 7
+#define MASTER_MNOC_SF_MEM_NOC 8
+#define MASTER_COMPUTE_NOC 9
+#define MASTER_ANOC_PCIE_GEM_NOC 10
+#define MASTER_QPACE 11
+#define MASTER_SNOC_SF_MEM_NOC 12
+#define MASTER_WLAN_Q6 13
+#define SLAVE_GEM_NOC_CNOC 14
+#define SLAVE_LLCC 15
+#define SLAVE_MEM_NOC_PCIE_SNOC 16
+
+#define MASTER_LPIAON_NOC_LLCLPI_NOC 0
+#define SLAVE_LPASS_LPI_CC 1
+#define SLAVE_LLCC_ISLAND 2
+#define SLAVE_SERVICE_LLCLPI_NOC 3
+#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4
+
+#define MASTER_LPIAON_NOC 0
+#define SLAVE_LPASS_GEM_NOC 1
+
+#define MASTER_LPASS_LPINOC 0
+#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2
+
+#define MASTER_LPASS_PROC 0
+#define SLAVE_LPICX_NOC_LPIAON_NOC 1
+
+#define MASTER_LLCC 0
+#define MASTER_DDR_RT 1
+#define SLAVE_EBI1 2
+#define SLAVE_DDR_RT 3
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_MDP 1
+#define SLAVE_MNOC_HF_MEM_NOC 2
+
+#define MASTER_CAMNOC_NRT_ICP_SF 0
+#define MASTER_CAMNOC_RT_CDM_SF 1
+#define MASTER_CAMNOC_SF 2
+#define MASTER_MDSS_DCP 3
+#define MASTER_CDSP_HCP 4
+#define MASTER_VIDEO_CV_PROC 5
+#define MASTER_VIDEO_EVA 6
+#define MASTER_VIDEO_MVP 7
+#define MASTER_VIDEO_V_PROC 8
+#define SLAVE_MNOC_SF_MEM_NOC 9
+
+#define MASTER_CDSP_PROC 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_PCIE_ANOC_CFG 0
+#define MASTER_PCIE_0 1
+#define MASTER_PCIE_1 2
+#define SLAVE_ANOC_PCIE_GEM_NOC 3
+#define SLAVE_SERVICE_PCIE_ANOC 4
+
+#define MASTER_CFG_CENTER 0
+#define MASTER_CFG_EAST 1
+#define MASTER_CFG_MM_HF 2
+#define MASTER_CFG_MM_SF 3
+#define MASTER_CFG_NORTH 4
+#define MASTER_CFG_SOUTH 5
+#define MASTER_CFG_WEST 6
+#define SLAVE_AHB2PHY_SOUTH 7
+#define SLAVE_BOOT_ROM 8
+#define SLAVE_CAMERA_CFG 9
+#define SLAVE_CLK_CTL 10
+#define SLAVE_CRYPTO_CFG 11
+#define SLAVE_DISPLAY_CFG 12
+#define SLAVE_EVA_CFG 13
+#define SLAVE_GFX3D_CFG 14
+#define SLAVE_I2C 15
+#define SLAVE_IMEM_CFG 16
+#define SLAVE_IPC_ROUTER_CFG 17
+#define SLAVE_IRIS_CFG 18
+#define SLAVE_CNOC_MSS 19
+#define SLAVE_PCIE_0_CFG 20
+#define SLAVE_PCIE_1_CFG 21
+#define SLAVE_PRNG 22
+#define SLAVE_QSPI_0 23
+#define SLAVE_QUP_1 24
+#define SLAVE_QUP_2 25
+#define SLAVE_QUP_3 26
+#define SLAVE_QUP_4 27
+#define SLAVE_QUP_5 28
+#define SLAVE_SDCC_2 29
+#define SLAVE_SDCC_4 30
+#define SLAVE_TLMM 31
+#define SLAVE_UFS_MEM_CFG 32
+#define SLAVE_USB3 33
+#define SLAVE_VSENSE_CTRL_CFG 34
+#define SLAVE_PCIE_ANOC_CFG 35
+#define SLAVE_QDSS_CFG 36
+#define SLAVE_QDSS_STM 37
+#define SLAVE_TCSR 38
+#define SLAVE_TCU 39
+
+#define MASTER_CNOC_STARDUST 0
+#define SLAVE_STARDUST_CENTER_CFG 1
+#define SLAVE_STARDUST_EAST_CFG 2
+#define SLAVE_STARDUST_MM_HF_CFG 3
+#define SLAVE_STARDUST_MM_SF_CFG 4
+#define SLAVE_STARDUST_NORTH_CFG 5
+#define SLAVE_STARDUST_SOUTH_CFG 6
+#define SLAVE_STARDUST_WEST_CFG 7
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_APSS_NOC 1
+#define MASTER_CNOC_SNOC 2
+#define SLAVE_SNOC_GEM_NOC_SF 3
+
+#endif
--
2.43.0
^ permalink raw reply related
* [PATCH 2/2] interconnect: qcom: add Maili interconnect provider driver
From: Raviteja Laggyshetty @ 2026-06-22 6:06 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jingyi Wang
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel,
Raviteja Laggyshetty, Odelu Kukatla
In-Reply-To: <20260622-maili_icc-v1-0-0aa8286e6748@oss.qualcomm.com>
Add driver for the Qualcomm interconnect buses found in Maili
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pairs.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
drivers/interconnect/qcom/Kconfig | 10 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/maili.c | 2091 ++++++++++++++++++++++++++++++++++++
3 files changed, 2103 insertions(+)
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 5b8a094ca4ed..5b57f111c63c 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -47,6 +47,16 @@ config INTERCONNECT_QCOM_KAANAPALI
This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
platforms.
+config INTERCONNECT_QCOM_MAILI
+ tristate "Qualcomm MAILI interconnect driver"
+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ default ARCH_QCOM
+ help
+ This is a driver for the Qualcomm Network-on-Chip on maili-based
+ platforms.
+
config INTERCONNECT_QCOM_MSM8909
tristate "Qualcomm MSM8909 interconnect driver"
depends on INTERCONNECT_QCOM
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 1c7d410b40cc..5f139a370bbe 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -8,6 +8,7 @@ qnoc-eliza-objs := eliza.o
qnoc-glymur-objs := glymur.o
qnoc-hawi-objs := hawi.o
qnoc-kaanapali-objs := kaanapali.o
+qnoc-maili-objs := maili.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
qnoc-msm8916-objs := msm8916.o
@@ -56,6 +57,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) += qnoc-eliza.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) += qnoc-hawi.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
+obj-$(CONFIG_INTERCONNECT_QCOM_MAILI) += qnoc-maili.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
diff --git a/drivers/interconnect/qcom/maili.c b/drivers/interconnect/qcom/maili.c
new file mode 100644
index 000000000000..e5eed7f998f9
--- /dev/null
+++ b/drivers/interconnect/qcom/maili.c
@@ -0,0 +1,2091 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,maili-rpmh.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+
+static struct qcom_icc_node ddr_eff_veto_slave = {
+ .name = "ddr_eff_veto_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup1_core_slave = {
+ .name = "qup1_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup2_core_slave = {
+ .name = "qup2_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup3_core_slave = {
+ .name = "qup3_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup4_core_slave = {
+ .name = "qup4_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup5_core_slave = {
+ .name = "qup5_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_aoss = {
+ .name = "qhs_aoss",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipa = {
+ .name = "qhs_ipa",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router_fence = {
+ .name = "qhs_ipc_router_fence",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_soccp = {
+ .name = "qhs_soccp",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tme_cfg = {
+ .name = "qhs_tme_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_ddrss_cfg = {
+ .name = "qss_ddrss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qxs_imem = {
+ .name = "qxs_imem",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie = {
+ .name = "xs_pcie",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie_g4x1 = {
+ .name = "xs_pcie_g4x1",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_lpi_cc = {
+ .name = "qhs_lpi_cc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_lb = {
+ .name = "qns_lb",
+ .channels = 4,
+ .buswidth = 16,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc = {
+ .name = "srvc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc_chipcx = {
+ .name = "srvc_llclpi_noc_chipcx",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ebi = {
+ .name = "ebi",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ddr_rt_slave = {
+ .name = "ddr_rt_slave",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_pcie_aggre_noc = {
+ .name = "srvc_pcie_aggre_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy0 = {
+ .name = "qhs_ahb2phy0",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_boot_rom = {
+ .name = "qhs_boot_rom",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_cfg = {
+ .name = "qhs_camera_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_clk_ctl = {
+ .name = "qhs_clk_ctl",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_crypto_cfg = {
+ .name = "qhs_crypto_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display_cfg = {
+ .name = "qhs_display_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_eva_cfg = {
+ .name = "qhs_eva_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpuss_cfg = {
+ .name = "qhs_gpuss_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_i2c = {
+ .name = "qhs_i2c",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_imem_cfg = {
+ .name = "qhs_imem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router = {
+ .name = "qhs_ipc_router",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_iris_cfg = {
+ .name = "qhs_iris_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_mss_cfg = {
+ .name = "qhs_mss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_cfg = {
+ .name = "qhs_pcie_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_g4x1_cfg = {
+ .name = "qhs_pcie_g4x1_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_prng = {
+ .name = "qhs_prng",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qspi = {
+ .name = "qhs_qspi",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup1 = {
+ .name = "qhs_qup1",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup2 = {
+ .name = "qhs_qup2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup3 = {
+ .name = "qhs_qup3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup4 = {
+ .name = "qhs_qup4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup5 = {
+ .name = "qhs_qup5",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc2 = {
+ .name = "qhs_sdc2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc4 = {
+ .name = "qhs_sdc4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tlmm = {
+ .name = "qhs_tlmm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ufs_mem_cfg = {
+ .name = "qhs_ufs_mem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb3 = {
+ .name = "qhs_usb3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
+ .name = "qhs_vsense_ctrl_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_cfg = {
+ .name = "qss_qdss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_stm = {
+ .name = "qss_qdss_stm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_tcsr = {
+ .name = "qss_tcsr",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node xs_sys_tcu_cfg = {
+ .name = "xs_sys_tcu_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node ddr_eff_veto_master = {
+ .name = "ddr_eff_veto_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_node qup1_core_master = {
+ .name = "qup1_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_node qup2_core_master = {
+ .name = "qup2_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_node qup3_core_master = {
+ .name = "qup3_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_node qup4_core_master = {
+ .name = "qup4_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_node qup5_core_master = {
+ .name = "qup5_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup5_core_slave },
+};
+
+static struct qcom_icc_node qnm_gemnoc_pcie = {
+ .name = "qnm_gemnoc_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 2,
+ .link_nodes = { &xs_pcie, &xs_pcie_g4x1 },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = {
+ .name = "qnm_lpiaon_noc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 4,
+ .link_nodes = { &qhs_lpi_cc, &qns_lb,
+ &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx },
+};
+
+static struct qcom_icc_node llcc_mc = {
+ .name = "llcc_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ebi },
+};
+
+static struct qcom_icc_node ddr_rt_mc = {
+ .name = "ddr_rt_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_node qsm_pcie_anoc_cfg = {
+ .name = "qsm_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &srvc_pcie_aggre_noc },
+};
+
+static struct qcom_icc_node qsm_cfg_center = {
+ .name = "qsm_cfg_center",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 14,
+ .link_nodes = { &qhs_boot_rom, &qhs_clk_ctl,
+ &qhs_crypto_cfg, &qhs_gpuss_cfg,
+ &qhs_imem_cfg, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_prng,
+ &qhs_tlmm, &qhs_vsense_ctrl_cfg,
+ &qss_qdss_cfg, &qss_qdss_stm,
+ &qss_tcsr, &xs_sys_tcu_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_east = {
+ .name = "qsm_cfg_east",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .link_nodes = { &qhs_qup2, &qhs_qup4 },
+};
+
+static struct qcom_icc_node qsm_cfg_mm_hf = {
+ .name = "qsm_cfg_mm_hf",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qhs_display_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_mm_sf = {
+ .name = "qsm_cfg_mm_sf",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 3,
+ .link_nodes = { &qhs_camera_cfg, &qhs_eva_cfg,
+ &qhs_iris_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_north = {
+ .name = "qsm_cfg_north",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 3,
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ufs_mem_cfg,
+ &qhs_usb3 },
+};
+
+static struct qcom_icc_node qsm_cfg_west = {
+ .name = "qsm_cfg_west",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .link_nodes = { &qhs_qup1, &qhs_sdc2 },
+};
+
+static struct qcom_icc_node qns_llcc = {
+ .name = "qns_llcc",
+ .channels = 4,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &llcc_mc },
+};
+
+static struct qcom_icc_node qns_pcie = {
+ .name = "qns_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_pcie },
+};
+
+static struct qcom_icc_node qns_llc_lpinoc = {
+ .name = "qns_llc_lpinoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc_llclpi_noc },
+};
+
+static struct qcom_icc_node qss_pcie_anoc_cfg = {
+ .name = "qss_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_pcie_anoc_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_center_cfg = {
+ .name = "qss_stdst_center_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_center },
+};
+
+static struct qcom_icc_node qss_stdst_east_cfg = {
+ .name = "qss_stdst_east_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_east },
+};
+
+static struct qcom_icc_node qss_stdst_mm_hf_cfg = {
+ .name = "qss_stdst_mm_hf_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_mm_hf },
+};
+
+static struct qcom_icc_node qss_stdst_mm_sf_cfg = {
+ .name = "qss_stdst_mm_sf_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_mm_sf },
+};
+
+static struct qcom_icc_node qss_stdst_north_cfg = {
+ .name = "qss_stdst_north_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_north },
+};
+
+static struct qcom_icc_node qss_stdst_west_cfg = {
+ .name = "qss_stdst_west_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_west },
+};
+
+static struct qcom_icc_node alm_gic = {
+ .name = "alm_gic",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14d000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_qpace = {
+ .name = "qnm_qpace",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x153000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qsm_cfg_south = {
+ .name = "qsm_cfg_south",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 8,
+ .link_nodes = { &qhs_i2c, &qhs_pcie_cfg,
+ &qhs_pcie_g4x1_cfg, &qhs_qspi,
+ &qhs_qup3, &qhs_qup5,
+ &qhs_sdc4, &qss_pcie_anoc_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_south_cfg = {
+ .name = "qss_stdst_south_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_south },
+};
+
+static struct qcom_icc_node qsm_cnoc_main = {
+ .name = "qsm_cnoc_main",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 7,
+ .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg,
+ &qss_stdst_mm_hf_cfg, &qss_stdst_mm_sf_cfg,
+ &qss_stdst_north_cfg, &qss_stdst_south_cfg,
+ &qss_stdst_west_cfg },
+};
+
+static struct qcom_icc_node qss_cfg = {
+ .name = "qss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cnoc_main },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+ .name = "qnm_gemnoc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 8,
+ .link_nodes = { &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem },
+};
+
+static struct qcom_icc_node qns_gem_noc_cnoc = {
+ .name = "qns_gem_noc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_cnoc },
+};
+
+static struct qcom_icc_node alm_gpu_tcu = {
+ .name = "alm_gpu_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x145000 },
+ .prio = 1,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node alm_sys_tcu = {
+ .name = "alm_sys_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x147000 },
+ .prio = 6,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node chm_apps = {
+ .name = "chm_apps",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_gpu = {
+ .name = "qnm_gpu",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x51000, 0xd1000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_lpass_gemnoc = {
+ .name = "qnm_lpass_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x149000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mdsp = {
+ .name = "qnm_mdsp",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_hf = {
+ .name = "qnm_mnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x55000, 0xd5000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_sf = {
+ .name = "qnm_mnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x57000, 0xd7000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_nsp_gemnoc = {
+ .name = "qnm_nsp_gemnoc",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x59000, 0xd9000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_pcie = {
+ .name = "qnm_pcie",
+ .channels = 1,
+ .buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14b000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+ .name = "qnm_snoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14f000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_wlan_q6 = {
+ .name = "qnm_wlan_q6",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
+ .name = "qns_lpass_ag_noc_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_gemnoc },
+};
+
+static struct qcom_icc_node qns_mem_noc_hf = {
+ .name = "qns_mem_noc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_hf },
+};
+
+static struct qcom_icc_node qns_mem_noc_sf = {
+ .name = "qns_mem_noc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_sf },
+};
+
+static struct qcom_icc_node qns_nsp_gemnoc = {
+ .name = "qns_nsp_gemnoc",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_nsp_gemnoc },
+};
+
+static struct qcom_icc_node qns_pcie_gemnoc = {
+ .name = "qns_pcie_gemnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_pcie },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+ .name = "qns_gemnoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_snoc_sf },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc = {
+ .name = "qnm_lpiaon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc },
+};
+
+static struct qcom_icc_node qnm_camnoc_hf = {
+ .name = "qnm_camnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x50000, 0x51000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_mdp = {
+ .name = "qnm_mdp",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x52000, 0x53000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
+ .name = "qnm_camnoc_nrt_icp_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x20000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
+ .name = "qnm_camnoc_rt_cdm_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x28000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_sf = {
+ .name = "qnm_camnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x21000, 0x22000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_mdss_dcp = {
+ .name = "qnm_mdss_dcp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x29000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_vapss_hcp = {
+ .name = "qnm_vapss_hcp",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_cv_cpu = {
+ .name = "qnm_video_cv_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x24000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_eva = {
+ .name = "qnm_video_eva",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x25000, 0x26000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_mvp = {
+ .name = "qnm_video_mvp",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x23000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_v_cpu = {
+ .name = "qnm_video_v_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x27000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_nsp = {
+ .name = "qnm_nsp",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie = {
+ .name = "xm_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 3,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie_g4x1 = {
+ .name = "xm_pcie_g4x1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node qnm_aggre_noc = {
+ .name = "qnm_aggre_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x20000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_apss_noc = {
+ .name = "qnm_apss_noc",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1e000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_cnoc_data = {
+ .name = "qnm_cnoc_data",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1f000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qns_a1noc_snoc = {
+ .name = "qns_a1noc_snoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_node qns_lpass_aggnoc = {
+ .name = "qns_lpass_aggnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc },
+};
+
+static struct qcom_icc_node qhm_qspi = {
+ .name = "qhm_qspi",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x49000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup2 = {
+ .name = "qhm_qup2",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x48000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup3 = {
+ .name = "qhm_qup3",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x46000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup4 = {
+ .name = "qhm_qup4",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x47000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup5 = {
+ .name = "qhm_qup5",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4e000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_crypto = {
+ .name = "qxm_crypto",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x40000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_ipa = {
+ .name = "qxm_ipa",
+ .channels = 1,
+ .buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x41000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_qup1 = {
+ .name = "qxm_qup1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4d000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_soccp = {
+ .name = "qxm_soccp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x45000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_0 = {
+ .name = "xm_qdss_etr_0",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x42000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_1 = {
+ .name = "xm_qdss_etr_1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x43000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc2 = {
+ .name = "xm_sdc2",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x44000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc4 = {
+ .name = "xm_sdc4",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_ufs_mem = {
+ .name = "xm_ufs_mem",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4b000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_usb3 = {
+ .name = "xm_usb3",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4c000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qnm_lpass_lpinoc = {
+ .name = "qnm_lpass_lpinoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 2,
+ .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_node qns_lpi_aon_noc = {
+ .name = "qns_lpi_aon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_lpinoc },
+};
+
+static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
+ .name = "qnm_lpinoc_dsp_qns4m",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpi_aon_noc },
+};
+
+static struct qcom_icc_bcm bcm_acv = {
+ .name = "ACV",
+ .enable_mask = BIT(3),
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_ce0 = {
+ .name = "CE0",
+ .num_nodes = 1,
+ .nodes = { &qxm_crypto },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+ .name = "CN0",
+ .enable_mask = BIT(0),
+ .keepalive = true,
+ .num_nodes = 25,
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
+ &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem,
+ &xs_pcie, &xs_pcie_g4x1,
+ &qsm_cfg_center, &qsm_cfg_east,
+ &qsm_cfg_mm_hf, &qsm_cfg_mm_sf,
+ &qsm_cfg_north, &qsm_cfg_south,
+ &qsm_cfg_west, &qhs_ahb2phy0,
+ &qhs_boot_rom, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_crypto_cfg,
+ &qhs_eva_cfg },
+};
+
+static struct qcom_icc_bcm bcm_cn1 = {
+ .name = "CN1",
+ .num_nodes = 6,
+ .nodes = { &qhs_display_cfg, &qhs_qup1,
+ &qhs_qup2, &qhs_qup3,
+ &qhs_qup4, &qhs_qup5 },
+};
+
+static struct qcom_icc_bcm bcm_co0 = {
+ .name = "CO0",
+ .enable_mask = BIT(0),
+ .num_nodes = 2,
+ .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_bcm bcm_de0 = {
+ .name = "DE0",
+ .enable_mask = BIT(0),
+ .num_nodes = 1,
+ .nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_bcm bcm_lp0 = {
+ .name = "LP0",
+ .num_nodes = 5,
+ .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb,
+ &qnm_lpass_lpinoc, &qns_llc_lpinoc,
+ &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+ .name = "MC0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_mc5 = {
+ .name = "MC5",
+ .num_nodes = 1,
+ .nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_bcm bcm_mm0 = {
+ .name = "MM0",
+ .num_nodes = 1,
+ .nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_bcm bcm_mm1 = {
+ .name = "MM1",
+ .enable_mask = BIT(0),
+ .num_nodes = 9,
+ .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
+ &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
+ &qnm_vapss_hcp, &qnm_video_cv_cpu,
+ &qnm_video_mvp, &qnm_video_v_cpu,
+ &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_bcm bcm_qpc0 = {
+ .name = "QPC0",
+ .num_nodes = 1,
+ .nodes = { &qnm_qpace },
+};
+
+static struct qcom_icc_bcm bcm_qup0 = {
+ .name = "QUP0",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup1 = {
+ .name = "QUP1",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup2 = {
+ .name = "QUP2",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup3 = {
+ .name = "QUP3",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup4 = {
+ .name = "QUP4",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup5 = {
+ .name = "QUP5",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup5_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+ .name = "SH0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh1 = {
+ .name = "SH1",
+ .enable_mask = BIT(0),
+ .num_nodes = 15,
+ .nodes = { &alm_gic, &alm_gpu_tcu,
+ &alm_sys_tcu, &chm_apps,
+ &qnm_gpu, &qnm_lpass_gemnoc,
+ &qnm_mdsp, &qnm_mnoc_hf,
+ &qnm_mnoc_sf, &qnm_nsp_gemnoc,
+ &qnm_pcie, &qnm_snoc_sf,
+ &qnm_wlan_q6, &qns_gem_noc_cnoc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+ .name = "SN0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sn2 = {
+ .name = "SN2",
+ .num_nodes = 1,
+ .nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn3 = {
+ .name = "SN3",
+ .num_nodes = 1,
+ .nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
+ &bcm_ce0,
+};
+
+static struct qcom_icc_node * const aggre1_noc_nodes[] = {
+ [MASTER_QSPI_0] = &qhm_qspi,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_QUP_3] = &qhm_qup3,
+ [MASTER_QUP_4] = &qhm_qup4,
+ [MASTER_QUP_5] = &qhm_qup5,
+ [MASTER_CRYPTO] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_QUP_1] = &qxm_qup1,
+ [MASTER_SOCCP_PROC] = &qxm_soccp,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
+ [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
+ [MASTER_SDCC_2] = &xm_sdc2,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB3] = &xm_usb3,
+ [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+};
+
+static const struct regmap_config maili_aggre1_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x56200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_aggre1_noc = {
+ .config = &maili_aggre1_noc_regmap_config,
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const clk_virt_bcms[] = {
+ &bcm_de0,
+ &bcm_qup0,
+ &bcm_qup1,
+ &bcm_qup2,
+ &bcm_qup3,
+ &bcm_qup4,
+ &bcm_qup5,
+};
+
+static struct qcom_icc_node * const clk_virt_nodes[] = {
+ [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master,
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [MASTER_QUP_CORE_1] = &qup1_core_master,
+ [MASTER_QUP_CORE_2] = &qup2_core_master,
+ [MASTER_QUP_CORE_3] = &qup3_core_master,
+ [MASTER_QUP_CORE_4] = &qup4_core_master,
+ [MASTER_QUP_CORE_5] = &qup5_core_master,
+ [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+ [SLAVE_QUP_CORE_1] = &qup1_core_slave,
+ [SLAVE_QUP_CORE_2] = &qup2_core_slave,
+ [SLAVE_QUP_CORE_3] = &qup3_core_slave,
+ [SLAVE_QUP_CORE_4] = &qup4_core_slave,
+ [SLAVE_QUP_CORE_5] = &qup5_core_slave,
+};
+
+static const struct qcom_icc_desc maili_clk_virt = {
+ .nodes = clk_virt_nodes,
+ .num_nodes = ARRAY_SIZE(clk_virt_nodes),
+ .bcms = clk_virt_bcms,
+ .num_bcms = ARRAY_SIZE(clk_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
+ &bcm_cn0,
+};
+
+static struct qcom_icc_node * const cnoc_main_nodes[] = {
+ [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence,
+ [SLAVE_SOCCP] = &qhs_soccp,
+ [SLAVE_TME_CFG] = &qhs_tme_cfg,
+ [SLAVE_CNOC_CFG] = &qss_cfg,
+ [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
+ [SLAVE_IMEM] = &qxs_imem,
+ [SLAVE_PCIE_0] = &xs_pcie,
+ [SLAVE_PCIE_1] = &xs_pcie_g4x1,
+};
+
+static const struct regmap_config maili_cnoc_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_cnoc_main = {
+ .config = &maili_cnoc_main_regmap_config,
+ .nodes = cnoc_main_nodes,
+ .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
+ .bcms = cnoc_main_bcms,
+ .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
+};
+
+static struct qcom_icc_bcm * const gem_noc_bcms[] = {
+ &bcm_qpc0,
+ &bcm_sh0,
+ &bcm_sh1,
+};
+
+static struct qcom_icc_node * const gem_noc_nodes[] = {
+ [MASTER_GIC] = &alm_gic,
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_GFX3D] = &qnm_gpu,
+ [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
+ [MASTER_MSS_PROC] = &qnm_mdsp,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_QPACE] = &qnm_qpace,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_WLAN_Q6] = &qnm_wlan_q6,
+ [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
+};
+
+static const struct regmap_config maili_gem_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x160200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_gem_noc = {
+ .config = &maili_gem_noc_regmap_config,
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const llclpi_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const llclpi_noc_nodes[] = {
+ [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc,
+ [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc,
+ [SLAVE_LLCC_ISLAND] = &qns_lb,
+ [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc,
+ [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx,
+};
+
+static const struct regmap_config maili_llclpi_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x17200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_llclpi_noc = {
+ .config = &maili_llclpi_noc_regmap_config,
+ .nodes = llclpi_noc_nodes,
+ .num_nodes = ARRAY_SIZE(llclpi_noc_nodes),
+ .bcms = llclpi_noc_bcms,
+ .num_bcms = ARRAY_SIZE(llclpi_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
+ [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
+ [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
+};
+
+static const struct regmap_config maili_lpass_ag_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xc080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_lpass_ag_noc = {
+ .config = &maili_lpass_ag_noc_regmap_config,
+ .nodes = lpass_ag_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
+ [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
+ [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc,
+ [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
+};
+
+static const struct regmap_config maili_lpass_lpiaon_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x19080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_lpass_lpiaon_noc = {
+ .config = &maili_lpass_lpiaon_noc_regmap_config,
+ .nodes = lpass_lpiaon_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
+ .bcms = lpass_lpiaon_noc_bcms,
+ .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
+ [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
+ [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
+};
+
+static const struct regmap_config maili_lpass_lpicx_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x46080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_lpass_lpicx_noc = {
+ .config = &maili_lpass_lpicx_noc_regmap_config,
+ .nodes = lpass_lpicx_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_mc0,
+ &bcm_mc5,
+};
+
+static struct qcom_icc_node * const mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [MASTER_DDR_RT] = &ddr_rt_mc,
+ [SLAVE_EBI1] = &ebi,
+ [SLAVE_DDR_RT] = &ddr_rt_slave,
+};
+
+static const struct qcom_icc_desc maili_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+};
+
+static struct qcom_icc_node * const mmss_noc_nodes[] = {
+ [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+ [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
+ [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
+ [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+ [MASTER_MDP] = &qnm_mdp,
+ [MASTER_MDSS_DCP] = &qnm_mdss_dcp,
+ [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
+ [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
+ [MASTER_VIDEO_EVA] = &qnm_video_eva,
+ [MASTER_VIDEO_MVP] = &qnm_video_mvp,
+ [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+};
+
+static const struct regmap_config maili_mmss_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5f800,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_mmss_noc = {
+ .config = &maili_mmss_noc_regmap_config,
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
+ &bcm_co0,
+};
+
+static struct qcom_icc_node * const nsp_noc_nodes[] = {
+ [MASTER_CDSP_PROC] = &qnm_nsp,
+ [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
+};
+
+static const struct regmap_config maili_nsp_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x21280,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_nsp_noc = {
+ .config = &maili_nsp_noc_regmap_config,
+ .nodes = nsp_noc_nodes,
+ .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
+ .bcms = nsp_noc_bcms,
+ .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node * const pcie_anoc_nodes[] = {
+ [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
+ [MASTER_PCIE_0] = &xm_pcie,
+ [MASTER_PCIE_1] = &xm_pcie_g4x1,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
+ [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
+};
+
+static const struct regmap_config maili_pcie_anoc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x12400,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_pcie_anoc = {
+ .config = &maili_pcie_anoc_regmap_config,
+ .nodes = pcie_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
+ .bcms = pcie_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const stdst_cfg_bcms[] = {
+ &bcm_cn0,
+ &bcm_cn1,
+};
+
+static struct qcom_icc_node * const stdst_cfg_nodes[] = {
+ [MASTER_CFG_CENTER] = &qsm_cfg_center,
+ [MASTER_CFG_EAST] = &qsm_cfg_east,
+ [MASTER_CFG_MM_HF] = &qsm_cfg_mm_hf,
+ [MASTER_CFG_MM_SF] = &qsm_cfg_mm_sf,
+ [MASTER_CFG_NORTH] = &qsm_cfg_north,
+ [MASTER_CFG_SOUTH] = &qsm_cfg_south,
+ [MASTER_CFG_WEST] = &qsm_cfg_west,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+ [SLAVE_BOOT_ROM] = &qhs_boot_rom,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_EVA_CFG] = &qhs_eva_cfg,
+ [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_I2C] = &qhs_i2c,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_IRIS_CFG] = &qhs_iris_cfg,
+ [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QSPI_0] = &qhs_qspi,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_QUP_3] = &qhs_qup3,
+ [SLAVE_QUP_4] = &qhs_qup4,
+ [SLAVE_QUP_5] = &qhs_qup5,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB3] = &qhs_usb3,
+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+ [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
+ [SLAVE_QDSS_CFG] = &qss_qdss_cfg,
+ [SLAVE_QDSS_STM] = &qss_qdss_stm,
+ [SLAVE_TCSR] = &qss_tcsr,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static const struct regmap_config maili_stdst_cfg_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x9000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_stdst_cfg = {
+ .config = &maili_stdst_cfg_regmap_config,
+ .nodes = stdst_cfg_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_cfg_nodes),
+ .bcms = stdst_cfg_bcms,
+ .num_bcms = ARRAY_SIZE(stdst_cfg_bcms),
+};
+
+static struct qcom_icc_node * const stdst_main_nodes[] = {
+ [MASTER_CNOC_STARDUST] = &qsm_cnoc_main,
+ [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg,
+ [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg,
+ [SLAVE_STARDUST_MM_HF_CFG] = &qss_stdst_mm_hf_cfg,
+ [SLAVE_STARDUST_MM_SF_CFG] = &qss_stdst_mm_sf_cfg,
+ [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg,
+ [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg,
+ [SLAVE_STARDUST_WEST_CFG] = &qss_stdst_west_cfg,
+};
+
+static const struct regmap_config maili_stdst_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf9000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_stdst_main = {
+ .config = &maili_stdst_main_regmap_config,
+ .nodes = stdst_main_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_main_nodes),
+};
+
+static struct qcom_icc_bcm * const system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn2,
+};
+
+static struct qcom_icc_node * const system_noc_nodes[] = {
+ [MASTER_A1NOC_SNOC] = &qnm_aggre_noc,
+ [MASTER_APSS_NOC] = &qnm_apss_noc,
+ [MASTER_CNOC_SNOC] = &qnm_cnoc_data,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+};
+
+static const struct regmap_config maili_system_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_system_noc = {
+ .config = &maili_system_noc_regmap_config,
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,maili-aggre-noc", .data = &maili_aggre1_noc },
+ { .compatible = "qcom,maili-clk-virt", .data = &maili_clk_virt },
+ { .compatible = "qcom,maili-cnoc-main", .data = &maili_cnoc_main },
+ { .compatible = "qcom,maili-gem-noc", .data = &maili_gem_noc },
+ { .compatible = "qcom,maili-llclpi-noc", .data = &maili_llclpi_noc },
+ { .compatible = "qcom,maili-lpass-ag-noc", .data = &maili_lpass_ag_noc },
+ { .compatible = "qcom,maili-lpass-lpiaon-noc", .data = &maili_lpass_lpiaon_noc },
+ { .compatible = "qcom,maili-lpass-lpicx-noc", .data = &maili_lpass_lpicx_noc },
+ { .compatible = "qcom,maili-mc-virt", .data = &maili_mc_virt },
+ { .compatible = "qcom,maili-mmss-noc", .data = &maili_mmss_noc },
+ { .compatible = "qcom,maili-nsp-noc", .data = &maili_nsp_noc },
+ { .compatible = "qcom,maili-pcie-anoc", .data = &maili_pcie_anoc },
+ { .compatible = "qcom,maili-stdst-cfg", .data = &maili_stdst_cfg },
+ { .compatible = "qcom,maili-stdst-main", .data = &maili_stdst_main },
+ { .compatible = "qcom,maili-system-noc", .data = &maili_system_noc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qcom_icc_rpmh_probe,
+ .remove = qcom_icc_rpmh_remove,
+ .driver = {
+ .name = "qnoc-maili",
+ .of_match_table = qnoc_of_match,
+ .sync_state = icc_sync_state,
+ },
+};
+
+static int __init qnoc_driver_init(void)
+{
+ return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+ platform_driver_unregister(&qnoc_driver);
+}
+module_exit(qnoc_driver_exit);
+
+MODULE_DESCRIPTION("Qualcomm Maili NoC driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v4 1/2] ASoC: dt-bindings: nuvoton,nau8360: Add NAU83G60
From: YLCHANG2 @ 2026-06-22 6:10 UTC (permalink / raw)
To: Krzysztof Kozlowski, Neo Chang
Cc: broonie, lgirdwood, perex, robh, krzk+dt, linux-sound, devicetree,
alsa-devel, kchsu0, sjlin0
In-Reply-To: <20260609-hysterical-rhino-of-resistance-d7e1da@quoll>
On 6/9/26 15:04, Krzysztof Kozlowski wrote:
> On Tue, Jun 09, 2026 at 10:41:27AM +0800, Neo Chang wrote:
>> Add device tree bindings documentation for the Nuvoton NAU83G60
>> audio amplifier.
>>
>> Signed-off-by: Neo Chang <YLCHANG2@nuvoton.com>
>> ---
>> Changes in v4:
>> - Refine the `firmware-name` description to clarify the loading order
>> (Left then Right) and the PBTL mode behavior.
>> - Remove the "dsp bypass" option description.
>> - Update the example node to follow devicetree coding styles.
>>
>> Changes in v3:
>> - Remove colon to resolve YAML build warnings.
>> - Fix 'firmware-name' property definition to comply with binding schemas
>>
>> Changes in v2:
>> - Dropped the word "driver" from the description.
>> - Removed runtime/software configuration properties:
>> nuvoton,low-latency, nuvoton,anc-enable, nuvoton,aec-enable,
>> nuvoton,vbat-microvolt, and nuvoton,tdm-channel-length.
>> - Added missing "nuvoton,dac-cur-enable" property for static speaker impedance matching.
>> - Removed unnecessary '|' formatting from single-line descriptions.
>> - Fixed typo in firmware-name property.
>> ---
>> .../bindings/sound/nuvoton,nau8360.yaml | 83 +++++++++++++++++++
>> 1 file changed, 83 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/sound/nuvoton,nau8360.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/sound/nuvoton,nau8360.yaml b/Documentation/devicetree/bindings/sound/nuvoton,nau8360.yaml
>> new file mode 100644
>> index 000000000000..2d19aedf1419
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/sound/nuvoton,nau8360.yaml
>> @@ -0,0 +1,83 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/sound/nuvoton,nau8360.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Nuvoton NAU83G60 Stereo Class-D Amplifier with DSP
>> +
>> +description:
>> + Stereo Class-D Amplifier with DSP and I/V-sense.
>> + This device supports I2C.
>> +
>> +maintainers:
>> + - Neo Chang <YLCHANG2@nuvoton.com>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - nuvoton,nau8360
>> +
>> + reg:
>> + maxItems: 1
>> + description:
> You want |
>
> Or this could be just enum of addresses, no need to copy paste address
> decoding from datasheet.
Thank you for the suggestion. I will modify it to an enum of addresses
and remove redundant description in v5.
>
>> + The I2C address of the device. The address is determined by the external
>> + hardware configuration of GPIO1 and GPIO2 pins.
>> + - 0x1a (GPIO2=Low, GPIO1=Low)
>> + - 0x1b (GPIO2=Low, GPIO1=High)
>> + - 0x4a (GPIO2=High, GPIO1=Low)
>> + - 0x4b (GPIO2=High, GPIO1=High)
>> +
>> + "#sound-dai-cells":
>> + const: 0
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + const: mclk
>> +
>> + firmware-name:
>> + minItems: 2
>> + maxItems: 2
>> + description:
>> + Assign firmware filenames for Left and Right DSP cores.
>> + The first firmware is for the Left channel,
>> + and the second is for the Right channel.
> Drop all above and just list the items with description
>
>> + In PBTL mode, the Left firmware is ignored and only the Right is applied.
> Combining also this.
>
> items:
> - description: ...
> - description: ...
Got it, I will format this using items and merge the descriptions in v5.
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* Re: [PATCH v4 2/2] ASoC: codecs: nau8360: Add support for NAU83G60 amplifier
From: YLCHANG2 @ 2026-06-22 6:12 UTC (permalink / raw)
To: Cezary Rojewski, Neo Chang
Cc: lgirdwood, perex, robh, krzk+dt, linux-sound, devicetree,
alsa-devel, kchsu0, sjlin0, Mark Brown
In-Reply-To: <329cf637-786d-4fee-9c63-b8e73827b330@intel.com>
On 6/9/26 17:49, Cezary Rojewski wrote:
> On 6/9/2026 4:41 AM, Neo Chang wrote:
>> Add support for the Nuvoton NAU83G60 audio codec. The NAU83G60 is a
>> stereo 30W+30W smart amplifier with an integrated low-latency
>> Advanced Audio DSP.
>
> Hi Neo,
>
> I've provided a number of possible improvements and nitpicks which
> scale for the entire file - not just the occurrences I've
> highlighted. In general, it's hard to follow the code. A lot of
> arithmetics bundled together with limited
> spacing/comments/self-explanatory names. Sheer number of
> if-statements and brackets does not help either.
>
> There seem to be quite a bit of defensive programming here too -
> checks just to print a message. I'd suggest to enlist event tracing
> and log the TX/RX communication unconditionally. Would eliminate the
> need for many of prints found here.
Hi Cezary,
Thank you for the detailed review and the valuable suggestions regarding
the code structure, readability, and coding style.
I will apply these suggestions in v5 to make the code easier to follow.
Regarding the defensive programming, I will drop those redundant print
checks.
If necessary, I will consider adding event tracing for TX/RX in a future
patch.
>
>> +static int nau8360_reply_from_dsp(struct snd_soc_component *component,
>> + const struct nau8360_cmd_info *cmd_info, int data_size,
>> + void *data, unsigned short dsp_addr)
>> +{
>> + struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component);
>> + struct device *dev = component->dev;
>> + unsigned int payload, *data_buf;
>> + int i, j, ret, frag_len, frag_payload_len, len_pos, pad_len,
>> pad_len_exp;
>> + int data_count = 0;
>
> 13 local variables. Does not look good. I'd try to refactor this
> one. Ask yourself - what's the (one) goal this function shall
> achieve. It's clear that currently it does more than one thing e.g.:
> performs validation of the payload. The validation could be moved
> into a separate function.
I will refactor this function and extract the logic into a separate
helper function to simplify this and reduce the number of local
variables in v5.
>
>> +
>> + if (!cmd_info->reply_data) {
>> + dsp_dbg(dev, "The cmd without reply data!!");
>> + ret = nau8360_dsp_replied(nau8360, &frag_len, dsp_addr);
>> + if (ret)
>> + goto err;
>> + else if (!frag_len)
>> + goto done;
>
> No need for 'else if', 'if' suffices.
I will change this to a simple 'if' in v5.
>
>> + }
>> +
>> + if (!data) {
>> + ret = -EINVAL;
>> + goto err;
>> + }
>> + data_buf = (unsigned int *)data;
>> +
>> + ret = nau8360_dsp_replied(nau8360, &frag_len, dsp_addr);
>> + if (ret)
>> + goto err;
>> + else if (!frag_len)
>> + goto done;
>
> Ditto.
Ditto, will update to a simple 'if' in v5.
>
>> +
>> + frag_payload_len = frag_len - 1;
>> + if (cmd_info->msg_param)
>> + data_count = data_size;
>> + for (i = 0; i < frag_payload_len; i++) {
>> + ret = regmap_read(nau8360->regmap, dsp_addr, &payload);
>> + if (ret) {
>> + dev_err(dev, "failed to read payload of dsp");
>> + goto err;
>> + }
>> + if (cmd_info->msg_param) {
>> + if (data_count >= NAU8360_DSP_DATA_BYTE) {
>> + *data_buf++ = payload;
>> + data_count -= NAU8360_DSP_DATA_BYTE;
>> + payload_read(dev, payload);
>> + } else {
>> + for (j = 0; j < NAU8360_DSP_DATA_BYTE; j++) {
>> + if (data_count <= 0)
>> + break;
>> +
>> + ((u8 *)data_buf)[j] = (payload >> (j * 8)) & 0xff;
>> + data_count--;
>> + }
>> + payload_read(dev, payload);
>> + break;
>> + }
>> + } else {
>> + *data_buf = payload;
>> + payload_read(dev, payload);
>> + }
>> + }
>> +
>> + /* check the reply length same as request */
>> + if (data_count && (cmd_info->cmd_id ==
>> NAU8360_DSP_CMD_GET_KCS_RSLTS ||
>> + cmd_info->cmd_id == NAU8360_DSP_CMD_GET_KCS_SETUP)) {
>> + dev_warn(dev, "payload_len %d, expected %d",
>> + data_size - data_count, data_size);
>> + }
>> + dsp_dbg(dev, "reading trailing fragment");
>> + ret = regmap_read(nau8360->regmap, dsp_addr, &payload);
>> + if (ret) {
>> + dev_err(dev, "failed to read trailing fragment");
>> + goto err;
>> + }
>> +
>> + len_pos = payload & 0xff;
>> + len_pos |= ((payload >> 8) & 0xc0) << 2;
>> + if (len_pos != frag_len) {
>> + dev_err(dev, "LEN_POST %02X, expect %02X", len_pos, frag_len);
>> + ret = -EPROTO;
>> + goto err;
>> + }
>> +
>> + pad_len = ((payload >> 8) & 0x30) >> 4;
>> + if (cmd_info->msg_param)
>> + pad_len_exp = frag_payload_len * NAU8360_DSP_DATA_BYTE -
>> + (data_size - data_count);
>> + else
>> + pad_len_exp = 0;
>> + if (pad_len != pad_len_exp) {
>> + dev_err(dev, "PAD_LEN %02X, expect %02X", pad_len,
>> pad_len_exp);
>> + ret = -EPROTO;
>> + goto err;
>> + }
>> + dsp_dbg(dev, "LEN_POST 0x%x, PAD_LEN 0x%x", len_pos, pad_len);
>> + payload_read(dev, payload);
>> +done:
>> + return 0;
>> +err:
>> + dev_err(dev, "DSP reply error %d !!!", ret);
>> + return ret;
>> +}
>
> ...
>
>> +int nau8360_dsp_init(struct snd_soc_component *component)
>> +{
>> + dev_info(component->dev, "DSP initializing...");
>> + return nau8360_dsp_set_kcs_setup(component);
>> +}
>
> Do we need a function that just inlines to nau8360_dsp_set_kcs_setup()
> except for a single print? Doubt so.
I will repurpose this function in v5. nau8360_dsp_init() will now handle
the core DSP initialization logic and
wait for the firmware loading to complete.
>
> ...
>
>> +static int nau8360_adacl_event(struct snd_soc_dapm_widget *w,
>> + struct snd_kcontrol *kcontrol, int event)
>> +{
>> + struct snd_soc_component *component =
>> snd_soc_dapm_to_component(w->dapm);
>> +
>> + if (SND_SOC_DAPM_EVENT_ON(event))
>> + snd_soc_component_update_bits(component, NAU8360_R6E_DAC_CFG0,
>> + NAU8360_PD_DACL_DIS, 0);
>> +
>> + return 0;
>> +}
>> +
>> +static int nau8360_adacr_event(struct snd_soc_dapm_widget *w,
>> + struct snd_kcontrol *kcontrol, int event)
>> +{
>> + struct snd_soc_component *component =
>> snd_soc_dapm_to_component(w->dapm);
>> +
>> + if (SND_SOC_DAPM_EVENT_ON(event))
>> + snd_soc_component_update_bits(component, NAU8360_R6E_DAC_CFG0,
>> + NAU8360_PD_DACR_DIS, 0);
>> +
>> + return 0;
>> +}
>> +
>> +static int nau8360_dacl_event(struct snd_soc_dapm_widget *w,
>> + struct snd_kcontrol *kcontrol, int event)
>> +{
>> + struct snd_soc_component *component =
>> snd_soc_dapm_to_component(w->dapm);
>> +
>> + if (SND_SOC_DAPM_EVENT_OFF(event))
>> + snd_soc_component_update_bits(component, NAU8360_R6E_DAC_CFG0,
>> + NAU8360_PD_DACL_DIS, NAU8360_PD_DACL_DIS);
>> +
>> + return 0;
>> +}
>> +
>> +static int nau8360_dacr_event(struct snd_soc_dapm_widget *w,
>> + struct snd_kcontrol *kcontrol, int event)
>> +{
>> + struct snd_soc_component *component =
>> snd_soc_dapm_to_component(w->dapm);
>> +
>> + if (SND_SOC_DAPM_EVENT_OFF(event))
>> + snd_soc_component_update_bits(component, NAU8360_R6E_DAC_CFG0,
>> + NAU8360_PD_DACR_DIS, NAU8360_PD_DACR_DIS);
>> +
>> + return 0;
>> +}
>
> Refactor the above four functions - you could create a wrapper to
> lower LOCs without huring the readability. If you prefer, instead of
> a one-for-four, you could have one "positive" wrapper (handles
> EVENT_ON cases) and a "negative" one (handles EVENT_OFF cases).
I will refactor these into a common function to reduce LOC in v5.
>
> ...
>
>> +static int nau8360_codec_probe(struct snd_soc_component *component)
>> +{
>> + struct snd_soc_dapm_context *dapm =
>> snd_soc_component_to_dapm(component);
>> + struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component);
>> + struct regmap *regmap = nau8360->regmap;
>> + struct device *dev = nau8360->dev;
>> + int ret, vbat, vsaw_level, vsaw_slope;
>> +
>> + nau8360->dapm = dapm;
>> + nau8360_coeff_set_def(nau8360);
>> + ret = nau8360_dsp_setup(component);
>> + if (ret)
>> + goto err;
>> +
>> + ret = nau8360_dsp_setup_controls(component);
>> + if (ret) {
>> + nau8360_dsp_enable(regmap, false);
>> + dev_err(dev, "DSP setup controls failed(%d)", ret);
>> + goto err;
>> + }
>> +
>> + /* default disable Sense signal after booting */
>> + snd_soc_dapm_disable_pin(nau8360->dapm, "Sense");
>> + snd_soc_dapm_sync(nau8360->dapm);
>> +
>> + /* VBAT is sensed by chip. */
>> + ret = nau8360_vbat_level(regmap, &vbat);
>> + if (ret) {
>> + dev_err(dev, "Failed to get valid VBAT level: %d\n", ret);
>> + goto err;
>> + }
>> + dev_dbg(dev, "VBAT %dV for nau8360", vbat);
>> +
>> + /* Config sawtooth clock according to VBAT. Class D modulator
>> input short setting
>> + * for mute and de-pop purpose. Restore normal after initiation.
>> + */
>> + ret = nau8360_sawtooth_params(vbat, &vsaw_level, &vsaw_slope);
>> + if (ret) {
>> + dev_err(dev, "can't get sawtooth clock parameters (%d)", ret);
>> + goto err;
>> + }
>> + regmap_update_bits(regmap, NAU8360_RA5_ANA_REG_1,
>> NAU8360_VSAW_LV_MASK |
>> + NAU8360_KVCO_SAW_MASK, (vsaw_level << NAU8360_VSAW_LV_SFT) |
>> + (vsaw_slope << NAU8360_KVCO_SAW_SFT));
>> +
>> + return 0;
>> +err:
>> + return ret;
>
> Why are we using the goto here if there is no unwinding found within
> the error path? Either you've forgotten to add the unwinding or the
> goto is redundant.
>
> Repeat for all the functions with similar behavior found in this file.
I will drop the redundant 'goto err' and return the error code directly
across the entire file in v5.
>
>> +}
>> +
>> +static int __maybe_unused nau8360_suspend(struct snd_soc_component
>> *component)
>> +{
>> + struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component);
>> +
>> + regmap_update_bits(nau8360->regmap, NAU8360_R90_HW2_CTL0,
>> NAU8360_HW2_STALL,
>> + NAU8360_HW2_STALL);
>> + nau8360_dsp_enable(nau8360->regmap, false);
>> + regcache_cache_only(nau8360->regmap, true);
>> + regcache_mark_dirty(nau8360->regmap);
>> +
>> + return 0;
>> +}
>> +
>> +static int __maybe_unused nau8360_resume(struct snd_soc_component
>> *component)
>> +{
>> + struct nau8360 *nau8360 = snd_soc_component_get_drvdata(component);
>> + struct regmap *regmap = nau8360->regmap;
>> + int ret;
>> +
>> + regcache_cache_only(regmap, false);
>> + nau8360_peq_mem_enable(regmap, true);
>> + regcache_sync(regmap);
>> + nau8360_peq_mem_enable(regmap, false);
>> +
>> + /* disable Sense at standby */
>> + snd_soc_dapm_disable_pin(nau8360->dapm, "Sense");
>> + snd_soc_dapm_sync(nau8360->dapm);
>> +
>> + ret = nau8360_dsp_setup(component);
>> + if (ret)
>> + goto err;
>
> Drop the goto, no error handling here.
I will drop the redundant goto here in v5.
>
>> +
>> + return 0;
>> +err:
>> + return ret;
>> +}
>
> ...
>
>> +static int nau8360_reg_write(void *context, unsigned int reg,
>> unsigned int value)
>> +{
>> + struct i2c_client *client = context;
>> + int ret, count = 0;
>> + u8 buf[6];
>> +
>> + buf[count++] = reg >> 8;
>> + buf[count++] = reg & 0xff;
>> + if (reg != NAU8360_RF000_DSP_COMM && reg !=
>> NAU8360_RF002_DSP_COMM) {
>
> Refactor to positive a check. Positive checks are easier to follow
> and as long as there is no major impact on complexity of the code that
> follows, there is no reason to hurt readability.
I will refactor this to a positive check for better readability in v5.
>
>> + /* format for Codec, 2 bytes value and endian big */
>> + buf[count++] = value >> 8;
>> + buf[count++] = value & 0xff;
>> + dev_dbg(&client->dev, " %x <= %x", reg, value);
>> + } else {
>> + /* format for DSP, 4 bytes value and native */
>> + buf[count++] = value & 0xff;
>> + buf[count++] = (value >> 8) & 0xff;
>> + buf[count++] = (value >> 16) & 0xff;
>> + buf[count++] = (value >> 24) & 0xff;
>> + }
>> +
>> + ret = i2c_master_send(client, buf, count);
>> + if (ret == count)
>> + return 0;
>> + else if (ret < 0)
>> + return ret;
>> + else
>> + return -EIO;
>
> No need for 'else if', 'if' suffices. And the 'else' can be dropped.
I will change 'else if' to 'if' and drop the 'else' branches in v5.
>
>> +}
>
> ...
>
>> +static struct reg_default *nau8360_alloc_defaults(struct device
>> *dev, int *total_regs)
>> +{
>> + struct reg_default *dyn_defaults;
>> + int reg_num = ARRAY_SIZE(nau8360_reg_defaults);
>> + int total = reg_num + (2 * NAU8360_TOT_BAND_PER_CH *
>> NAU8360_TOT_BAND_COE);
>> + int i, j, idx;
>> +
>> + dyn_defaults = devm_kzalloc(dev, total * sizeof(*dyn_defaults),
>> GFP_KERNEL);
>> + if (!dyn_defaults)
>> + return NULL;
>> +
>> + memcpy(dyn_defaults, nau8360_reg_defaults, sizeof(*dyn_defaults)
>> * reg_num);
>> + idx = reg_num;
>> +
>> + for (i = 0; i < NAU8360_TOT_BAND_PER_CH; i++) {
>> + unsigned int l_base = NAU8360_R100_LEFT_BIQ0_COE +
>> + (i * NAU8360_TOT_BAND_COE_RANGE);
>> + unsigned int r_base = NAU8360_R200_RIGHT_BIQ0_COE +
>> + (i * NAU8360_TOT_BAND_COE_RANGE);
>
> Just add a local:
> unsigned int range = i * NAU8360_TOT_BAND_COE_RANGE;
> to simplify the code.
I will add this local variable to simplify duplicated arithmetic in v5.
>
>> +
>> + for (j = 0; j < NAU8360_TOT_BAND_COE; j++) {
>> + dyn_defaults[idx++].reg = l_base + j;
>> + dyn_defaults[idx++].reg = r_base + j;
>> + }
>> + }
>> +
>> + *total_regs = total;
>> +
>> + return dyn_defaults;
>> +}
>> +
>> +static int nau8360_i2c_probe(struct i2c_client *i2c)
>> +{
>> + struct device *dev = &i2c->dev;
>> + struct nau8360 *nau8360 = dev_get_platdata(dev);
>> + struct regmap_config regmap_cfg = nau8360_regmap_config;
>> + struct reg_default *dyn_defaults;
>> + int num_total_regs;
>> + int i, ret, value;
>> +
>> + if (!nau8360) {
>
> What? This seems redundant.
I will drop the dev_get_platdata() check in v5.
>
>> + nau8360 = devm_kzalloc(dev, sizeof(*nau8360), GFP_KERNEL);
>> + if (!nau8360)
>> + return -ENOMEM;
>> + }
>> + i2c_set_clientdata(i2c, nau8360);
>> + mutex_init(&nau8360->lock);
>> +
>> + dyn_defaults = nau8360_alloc_defaults(dev, &num_total_regs);
>> + if (!dyn_defaults)
>> + return -ENOMEM;
>> +
>> + regmap_cfg.reg_defaults = dyn_defaults;
>> + regmap_cfg.num_reg_defaults = num_total_regs;
>> +
>> + nau8360->regmap = devm_regmap_init(dev, NULL, i2c, ®map_cfg);
>> + if (IS_ERR(nau8360->regmap))
>> + return PTR_ERR(nau8360->regmap);
>> + nau8360->dev = dev;
>> +
>> + nau8360_reset_chip(nau8360->regmap);
>> + ret = regmap_read(nau8360->regmap, NAU8360_R46_I2C_DEVICE_ID,
>> &value);
>> + if (ret) {
>> + dev_err(dev, "Failed to read NAU83G60 device id %d",
>> + ret);
>
> No need for a new line here, you won't exceed the recommended char limit.
I will format this into a single line in v5.
>
>> + return ret;
>> + }
>> +
>> + for (i = 0; i < NAU8360_TDM_TXN; i++)
>> + nau8360->tdm_tx_func_slot[i] = TDM_SLOT_NONE;
>> + for (i = 0; i < NAU8360_TDM_RXN; i++)
>> + nau8360->tdm_rx_func_slot[i] = TDM_SLOT_NONE;
>> + nau8360->tdm_chan_len = 32;
>
> Either use constant or comment any use of hardcodes.
I will define a macro constant for this value in v5.
>
>> + ret = nau8360_read_device_properties(nau8360);
>> + if (ret)
>> + return ret;
>> +
>> + nau8360_print_device_properties(nau8360);
>> + nau8360_init_regs(nau8360);
>> +
>> + return devm_snd_soc_register_component(dev,
>> &soc_comp_dev_nau8360, &nau8360_dai, 1);
>> +}
>> +
>> +static const struct i2c_device_id nau8360_i2c_ids[] = {
>> + { "nau8360", 0 },
>> + { }
>
> Please match the style of existing entires. Checkout Mark's for-next
> to be up-to-date with recommended style or see commit 910714d4e79b
> ("ASoC: Use named initializers for arrays of i2c_device_data").
>
> [1]:
> https://patch.msgid.link/ae2ff4898eb340bd8bcafb7b75443eb4a0ce3e76.1778692164.git.u.kleine-koenig@b
> aylibre.com
I will update the array to use named initializers to match the current
standard in v5.
>
>> +};
>> +MODULE_DEVICE_TABLE(i2c, nau8360_i2c_ids);
>> +
>> +#ifdef CONFIG_OF
>> +static const struct of_device_id nau8360_of_ids[] = {
>> + { .compatible = "nuvoton,nau8360", },
>> + {}
>
> Ditto. Sidenote: you've used a different style then for the i2c table.
I will fix the style to be consistent in v5.
>
>> +};
>> +MODULE_DEVICE_TABLE(of, nau8360_of_ids);
>> +#endif
>> +
>> +#ifdef CONFIG_ACPI
>> +static const struct acpi_device_id nau8360_acpi_match[] = {
>
> struct acpi_device_id is available even if CONFIG_ACPI is disabled.
> Not sure if we even need preproc #ifdef here. Remove it and do some
> compilation checks.
I will remove the #ifdef wrapper and verify the build works with and
without CONFIG_ACPI in v5.
>
>> + {"NVTN2002", 0,},
>> + {},
>
> Ditto. Sidenote: you've used a different style then for the i2c and
> the of table.
I will fix the style to be consistent in v5.
>
>> +};
>> +MODULE_DEVICE_TABLE(acpi, nau8360_acpi_match);
>> +#endif
>> +
>> +static struct i2c_driver nau8360_i2c_driver = {
>> + .driver = {
>> + .name = "nau8360",
>> + .of_match_table = of_match_ptr(nau8360_of_ids),
>> + .acpi_match_table = ACPI_PTR(nau8360_acpi_match),
>
> Does this compile if I disable e.g.: CONFIG_ACPI ?
I will confirm the build works successfully with CONFIG_ACPI disabled in v5.
>
>> + },
>> + .probe = nau8360_i2c_probe,
>> + .id_table = nau8360_i2c_ids,
>> +};
>> +module_i2c_driver(nau8360_i2c_driver);
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
From: sashiko-bot @ 2026-06-22 6:15 UTC (permalink / raw)
To: Raviteja Laggyshetty; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260622-maili_icc-v1-1-0aa8286e6748@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing Compatible String / ID Space Collision for MMSS_NOC
--
commit 83d867b001ed2e53e22f1f16fa3aee0194837787
Author: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
Document the RPMh Network-On-Chip interconnect for the Qualcomm Maili SoC.
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml
> new file mode 100644
> index 0000000000000..3db8d8b23219f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml
[ ... ]
> +properties:
> + compatible:
> + enum:
[ ... ]
> + - qcom,maili-mc-virt
> + - qcom,maili-mmss-noc
> + - qcom,maili-nsp-noc
[ ... ]
> diff --git a/include/dt-bindings/interconnect/qcom,maili-rpmh.h b/include/dt-bindings/interconnect/qcom,maili-rpmh.h
> new file mode 100644
> index 0000000000000..e7a957a9d0f0e
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,maili-rpmh.h
[ ... ]
> +#define MASTER_CAMNOC_HF 0
> +#define MASTER_MDP 1
> +#define SLAVE_MNOC_HF_MEM_NOC 2
> +
> +#define MASTER_CAMNOC_NRT_ICP_SF 0
> +#define MASTER_CAMNOC_RT_CDM_SF 1
> +#define MASTER_CAMNOC_SF 2
[Severity: High]
Since both the HF and SF blocks start at index 0 in the header, but only a
single compatible string (qcom,maili-mmss-noc) is defined in the YAML schema
to represent the mmss domain, will this cause ID space collisions?
If the driver combines both sets of endpoints into a single mmss_noc_nodes[]
array using these overlapping 0-based indices:
static struct qcom_icc_node * const mmss_noc_nodes[] = {
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
[MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
...
};
won't the C compiler silently overwrite the HF nodes at indices 0, 1, and 2
with the SF nodes?
Does this mean the HF nodes will be lost from the driver's state, preventing
multimedia hardware from configuring its bandwidth?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260622-maili_icc-v1-0-0aa8286e6748@oss.qualcomm.com?part=1
^ permalink raw reply
* Re: [PATCH 2/2] interconnect: qcom: add Maili interconnect provider driver
From: sashiko-bot @ 2026-06-22 6:17 UTC (permalink / raw)
To: Raviteja Laggyshetty; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260622-maili_icc-v1-2-0aa8286e6748@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Overlapping array indices in `mmss_noc_nodes` due to unsequential DT binding macros.
- [Low] INTERCONNECT_QCOM_MAILI Kconfig entry deviates from standard subsystem patterns by missing architecture dependencies and improperly adding `default ARCH_QCOM`.
--
commit 8dd65bdb718ff52c61f92fb6eb9e65eee995529e
Author: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
interconnect: qcom: add Maili interconnect provider driver
Add driver for the Qualcomm interconnect buses found in Maili based platforms.
The topology consists of several NoCs that are controlled by a remote processor
that collects the aggregated bandwidth for each master-slave pairs.
> diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
> index 5b8a094ca4ede..5b57f111c63c0 100644
> --- a/drivers/interconnect/qcom/Kconfig
> +++ b/drivers/interconnect/qcom/Kconfig
> @@ -47,6 +47,16 @@ config INTERCONNECT_QCOM_KAANAPALI
> This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
> platforms.
>
> +config INTERCONNECT_QCOM_MAILI
> + tristate "Qualcomm MAILI interconnect driver"
> + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
> + select INTERCONNECT_QCOM_RPMH
> + select INTERCONNECT_QCOM_BCM_VOTER
> + default ARCH_QCOM
[Severity: Low]
Does this Kconfig definition miss the standard "depends on ARM64 || COMPILE_TEST"
constraint found in other Qualcomm interconnect drivers?
Also, by specifying "default ARCH_QCOM", does this unconditionally force the
driver to build on all Qualcomm targets rather than relying on defconfigs,
potentially causing unnecessary bloat?
> + help
> + This is a driver for the Qualcomm Network-on-Chip on maili-based
> + platforms.
> +
> config INTERCONNECT_QCOM_MSM8909
> tristate "Qualcomm MSM8909 interconnect driver"
> depends on INTERCONNECT_QCOM
[ ... ]
> diff --git a/drivers/interconnect/qcom/maili.c b/drivers/interconnect/qcom/maili.c
> new file mode 100644
> index 0000000000000..e5eed7f998f92
> --- /dev/null
> +++ b/drivers/interconnect/qcom/maili.c
[ ... ]
> +static struct qcom_icc_node * const mmss_noc_nodes[] = {
> + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
> + [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
> + [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
> + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
> + [MASTER_MDP] = &qnm_mdp,
> + [MASTER_MDSS_DCP] = &qnm_mdss_dcp,
[Severity: High]
Does mmss_noc_nodes[] have overlapping array indices due to how the
dt-bindings are defined?
Looking at dt-bindings/interconnect/qcom,maili-rpmh.h:
#define MASTER_CAMNOC_HF 0
#define MASTER_MDP 1
...
#define MASTER_CAMNOC_NRT_ICP_SF 0
#define MASTER_CAMNOC_RT_CDM_SF 1
#define MASTER_CAMNOC_SF 2
Because these macros share the same values, the later designated initializers
in mmss_noc_nodes[] will silently overwrite the earlier ones.
Does this unintentionally drop qnm_camnoc_hf, qnm_mdp, and qns_mem_noc_hf from
the provider array, breaking interconnect requests that target them?
> + [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
> + [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
> + [MASTER_VIDEO_EVA] = &qnm_video_eva,
> + [MASTER_VIDEO_MVP] = &qnm_video_mvp,
> + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
> + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
> + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260622-maili_icc-v1-0-0aa8286e6748@oss.qualcomm.com?part=2
^ permalink raw reply
* Re: [PATCH v4 2/2] clk: amlogic: Add A9 AO clock controller driver
From: Jian Hu @ 2026-06-22 6:19 UTC (permalink / raw)
To: Jerome Brunet, sashiko-bot
Cc: Jian Hu via B4 Relay, sashiko-reviews, linux-amlogic,
neil.armstrong, robh, devicetree, conor+dt
In-Reply-To: <1j33yjc7b9.fsf@starbuckisacylon.baylibre.com>
Hi Jerome,
Thanks for your review.
On 6/19/2026 3:34 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On jeu. 18 juin 2026 at 10:03, sashiko-bot@kernel.org wrote:
>
>> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
>> - [Medium] The AO PWM clocks are registered without an `ao_` or `a9_ao_`
>> prefix, which will cause global namespace collisions with the main clock
>> controller.
>> - [Low] Typographical error in the clock name string literal for the RTC
>> dualdiv input gate: `ao_rtc_duandiv_in` instead of `ao_rtc_dualdiv_in`.
>> - [Low] Missing `#include <linux/module.h>` for `MODULE_*` macros.
>> --
>>
>> commit ef5998ff087b6faed09d9eed4f59078d2b2f0a60
>> Author: Jian Hu <jian.hu@amlogic.com>
>>
>> clk: amlogic: Add A9 AO clock controller driver
>>
>> Add the Always-on clock controller driver for the Amlogic A9 SoC family.
>>
>>> diff --git a/drivers/clk/meson/a9-aoclk.c b/drivers/clk/meson/a9-aoclk.c
>>> new file mode 100644
>>> index 0000000000000..88aa8cf3f5d00
>>> --- /dev/null
>>> +++ b/drivers/clk/meson/a9-aoclk.c
>>> @@ -0,0 +1,488 @@
>>> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
>>> +/*
>>> + * Copyright (C) 2026 Amlogic, Inc. All rights reserved
>>> + */
>>> +
>>> +#include <dt-bindings/clock/amlogic,a9-aoclkc.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/platform_device.h>
>> [Severity: Low]
>> Should this file explicitly include <linux/module.h>?
>>
>> The file relies on several module macros at the end (such as MODULE_DESCRIPTION,
>> MODULE_AUTHOR, and MODULE_LICENSE). Although it currently compiles successfully
>> due to transitive includes from <linux/platform_device.h>, standard kernel
>> practice is to include the header explicitly.
> Yes please fix this
Ok, I will fix it in the next version.
>> [ ... ]
>>
>>> +static const struct clk_parent_data a9_ao_pwm_parents[] = {
>>> + { .hw = &a9_ao_xtal.hw },
>>> + { .fw_name = "fdiv5", },
>>> + { .fw_name = "fdiv4", },
>>> + { .fw_name = "fdiv3", }
>>> +};
>>> +
>>> +static A9_COMP_SEL(pwm_a, AO_PWM_CLK_A_CTRL, 9, 0x7, a9_ao_pwm_parents);
>> [Severity: Medium]
>> Will this cause a clock name collision with the main clock controller?
>>
>> Because the A9_COMP_SEL macro uses the #_name stringification operator inside
>> MESON_COMP_SEL, this will generate the clock name as exactly "pwm_a_sel"
>> (and similarly "pwm_a_div" and "pwm_a" for the others), without any "ao_" or
>> "a9_ao_" prefix.
> I think AI got it wrong and missed the prefix addition. Unless I missed
> something my self, I think you are fine here
Thanks for confirming. That was my understanding as well,
so I'll keep the current implementation unchanged.
>> If the main clock controller conventionally registers a "pwm_a" clock, failing
>> to prefix the Always-On clocks will lead to global namespace collisions in the
>> Common Clock Framework and debugfs.
>>
>>> +static A9_COMP_DIV(pwm_a, AO_PWM_CLK_A_CTRL, 0, 8);
>>> +static A9_COMP_GATE(pwm_a, AO_PWM_CLK_A_CTRL, 8);
>>> +
>>> +static A9_COMP_SEL(pwm_b, AO_PWM_CLK_B_CTRL, 9, 0x7, a9_ao_pwm_parents);
>> [ ... ]
>>
>>> +static struct clk_regmap a9_ao_rtc_dualdiv_in = {
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = AO_RTC_BY_OSCIN_CTRL0,
>>> + .bit_idx = 31,
>>> + },
>>> + .hw.init = &(struct clk_init_data) {
>>> + .name = "ao_rtc_duandiv_in",
>> [Severity: Low]
>> This isn't a bug, but there's a typo in the clock name literal. Should
>> "ao_rtc_duandiv_in" be "ao_rtc_dualdiv_in"?
> Yes
Ok, I will fix it in the next version.
>>> + .ops = &clk_regmap_gate_ops,
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &a9_ao_xtal.hw
>>> + },
> --
> Jerome
--
Jian
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: misc: add binding for Xilinx AXI-Stream FIFO
From: Aditya Chari S @ 2026-06-22 6:22 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh, krzk+dt, conor+dt, gregkh
Cc: jacobsfeder, devicetree, linux-staging, linux-kernel,
michal.simek, lucas.fariamo08
In-Reply-To: <37006444-95a7-41f1-a5a3-58d116c10c14@kernel.org>
On Mon, Jun 22, 2026, Krzysztof Kozlowski wrote:
> The main point is that driver is in staging, so we don't take bindings
> for it.
Understood, thanks for clarifying.
Regards,
Aditya
On Mon, Jun 22, 2026 at 10:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 22/06/2026 06:21, Aditya Chari S wrote:
> > Sorry about the pace - jumped from automated lint feedback straight to
> > a new version without waiting for an actual reviewer. Won't happen
> > again.
> >
> > On the staging binding question - I found the driver-removal thread
> > from June 2 and read through it. Michal Simek's reply makes clear this
> > driver isn't going anywhere (their networking team has plans that
> > depend on it), and that there's already an in-flight binding
> > conversion from Lucas Faria Mendes that he's actively tracking. I
> > wasn't aware of that series when I started this.
> >
> > Given that, I'll withdraw mine rather than duplicate work that's
> > already further along and already has the relevant maintainer's eyes
> > on it.
> >
>
> The main point is that driver is in staging, so we don't take bindings
> for it.
>
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH] arm64: dts: broadcom: bcm2712: Remove non-functional EL2 virtual timer
From: Marek Szyprowski @ 2026-06-22 6:20 UTC (permalink / raw)
To: Daniel Drake, Florian Fainelli, Marc Zyngier
Cc: robh, krzk+dt, conor+dt, bcm-kernel-feedback-list, devicetree,
linux-rpi-kernel, linux-arm-kernel, andrea.porta
In-Reply-To: <89a39670-c459-4467-a032-a965bc1dea6b@reactivated.net>
On 21.06.2026 22:58, Daniel Drake wrote:
> On 21/06/2026 21:03, Florian Fainelli wrote:
>> Daniel, do you happen to know which 2712 SoC revision you have, whether this is a C0 or D0 stepping?
>>
>> We have an internal bug tracker item pertaining exactly to the virtual timer interrupt connection however it affected a sister chip (77122) and not 2712 AFAICT, now checking with the design team whether the same happened on 2712.
> Thanks for looking into this! I am using Raspberry Pi 500 with D0 stepping.
>
Here it happens on one of the first shipped Raspberry Pi5, so probably C0 stepping.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH v2 0/2] interconnect: qcom: Add support for upcoming Maili SoC
From: Raviteja Laggyshetty @ 2026-06-22 6:34 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jingyi Wang
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel,
Raviteja Laggyshetty, Odelu Kukatla
Add interconnect bindings and RPMh-based interconnect driver support for
the upcoming Qualcomm Maili SoC.
Device tree changes are not part of this series, they will be posted
separately.
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
Changes in v2:
- Fix the incorrect endpoint ids in binding header. [Sashiko AI review]
- Link to v1: https://patch.msgid.link/20260622-maili_icc-v1-0-0aa8286e6748@oss.qualcomm.com
To: Georgi Djakov <djakov@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Raviteja Laggyshetty (2):
dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
interconnect: qcom: add Maili interconnect provider driver
.../bindings/interconnect/qcom,maili-rpmh.yaml | 127 ++
drivers/interconnect/qcom/Kconfig | 10 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/maili.c | 2091 ++++++++++++++++++++
include/dt-bindings/interconnect/qcom,maili-rpmh.h | 171 ++
5 files changed, 2401 insertions(+)
---
base-commit: 3ce97bd3c4f18608335e709c24d6a40e7036cab8
change-id: 20260622-maili_icc-94001df2a4d3
Best regards,
--
Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
From: Raviteja Laggyshetty @ 2026-06-22 6:34 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jingyi Wang
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel,
Raviteja Laggyshetty, Odelu Kukatla
In-Reply-To: <20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com>
Document the RPMh Network-On-Chip interconnect for the Qualcomm Maili
SoC.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
.../bindings/interconnect/qcom,maili-rpmh.yaml | 127 +++++++++++++++
include/dt-bindings/interconnect/qcom,maili-rpmh.h | 171 +++++++++++++++++++++
2 files changed, 298 insertions(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml
new file mode 100644
index 000000000000..3db8d8b23219
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,maili-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on Maili SoC
+
+maintainers:
+ - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also: include/dt-bindings/interconnect/qcom,maili-rpmh.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,maili-aggre-noc
+ - qcom,maili-clk-virt
+ - qcom,maili-cnoc-main
+ - qcom,maili-gem-noc
+ - qcom,maili-llclpi-noc
+ - qcom,maili-lpass-ag-noc
+ - qcom,maili-lpass-lpiaon-noc
+ - qcom,maili-lpass-lpicx-noc
+ - qcom,maili-mc-virt
+ - qcom,maili-mmss-noc
+ - qcom,maili-nsp-noc
+ - qcom,maili-pcie-anoc
+ - qcom,maili-stdst-cfg
+ - qcom,maili-stdst-main
+ - qcom,maili-system-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-clk-virt
+ - qcom,maili-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-aggre-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB3 PRIM AXI clock
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-pcie-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre-NOC PCIe AXI clock
+ - description: cfg-NOC PCIe a-NOC AHB clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,maili-aggre-noc
+ - qcom,maili-pcie-anoc
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ gem_noc: interconnect@31100000 {
+ compatible = "qcom,maili-gem-noc";
+ reg = <0x31100000 0x160200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre_noc: interconnect@f00000 {
+ compatible = "qcom,maili-aggre-noc";
+ reg = <0x00f00000 0x56200>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc_phy_axi_clk>,
+ <&gcc_prim_axi_clk>,
+ <&rpmhcc_ipa_clk>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,maili-rpmh.h b/include/dt-bindings/interconnect/qcom,maili-rpmh.h
new file mode 100644
index 000000000000..ae3e48b14eab
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,maili-rpmh.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MAILI_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_2 1
+#define MASTER_QUP_3 2
+#define MASTER_QUP_4 3
+#define MASTER_QUP_5 4
+#define MASTER_CRYPTO 5
+#define MASTER_IPA 6
+#define MASTER_QUP_1 7
+#define MASTER_SOCCP_PROC 8
+#define MASTER_QDSS_ETR 9
+#define MASTER_QDSS_ETR_1 10
+#define MASTER_SDCC_2 11
+#define MASTER_SDCC_4 12
+#define MASTER_UFS_MEM 13
+#define MASTER_USB3 14
+#define SLAVE_A1NOC_SNOC 15
+
+#define MASTER_DDR_EFF_VETO 0
+#define MASTER_QUP_CORE_0 1
+#define MASTER_QUP_CORE_1 2
+#define MASTER_QUP_CORE_2 3
+#define MASTER_QUP_CORE_3 4
+#define MASTER_QUP_CORE_4 5
+#define MASTER_QUP_CORE_5 6
+#define SLAVE_DDR_EFF_VETO 7
+#define SLAVE_QUP_CORE_0 8
+#define SLAVE_QUP_CORE_1 9
+#define SLAVE_QUP_CORE_2 10
+#define SLAVE_QUP_CORE_3 11
+#define SLAVE_QUP_CORE_4 12
+#define SLAVE_QUP_CORE_5 13
+
+#define MASTER_GEM_NOC_CNOC 0
+#define MASTER_GEM_NOC_PCIE_SNOC 1
+#define SLAVE_AOSS 2
+#define SLAVE_IPA_CFG 3
+#define SLAVE_IPC_ROUTER_FENCE 4
+#define SLAVE_SOCCP 5
+#define SLAVE_TME_CFG 6
+#define SLAVE_CNOC_CFG 7
+#define SLAVE_DDRSS_CFG 8
+#define SLAVE_IMEM 9
+#define SLAVE_PCIE_0 10
+#define SLAVE_PCIE_1 11
+
+#define MASTER_GIC 0
+#define MASTER_GPU_TCU 1
+#define MASTER_SYS_TCU 2
+#define MASTER_APPSS_PROC 3
+#define MASTER_GFX3D 4
+#define MASTER_LPASS_GEM_NOC 5
+#define MASTER_MSS_PROC 6
+#define MASTER_MNOC_HF_MEM_NOC 7
+#define MASTER_MNOC_SF_MEM_NOC 8
+#define MASTER_COMPUTE_NOC 9
+#define MASTER_ANOC_PCIE_GEM_NOC 10
+#define MASTER_QPACE 11
+#define MASTER_SNOC_SF_MEM_NOC 12
+#define MASTER_WLAN_Q6 13
+#define SLAVE_GEM_NOC_CNOC 14
+#define SLAVE_LLCC 15
+#define SLAVE_MEM_NOC_PCIE_SNOC 16
+
+#define MASTER_LPIAON_NOC_LLCLPI_NOC 0
+#define SLAVE_LPASS_LPI_CC 1
+#define SLAVE_LLCC_ISLAND 2
+#define SLAVE_SERVICE_LLCLPI_NOC 3
+#define SLAVE_SERVICE_LLCLPI_NOC_CHIPCX 4
+
+#define MASTER_LPIAON_NOC 0
+#define SLAVE_LPASS_GEM_NOC 1
+
+#define MASTER_LPASS_LPINOC 0
+#define SLAVE_LPIAON_NOC_LLCLPI_NOC 1
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 2
+
+#define MASTER_LPASS_PROC 0
+#define SLAVE_LPICX_NOC_LPIAON_NOC 1
+
+#define MASTER_LLCC 0
+#define MASTER_DDR_RT 1
+#define SLAVE_EBI1 2
+#define SLAVE_DDR_RT 3
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_CAMNOC_NRT_ICP_SF 1
+#define MASTER_CAMNOC_RT_CDM_SF 2
+#define MASTER_CAMNOC_SF 3
+#define MASTER_MDP 4
+#define MASTER_MDSS_DCP 5
+#define MASTER_CDSP_HCP 6
+#define MASTER_VIDEO_CV_PROC 7
+#define MASTER_VIDEO_EVA 8
+#define MASTER_VIDEO_MVP 9
+#define MASTER_VIDEO_V_PROC 10
+#define SLAVE_MNOC_HF_MEM_NOC 11
+#define SLAVE_MNOC_SF_MEM_NOC 12
+
+#define MASTER_CDSP_PROC 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_PCIE_ANOC_CFG 0
+#define MASTER_PCIE_0 1
+#define MASTER_PCIE_1 2
+#define SLAVE_ANOC_PCIE_GEM_NOC 3
+#define SLAVE_SERVICE_PCIE_ANOC 4
+
+#define MASTER_CFG_CENTER 0
+#define MASTER_CFG_EAST 1
+#define MASTER_CFG_MM_HF 2
+#define MASTER_CFG_MM_SF 3
+#define MASTER_CFG_NORTH 4
+#define MASTER_CFG_SOUTH 5
+#define MASTER_CFG_WEST 6
+#define SLAVE_AHB2PHY_SOUTH 7
+#define SLAVE_BOOT_ROM 8
+#define SLAVE_CAMERA_CFG 9
+#define SLAVE_CLK_CTL 10
+#define SLAVE_CRYPTO_CFG 11
+#define SLAVE_DISPLAY_CFG 12
+#define SLAVE_EVA_CFG 13
+#define SLAVE_GFX3D_CFG 14
+#define SLAVE_I2C 15
+#define SLAVE_IMEM_CFG 16
+#define SLAVE_IPC_ROUTER_CFG 17
+#define SLAVE_IRIS_CFG 18
+#define SLAVE_CNOC_MSS 19
+#define SLAVE_PCIE_0_CFG 20
+#define SLAVE_PCIE_1_CFG 21
+#define SLAVE_PRNG 22
+#define SLAVE_QSPI_0 23
+#define SLAVE_QUP_1 24
+#define SLAVE_QUP_2 25
+#define SLAVE_QUP_3 26
+#define SLAVE_QUP_4 27
+#define SLAVE_QUP_5 28
+#define SLAVE_SDCC_2 29
+#define SLAVE_SDCC_4 30
+#define SLAVE_TLMM 31
+#define SLAVE_UFS_MEM_CFG 32
+#define SLAVE_USB3 33
+#define SLAVE_VSENSE_CTRL_CFG 34
+#define SLAVE_PCIE_ANOC_CFG 35
+#define SLAVE_QDSS_CFG 36
+#define SLAVE_QDSS_STM 37
+#define SLAVE_TCSR 38
+#define SLAVE_TCU 39
+
+#define MASTER_CNOC_STARDUST 0
+#define SLAVE_STARDUST_CENTER_CFG 1
+#define SLAVE_STARDUST_EAST_CFG 2
+#define SLAVE_STARDUST_MM_HF_CFG 3
+#define SLAVE_STARDUST_MM_SF_CFG 4
+#define SLAVE_STARDUST_NORTH_CFG 5
+#define SLAVE_STARDUST_SOUTH_CFG 6
+#define SLAVE_STARDUST_WEST_CFG 7
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_APSS_NOC 1
+#define MASTER_CNOC_SNOC 2
+#define SLAVE_SNOC_GEM_NOC_SF 3
+
+#endif
--
2.43.0
^ permalink raw reply related
* [PATCH v2 2/2] interconnect: qcom: add Maili interconnect provider driver
From: Raviteja Laggyshetty @ 2026-06-22 6:34 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jingyi Wang
Cc: linux-arm-msm, linux-pm, devicetree, linux-kernel,
Raviteja Laggyshetty, Odelu Kukatla
In-Reply-To: <20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com>
Add driver for the Qualcomm interconnect buses found in Maili
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pairs.
Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
drivers/interconnect/qcom/Kconfig | 10 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/maili.c | 2091 ++++++++++++++++++++++++++++++++++++
3 files changed, 2103 insertions(+)
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 5b8a094ca4ed..5b57f111c63c 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -47,6 +47,16 @@ config INTERCONNECT_QCOM_KAANAPALI
This is a driver for the Qualcomm Network-on-Chip on kaanapali-based
platforms.
+config INTERCONNECT_QCOM_MAILI
+ tristate "Qualcomm MAILI interconnect driver"
+ depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
+ select INTERCONNECT_QCOM_RPMH
+ select INTERCONNECT_QCOM_BCM_VOTER
+ default ARCH_QCOM
+ help
+ This is a driver for the Qualcomm Network-on-Chip on maili-based
+ platforms.
+
config INTERCONNECT_QCOM_MSM8909
tristate "Qualcomm MSM8909 interconnect driver"
depends on INTERCONNECT_QCOM
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 1c7d410b40cc..5f139a370bbe 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -8,6 +8,7 @@ qnoc-eliza-objs := eliza.o
qnoc-glymur-objs := glymur.o
qnoc-hawi-objs := hawi.o
qnoc-kaanapali-objs := kaanapali.o
+qnoc-maili-objs := maili.o
qnoc-milos-objs := milos.o
qnoc-msm8909-objs := msm8909.o
qnoc-msm8916-objs := msm8916.o
@@ -56,6 +57,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_ELIZA) += qnoc-eliza.o
obj-$(CONFIG_INTERCONNECT_QCOM_GLYMUR) += qnoc-glymur.o
obj-$(CONFIG_INTERCONNECT_QCOM_HAWI) += qnoc-hawi.o
obj-$(CONFIG_INTERCONNECT_QCOM_KAANAPALI) += qnoc-kaanapali.o
+obj-$(CONFIG_INTERCONNECT_QCOM_MAILI) += qnoc-maili.o
obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) += qnoc-milos.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
diff --git a/drivers/interconnect/qcom/maili.c b/drivers/interconnect/qcom/maili.c
new file mode 100644
index 000000000000..e5eed7f998f9
--- /dev/null
+++ b/drivers/interconnect/qcom/maili.c
@@ -0,0 +1,2091 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <dt-bindings/interconnect/qcom,maili-rpmh.h>
+
+#include "bcm-voter.h"
+#include "icc-rpmh.h"
+
+static struct qcom_icc_node ddr_eff_veto_slave = {
+ .name = "ddr_eff_veto_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup1_core_slave = {
+ .name = "qup1_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup2_core_slave = {
+ .name = "qup2_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup3_core_slave = {
+ .name = "qup3_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup4_core_slave = {
+ .name = "qup4_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup5_core_slave = {
+ .name = "qup5_core_slave",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_aoss = {
+ .name = "qhs_aoss",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipa = {
+ .name = "qhs_ipa",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router_fence = {
+ .name = "qhs_ipc_router_fence",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_soccp = {
+ .name = "qhs_soccp",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tme_cfg = {
+ .name = "qhs_tme_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_ddrss_cfg = {
+ .name = "qss_ddrss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qxs_imem = {
+ .name = "qxs_imem",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie = {
+ .name = "xs_pcie",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node xs_pcie_g4x1 = {
+ .name = "xs_pcie_g4x1",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_lpi_cc = {
+ .name = "qhs_lpi_cc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qns_lb = {
+ .name = "qns_lb",
+ .channels = 4,
+ .buswidth = 16,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc = {
+ .name = "srvc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_llclpi_noc_chipcx = {
+ .name = "srvc_llclpi_noc_chipcx",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ebi = {
+ .name = "ebi",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node ddr_rt_slave = {
+ .name = "ddr_rt_slave",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node srvc_pcie_aggre_noc = {
+ .name = "srvc_pcie_aggre_noc",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ahb2phy0 = {
+ .name = "qhs_ahb2phy0",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_boot_rom = {
+ .name = "qhs_boot_rom",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_camera_cfg = {
+ .name = "qhs_camera_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_clk_ctl = {
+ .name = "qhs_clk_ctl",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_crypto_cfg = {
+ .name = "qhs_crypto_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_display_cfg = {
+ .name = "qhs_display_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_eva_cfg = {
+ .name = "qhs_eva_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_gpuss_cfg = {
+ .name = "qhs_gpuss_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node qhs_i2c = {
+ .name = "qhs_i2c",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_imem_cfg = {
+ .name = "qhs_imem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ipc_router = {
+ .name = "qhs_ipc_router",
+ .channels = 4,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_iris_cfg = {
+ .name = "qhs_iris_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_mss_cfg = {
+ .name = "qhs_mss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_cfg = {
+ .name = "qhs_pcie_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_pcie_g4x1_cfg = {
+ .name = "qhs_pcie_g4x1_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_prng = {
+ .name = "qhs_prng",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qspi = {
+ .name = "qhs_qspi",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup1 = {
+ .name = "qhs_qup1",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup2 = {
+ .name = "qhs_qup2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup3 = {
+ .name = "qhs_qup3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup4 = {
+ .name = "qhs_qup4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_qup5 = {
+ .name = "qhs_qup5",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc2 = {
+ .name = "qhs_sdc2",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_sdc4 = {
+ .name = "qhs_sdc4",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_tlmm = {
+ .name = "qhs_tlmm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_ufs_mem_cfg = {
+ .name = "qhs_ufs_mem_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_usb3 = {
+ .name = "qhs_usb3",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
+ .name = "qhs_vsense_ctrl_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_cfg = {
+ .name = "qss_qdss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_qdss_stm = {
+ .name = "qss_qdss_stm",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qss_tcsr = {
+ .name = "qss_tcsr",
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node xs_sys_tcu_cfg = {
+ .name = "xs_sys_tcu_cfg",
+ .channels = 1,
+ .buswidth = 8,
+};
+
+static struct qcom_icc_node ddr_eff_veto_master = {
+ .name = "ddr_eff_veto_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_node qup1_core_master = {
+ .name = "qup1_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_node qup2_core_master = {
+ .name = "qup2_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_node qup3_core_master = {
+ .name = "qup3_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_node qup4_core_master = {
+ .name = "qup4_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_node qup5_core_master = {
+ .name = "qup5_core_master",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qup5_core_slave },
+};
+
+static struct qcom_icc_node qnm_gemnoc_pcie = {
+ .name = "qnm_gemnoc_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 2,
+ .link_nodes = { &xs_pcie, &xs_pcie_g4x1 },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = {
+ .name = "qnm_lpiaon_noc_llclpi_noc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 4,
+ .link_nodes = { &qhs_lpi_cc, &qns_lb,
+ &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx },
+};
+
+static struct qcom_icc_node llcc_mc = {
+ .name = "llcc_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ebi },
+};
+
+static struct qcom_icc_node ddr_rt_mc = {
+ .name = "ddr_rt_mc",
+ .channels = 4,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_node qsm_pcie_anoc_cfg = {
+ .name = "qsm_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &srvc_pcie_aggre_noc },
+};
+
+static struct qcom_icc_node qsm_cfg_center = {
+ .name = "qsm_cfg_center",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 14,
+ .link_nodes = { &qhs_boot_rom, &qhs_clk_ctl,
+ &qhs_crypto_cfg, &qhs_gpuss_cfg,
+ &qhs_imem_cfg, &qhs_ipc_router,
+ &qhs_mss_cfg, &qhs_prng,
+ &qhs_tlmm, &qhs_vsense_ctrl_cfg,
+ &qss_qdss_cfg, &qss_qdss_stm,
+ &qss_tcsr, &xs_sys_tcu_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_east = {
+ .name = "qsm_cfg_east",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .link_nodes = { &qhs_qup2, &qhs_qup4 },
+};
+
+static struct qcom_icc_node qsm_cfg_mm_hf = {
+ .name = "qsm_cfg_mm_hf",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qhs_display_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_mm_sf = {
+ .name = "qsm_cfg_mm_sf",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 3,
+ .link_nodes = { &qhs_camera_cfg, &qhs_eva_cfg,
+ &qhs_iris_cfg },
+};
+
+static struct qcom_icc_node qsm_cfg_north = {
+ .name = "qsm_cfg_north",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 3,
+ .link_nodes = { &qhs_ahb2phy0, &qhs_ufs_mem_cfg,
+ &qhs_usb3 },
+};
+
+static struct qcom_icc_node qsm_cfg_west = {
+ .name = "qsm_cfg_west",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 2,
+ .link_nodes = { &qhs_qup1, &qhs_sdc2 },
+};
+
+static struct qcom_icc_node qns_llcc = {
+ .name = "qns_llcc",
+ .channels = 4,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &llcc_mc },
+};
+
+static struct qcom_icc_node qns_pcie = {
+ .name = "qns_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_pcie },
+};
+
+static struct qcom_icc_node qns_llc_lpinoc = {
+ .name = "qns_llc_lpinoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc_llclpi_noc },
+};
+
+static struct qcom_icc_node qss_pcie_anoc_cfg = {
+ .name = "qss_pcie_anoc_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_pcie_anoc_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_center_cfg = {
+ .name = "qss_stdst_center_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_center },
+};
+
+static struct qcom_icc_node qss_stdst_east_cfg = {
+ .name = "qss_stdst_east_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_east },
+};
+
+static struct qcom_icc_node qss_stdst_mm_hf_cfg = {
+ .name = "qss_stdst_mm_hf_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_mm_hf },
+};
+
+static struct qcom_icc_node qss_stdst_mm_sf_cfg = {
+ .name = "qss_stdst_mm_sf_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_mm_sf },
+};
+
+static struct qcom_icc_node qss_stdst_north_cfg = {
+ .name = "qss_stdst_north_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_north },
+};
+
+static struct qcom_icc_node qss_stdst_west_cfg = {
+ .name = "qss_stdst_west_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_west },
+};
+
+static struct qcom_icc_node alm_gic = {
+ .name = "alm_gic",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14d000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_qpace = {
+ .name = "qnm_qpace",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x153000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_node qsm_cfg_south = {
+ .name = "qsm_cfg_south",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 8,
+ .link_nodes = { &qhs_i2c, &qhs_pcie_cfg,
+ &qhs_pcie_g4x1_cfg, &qhs_qspi,
+ &qhs_qup3, &qhs_qup5,
+ &qhs_sdc4, &qss_pcie_anoc_cfg },
+};
+
+static struct qcom_icc_node qss_stdst_south_cfg = {
+ .name = "qss_stdst_south_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cfg_south },
+};
+
+static struct qcom_icc_node qsm_cnoc_main = {
+ .name = "qsm_cnoc_main",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 7,
+ .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg,
+ &qss_stdst_mm_hf_cfg, &qss_stdst_mm_sf_cfg,
+ &qss_stdst_north_cfg, &qss_stdst_south_cfg,
+ &qss_stdst_west_cfg },
+};
+
+static struct qcom_icc_node qss_cfg = {
+ .name = "qss_cfg",
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .link_nodes = { &qsm_cnoc_main },
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+ .name = "qnm_gemnoc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 8,
+ .link_nodes = { &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem },
+};
+
+static struct qcom_icc_node qns_gem_noc_cnoc = {
+ .name = "qns_gem_noc_cnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_gemnoc_cnoc },
+};
+
+static struct qcom_icc_node alm_gpu_tcu = {
+ .name = "alm_gpu_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x145000 },
+ .prio = 1,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node alm_sys_tcu = {
+ .name = "alm_sys_tcu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x147000 },
+ .prio = 6,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node chm_apps = {
+ .name = "chm_apps",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_gpu = {
+ .name = "qnm_gpu",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x51000, 0xd1000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_lpass_gemnoc = {
+ .name = "qnm_lpass_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x149000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mdsp = {
+ .name = "qnm_mdsp",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_hf = {
+ .name = "qnm_mnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x55000, 0xd5000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_mnoc_sf = {
+ .name = "qnm_mnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x57000, 0xd7000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_nsp_gemnoc = {
+ .name = "qnm_nsp_gemnoc",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x59000, 0xd9000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_pcie = {
+ .name = "qnm_pcie",
+ .channels = 1,
+ .buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14b000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 2,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+ .name = "qnm_snoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x14f000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qnm_wlan_q6 = {
+ .name = "qnm_wlan_q6",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 3,
+ .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
+ .name = "qns_lpass_ag_noc_gemnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_gemnoc },
+};
+
+static struct qcom_icc_node qns_mem_noc_hf = {
+ .name = "qns_mem_noc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_hf },
+};
+
+static struct qcom_icc_node qns_mem_noc_sf = {
+ .name = "qns_mem_noc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_mnoc_sf },
+};
+
+static struct qcom_icc_node qns_nsp_gemnoc = {
+ .name = "qns_nsp_gemnoc",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_nsp_gemnoc },
+};
+
+static struct qcom_icc_node qns_pcie_gemnoc = {
+ .name = "qns_pcie_gemnoc",
+ .channels = 1,
+ .buswidth = 16,
+ .num_links = 1,
+ .link_nodes = { &qnm_pcie },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+ .name = "qns_gemnoc_sf",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_snoc_sf },
+};
+
+static struct qcom_icc_node qnm_lpiaon_noc = {
+ .name = "qnm_lpiaon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpass_ag_noc_gemnoc },
+};
+
+static struct qcom_icc_node qnm_camnoc_hf = {
+ .name = "qnm_camnoc_hf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x50000, 0x51000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_mdp = {
+ .name = "qnm_mdp",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x52000, 0x53000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = {
+ .name = "qnm_camnoc_nrt_icp_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x20000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = {
+ .name = "qnm_camnoc_rt_cdm_sf",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x28000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_camnoc_sf = {
+ .name = "qnm_camnoc_sf",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x21000, 0x22000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_mdss_dcp = {
+ .name = "qnm_mdss_dcp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x29000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_vapss_hcp = {
+ .name = "qnm_vapss_hcp",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_cv_cpu = {
+ .name = "qnm_video_cv_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x24000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_eva = {
+ .name = "qnm_video_eva",
+ .channels = 2,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 2,
+ .port_offsets = { 0x25000, 0x26000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_mvp = {
+ .name = "qnm_video_mvp",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x23000 },
+ .prio = 0,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_video_v_cpu = {
+ .name = "qnm_video_v_cpu",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x27000 },
+ .prio = 4,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_node qnm_nsp = {
+ .name = "qnm_nsp",
+ .channels = 2,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie = {
+ .name = "xm_pcie",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xc000 },
+ .prio = 3,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node xm_pcie_g4x1 = {
+ .name = "xm_pcie_g4x1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0xd000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_node qnm_aggre_noc = {
+ .name = "qnm_aggre_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x20000 },
+ .prio = 2,
+ .urg_fwd = 1,
+ .prio_fwd_disable = 0,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_apss_noc = {
+ .name = "qnm_apss_noc",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1e000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qnm_cnoc_data = {
+ .name = "qnm_cnoc_data",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x1f000 },
+ .prio = 2,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_node qns_a1noc_snoc = {
+ .name = "qns_a1noc_snoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_node qns_lpass_aggnoc = {
+ .name = "qns_lpass_aggnoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpiaon_noc },
+};
+
+static struct qcom_icc_node qhm_qspi = {
+ .name = "qhm_qspi",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x49000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup2 = {
+ .name = "qhm_qup2",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x48000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup3 = {
+ .name = "qhm_qup3",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x46000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup4 = {
+ .name = "qhm_qup4",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x47000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qhm_qup5 = {
+ .name = "qhm_qup5",
+ .channels = 1,
+ .buswidth = 4,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4e000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_crypto = {
+ .name = "qxm_crypto",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x40000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_ipa = {
+ .name = "qxm_ipa",
+ .channels = 1,
+ .buswidth = 16,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x41000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_qup1 = {
+ .name = "qxm_qup1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4d000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qxm_soccp = {
+ .name = "qxm_soccp",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x45000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_0 = {
+ .name = "xm_qdss_etr_0",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x42000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_qdss_etr_1 = {
+ .name = "xm_qdss_etr_1",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x43000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc2 = {
+ .name = "xm_sdc2",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x44000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_sdc4 = {
+ .name = "xm_sdc4",
+ .channels = 1,
+ .buswidth = 8,
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_ufs_mem = {
+ .name = "xm_ufs_mem",
+ .channels = 1,
+ .buswidth = 32,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4b000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node xm_usb3 = {
+ .name = "xm_usb3",
+ .channels = 1,
+ .buswidth = 8,
+ .qosbox = &(const struct qcom_icc_qosbox) {
+ .num_ports = 1,
+ .port_offsets = { 0x4c000 },
+ .prio = 0,
+ .urg_fwd = 0,
+ .prio_fwd_disable = 1,
+ },
+ .num_links = 1,
+ .link_nodes = { &qns_a1noc_snoc },
+};
+
+static struct qcom_icc_node qnm_lpass_lpinoc = {
+ .name = "qnm_lpass_lpinoc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 2,
+ .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_node qns_lpi_aon_noc = {
+ .name = "qns_lpi_aon_noc",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qnm_lpass_lpinoc },
+};
+
+static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = {
+ .name = "qnm_lpinoc_dsp_qns4m",
+ .channels = 1,
+ .buswidth = 32,
+ .num_links = 1,
+ .link_nodes = { &qns_lpi_aon_noc },
+};
+
+static struct qcom_icc_bcm bcm_acv = {
+ .name = "ACV",
+ .enable_mask = BIT(3),
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_ce0 = {
+ .name = "CE0",
+ .num_nodes = 1,
+ .nodes = { &qxm_crypto },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+ .name = "CN0",
+ .enable_mask = BIT(0),
+ .keepalive = true,
+ .num_nodes = 25,
+ .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
+ &qhs_aoss, &qhs_ipa,
+ &qhs_ipc_router_fence, &qhs_soccp,
+ &qhs_tme_cfg, &qss_cfg,
+ &qss_ddrss_cfg, &qxs_imem,
+ &xs_pcie, &xs_pcie_g4x1,
+ &qsm_cfg_center, &qsm_cfg_east,
+ &qsm_cfg_mm_hf, &qsm_cfg_mm_sf,
+ &qsm_cfg_north, &qsm_cfg_south,
+ &qsm_cfg_west, &qhs_ahb2phy0,
+ &qhs_boot_rom, &qhs_camera_cfg,
+ &qhs_clk_ctl, &qhs_crypto_cfg,
+ &qhs_eva_cfg },
+};
+
+static struct qcom_icc_bcm bcm_cn1 = {
+ .name = "CN1",
+ .num_nodes = 6,
+ .nodes = { &qhs_display_cfg, &qhs_qup1,
+ &qhs_qup2, &qhs_qup3,
+ &qhs_qup4, &qhs_qup5 },
+};
+
+static struct qcom_icc_bcm bcm_co0 = {
+ .name = "CO0",
+ .enable_mask = BIT(0),
+ .num_nodes = 2,
+ .nodes = { &qnm_nsp, &qns_nsp_gemnoc },
+};
+
+static struct qcom_icc_bcm bcm_de0 = {
+ .name = "DE0",
+ .enable_mask = BIT(0),
+ .num_nodes = 1,
+ .nodes = { &ddr_eff_veto_slave },
+};
+
+static struct qcom_icc_bcm bcm_lp0 = {
+ .name = "LP0",
+ .num_nodes = 5,
+ .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb,
+ &qnm_lpass_lpinoc, &qns_llc_lpinoc,
+ &qns_lpass_aggnoc },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+ .name = "MC0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_mc5 = {
+ .name = "MC5",
+ .num_nodes = 1,
+ .nodes = { &ddr_rt_slave },
+};
+
+static struct qcom_icc_bcm bcm_mm0 = {
+ .name = "MM0",
+ .num_nodes = 1,
+ .nodes = { &qns_mem_noc_hf },
+};
+
+static struct qcom_icc_bcm bcm_mm1 = {
+ .name = "MM1",
+ .enable_mask = BIT(0),
+ .num_nodes = 9,
+ .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf,
+ &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf,
+ &qnm_vapss_hcp, &qnm_video_cv_cpu,
+ &qnm_video_mvp, &qnm_video_v_cpu,
+ &qns_mem_noc_sf },
+};
+
+static struct qcom_icc_bcm bcm_qpc0 = {
+ .name = "QPC0",
+ .num_nodes = 1,
+ .nodes = { &qnm_qpace },
+};
+
+static struct qcom_icc_bcm bcm_qup0 = {
+ .name = "QUP0",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup0_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup1 = {
+ .name = "QUP1",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup1_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup2 = {
+ .name = "QUP2",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup2_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup3 = {
+ .name = "QUP3",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup3_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup4 = {
+ .name = "QUP4",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup4_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_qup5 = {
+ .name = "QUP5",
+ .vote_scale = 1,
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qup5_core_slave },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+ .name = "SH0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh1 = {
+ .name = "SH1",
+ .enable_mask = BIT(0),
+ .num_nodes = 15,
+ .nodes = { &alm_gic, &alm_gpu_tcu,
+ &alm_sys_tcu, &chm_apps,
+ &qnm_gpu, &qnm_lpass_gemnoc,
+ &qnm_mdsp, &qnm_mnoc_hf,
+ &qnm_mnoc_sf, &qnm_nsp_gemnoc,
+ &qnm_pcie, &qnm_snoc_sf,
+ &qnm_wlan_q6, &qns_gem_noc_cnoc,
+ &qns_pcie },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+ .name = "SN0",
+ .keepalive = true,
+ .num_nodes = 1,
+ .nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sn2 = {
+ .name = "SN2",
+ .num_nodes = 1,
+ .nodes = { &qnm_aggre_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn3 = {
+ .name = "SN3",
+ .num_nodes = 1,
+ .nodes = { &qns_pcie_gemnoc },
+};
+
+static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
+ &bcm_ce0,
+};
+
+static struct qcom_icc_node * const aggre1_noc_nodes[] = {
+ [MASTER_QSPI_0] = &qhm_qspi,
+ [MASTER_QUP_2] = &qhm_qup2,
+ [MASTER_QUP_3] = &qhm_qup3,
+ [MASTER_QUP_4] = &qhm_qup4,
+ [MASTER_QUP_5] = &qhm_qup5,
+ [MASTER_CRYPTO] = &qxm_crypto,
+ [MASTER_IPA] = &qxm_ipa,
+ [MASTER_QUP_1] = &qxm_qup1,
+ [MASTER_SOCCP_PROC] = &qxm_soccp,
+ [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
+ [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
+ [MASTER_SDCC_2] = &xm_sdc2,
+ [MASTER_SDCC_4] = &xm_sdc4,
+ [MASTER_UFS_MEM] = &xm_ufs_mem,
+ [MASTER_USB3] = &xm_usb3,
+ [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+};
+
+static const struct regmap_config maili_aggre1_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x56200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_aggre1_noc = {
+ .config = &maili_aggre1_noc_regmap_config,
+ .nodes = aggre1_noc_nodes,
+ .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+ .bcms = aggre1_noc_bcms,
+ .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const clk_virt_bcms[] = {
+ &bcm_de0,
+ &bcm_qup0,
+ &bcm_qup1,
+ &bcm_qup2,
+ &bcm_qup3,
+ &bcm_qup4,
+ &bcm_qup5,
+};
+
+static struct qcom_icc_node * const clk_virt_nodes[] = {
+ [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master,
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [MASTER_QUP_CORE_1] = &qup1_core_master,
+ [MASTER_QUP_CORE_2] = &qup2_core_master,
+ [MASTER_QUP_CORE_3] = &qup3_core_master,
+ [MASTER_QUP_CORE_4] = &qup4_core_master,
+ [MASTER_QUP_CORE_5] = &qup5_core_master,
+ [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+ [SLAVE_QUP_CORE_1] = &qup1_core_slave,
+ [SLAVE_QUP_CORE_2] = &qup2_core_slave,
+ [SLAVE_QUP_CORE_3] = &qup3_core_slave,
+ [SLAVE_QUP_CORE_4] = &qup4_core_slave,
+ [SLAVE_QUP_CORE_5] = &qup5_core_slave,
+};
+
+static const struct qcom_icc_desc maili_clk_virt = {
+ .nodes = clk_virt_nodes,
+ .num_nodes = ARRAY_SIZE(clk_virt_nodes),
+ .bcms = clk_virt_bcms,
+ .num_bcms = ARRAY_SIZE(clk_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
+ &bcm_cn0,
+};
+
+static struct qcom_icc_node * const cnoc_main_nodes[] = {
+ [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+ [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
+ [SLAVE_AOSS] = &qhs_aoss,
+ [SLAVE_IPA_CFG] = &qhs_ipa,
+ [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence,
+ [SLAVE_SOCCP] = &qhs_soccp,
+ [SLAVE_TME_CFG] = &qhs_tme_cfg,
+ [SLAVE_CNOC_CFG] = &qss_cfg,
+ [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
+ [SLAVE_IMEM] = &qxs_imem,
+ [SLAVE_PCIE_0] = &xs_pcie,
+ [SLAVE_PCIE_1] = &xs_pcie_g4x1,
+};
+
+static const struct regmap_config maili_cnoc_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_cnoc_main = {
+ .config = &maili_cnoc_main_regmap_config,
+ .nodes = cnoc_main_nodes,
+ .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
+ .bcms = cnoc_main_bcms,
+ .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
+};
+
+static struct qcom_icc_bcm * const gem_noc_bcms[] = {
+ &bcm_qpc0,
+ &bcm_sh0,
+ &bcm_sh1,
+};
+
+static struct qcom_icc_node * const gem_noc_nodes[] = {
+ [MASTER_GIC] = &alm_gic,
+ [MASTER_GPU_TCU] = &alm_gpu_tcu,
+ [MASTER_SYS_TCU] = &alm_sys_tcu,
+ [MASTER_APPSS_PROC] = &chm_apps,
+ [MASTER_GFX3D] = &qnm_gpu,
+ [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
+ [MASTER_MSS_PROC] = &qnm_mdsp,
+ [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
+ [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
+ [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
+ [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
+ [MASTER_QPACE] = &qnm_qpace,
+ [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+ [MASTER_WLAN_Q6] = &qnm_wlan_q6,
+ [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+ [SLAVE_LLCC] = &qns_llcc,
+ [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
+};
+
+static const struct regmap_config maili_gem_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x160200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_gem_noc = {
+ .config = &maili_gem_noc_regmap_config,
+ .nodes = gem_noc_nodes,
+ .num_nodes = ARRAY_SIZE(gem_noc_nodes),
+ .bcms = gem_noc_bcms,
+ .num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const llclpi_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const llclpi_noc_nodes[] = {
+ [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc,
+ [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc,
+ [SLAVE_LLCC_ISLAND] = &qns_lb,
+ [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc,
+ [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx,
+};
+
+static const struct regmap_config maili_llclpi_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x17200,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_llclpi_noc = {
+ .config = &maili_llclpi_noc_regmap_config,
+ .nodes = llclpi_noc_nodes,
+ .num_nodes = ARRAY_SIZE(llclpi_noc_nodes),
+ .bcms = llclpi_noc_bcms,
+ .num_bcms = ARRAY_SIZE(llclpi_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
+ [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
+ [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
+};
+
+static const struct regmap_config maili_lpass_ag_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xc080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_lpass_ag_noc = {
+ .config = &maili_lpass_ag_noc_regmap_config,
+ .nodes = lpass_ag_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
+ &bcm_lp0,
+};
+
+static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
+ [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
+ [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc,
+ [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
+};
+
+static const struct regmap_config maili_lpass_lpiaon_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x19080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_lpass_lpiaon_noc = {
+ .config = &maili_lpass_lpiaon_noc_regmap_config,
+ .nodes = lpass_lpiaon_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
+ .bcms = lpass_lpiaon_noc_bcms,
+ .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
+};
+
+static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
+ [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m,
+ [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
+};
+
+static const struct regmap_config maili_lpass_lpicx_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x46080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_lpass_lpicx_noc = {
+ .config = &maili_lpass_lpicx_noc_regmap_config,
+ .nodes = lpass_lpicx_noc_nodes,
+ .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
+};
+
+static struct qcom_icc_bcm * const mc_virt_bcms[] = {
+ &bcm_acv,
+ &bcm_mc0,
+ &bcm_mc5,
+};
+
+static struct qcom_icc_node * const mc_virt_nodes[] = {
+ [MASTER_LLCC] = &llcc_mc,
+ [MASTER_DDR_RT] = &ddr_rt_mc,
+ [SLAVE_EBI1] = &ebi,
+ [SLAVE_DDR_RT] = &ddr_rt_slave,
+};
+
+static const struct qcom_icc_desc maili_mc_virt = {
+ .nodes = mc_virt_nodes,
+ .num_nodes = ARRAY_SIZE(mc_virt_nodes),
+ .bcms = mc_virt_bcms,
+ .num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
+ &bcm_mm0,
+ &bcm_mm1,
+};
+
+static struct qcom_icc_node * const mmss_noc_nodes[] = {
+ [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
+ [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf,
+ [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf,
+ [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
+ [MASTER_MDP] = &qnm_mdp,
+ [MASTER_MDSS_DCP] = &qnm_mdss_dcp,
+ [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
+ [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
+ [MASTER_VIDEO_EVA] = &qnm_video_eva,
+ [MASTER_VIDEO_MVP] = &qnm_video_mvp,
+ [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
+ [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
+ [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
+};
+
+static const struct regmap_config maili_mmss_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5f800,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_mmss_noc = {
+ .config = &maili_mmss_noc_regmap_config,
+ .nodes = mmss_noc_nodes,
+ .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
+ .bcms = mmss_noc_bcms,
+ .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
+ &bcm_co0,
+};
+
+static struct qcom_icc_node * const nsp_noc_nodes[] = {
+ [MASTER_CDSP_PROC] = &qnm_nsp,
+ [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
+};
+
+static const struct regmap_config maili_nsp_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x21280,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_nsp_noc = {
+ .config = &maili_nsp_noc_regmap_config,
+ .nodes = nsp_noc_nodes,
+ .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
+ .bcms = nsp_noc_bcms,
+ .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
+ &bcm_sn3,
+};
+
+static struct qcom_icc_node * const pcie_anoc_nodes[] = {
+ [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
+ [MASTER_PCIE_0] = &xm_pcie,
+ [MASTER_PCIE_1] = &xm_pcie_g4x1,
+ [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
+ [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
+};
+
+static const struct regmap_config maili_pcie_anoc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x12400,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_pcie_anoc = {
+ .config = &maili_pcie_anoc_regmap_config,
+ .nodes = pcie_anoc_nodes,
+ .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
+ .bcms = pcie_anoc_bcms,
+ .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
+ .qos_requires_clocks = true,
+};
+
+static struct qcom_icc_bcm * const stdst_cfg_bcms[] = {
+ &bcm_cn0,
+ &bcm_cn1,
+};
+
+static struct qcom_icc_node * const stdst_cfg_nodes[] = {
+ [MASTER_CFG_CENTER] = &qsm_cfg_center,
+ [MASTER_CFG_EAST] = &qsm_cfg_east,
+ [MASTER_CFG_MM_HF] = &qsm_cfg_mm_hf,
+ [MASTER_CFG_MM_SF] = &qsm_cfg_mm_sf,
+ [MASTER_CFG_NORTH] = &qsm_cfg_north,
+ [MASTER_CFG_SOUTH] = &qsm_cfg_south,
+ [MASTER_CFG_WEST] = &qsm_cfg_west,
+ [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
+ [SLAVE_BOOT_ROM] = &qhs_boot_rom,
+ [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
+ [SLAVE_CLK_CTL] = &qhs_clk_ctl,
+ [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg,
+ [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
+ [SLAVE_EVA_CFG] = &qhs_eva_cfg,
+ [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
+ [SLAVE_I2C] = &qhs_i2c,
+ [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
+ [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
+ [SLAVE_IRIS_CFG] = &qhs_iris_cfg,
+ [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
+ [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg,
+ [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg,
+ [SLAVE_PRNG] = &qhs_prng,
+ [SLAVE_QSPI_0] = &qhs_qspi,
+ [SLAVE_QUP_1] = &qhs_qup1,
+ [SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_QUP_3] = &qhs_qup3,
+ [SLAVE_QUP_4] = &qhs_qup4,
+ [SLAVE_QUP_5] = &qhs_qup5,
+ [SLAVE_SDCC_2] = &qhs_sdc2,
+ [SLAVE_SDCC_4] = &qhs_sdc4,
+ [SLAVE_TLMM] = &qhs_tlmm,
+ [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+ [SLAVE_USB3] = &qhs_usb3,
+ [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
+ [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
+ [SLAVE_QDSS_CFG] = &qss_qdss_cfg,
+ [SLAVE_QDSS_STM] = &qss_qdss_stm,
+ [SLAVE_TCSR] = &qss_tcsr,
+ [SLAVE_TCU] = &xs_sys_tcu_cfg,
+};
+
+static const struct regmap_config maili_stdst_cfg_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x9000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_stdst_cfg = {
+ .config = &maili_stdst_cfg_regmap_config,
+ .nodes = stdst_cfg_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_cfg_nodes),
+ .bcms = stdst_cfg_bcms,
+ .num_bcms = ARRAY_SIZE(stdst_cfg_bcms),
+};
+
+static struct qcom_icc_node * const stdst_main_nodes[] = {
+ [MASTER_CNOC_STARDUST] = &qsm_cnoc_main,
+ [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg,
+ [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg,
+ [SLAVE_STARDUST_MM_HF_CFG] = &qss_stdst_mm_hf_cfg,
+ [SLAVE_STARDUST_MM_SF_CFG] = &qss_stdst_mm_sf_cfg,
+ [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg,
+ [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg,
+ [SLAVE_STARDUST_WEST_CFG] = &qss_stdst_west_cfg,
+};
+
+static const struct regmap_config maili_stdst_main_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xf9000,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_stdst_main = {
+ .config = &maili_stdst_main_regmap_config,
+ .nodes = stdst_main_nodes,
+ .num_nodes = ARRAY_SIZE(stdst_main_nodes),
+};
+
+static struct qcom_icc_bcm * const system_noc_bcms[] = {
+ &bcm_sn0,
+ &bcm_sn2,
+};
+
+static struct qcom_icc_node * const system_noc_nodes[] = {
+ [MASTER_A1NOC_SNOC] = &qnm_aggre_noc,
+ [MASTER_APSS_NOC] = &qnm_apss_noc,
+ [MASTER_CNOC_SNOC] = &qnm_cnoc_data,
+ [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+};
+
+static const struct regmap_config maili_system_noc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x20080,
+ .fast_io = true,
+};
+
+static const struct qcom_icc_desc maili_system_noc = {
+ .config = &maili_system_noc_regmap_config,
+ .nodes = system_noc_nodes,
+ .num_nodes = ARRAY_SIZE(system_noc_nodes),
+ .bcms = system_noc_bcms,
+ .num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static const struct of_device_id qnoc_of_match[] = {
+ { .compatible = "qcom,maili-aggre-noc", .data = &maili_aggre1_noc },
+ { .compatible = "qcom,maili-clk-virt", .data = &maili_clk_virt },
+ { .compatible = "qcom,maili-cnoc-main", .data = &maili_cnoc_main },
+ { .compatible = "qcom,maili-gem-noc", .data = &maili_gem_noc },
+ { .compatible = "qcom,maili-llclpi-noc", .data = &maili_llclpi_noc },
+ { .compatible = "qcom,maili-lpass-ag-noc", .data = &maili_lpass_ag_noc },
+ { .compatible = "qcom,maili-lpass-lpiaon-noc", .data = &maili_lpass_lpiaon_noc },
+ { .compatible = "qcom,maili-lpass-lpicx-noc", .data = &maili_lpass_lpicx_noc },
+ { .compatible = "qcom,maili-mc-virt", .data = &maili_mc_virt },
+ { .compatible = "qcom,maili-mmss-noc", .data = &maili_mmss_noc },
+ { .compatible = "qcom,maili-nsp-noc", .data = &maili_nsp_noc },
+ { .compatible = "qcom,maili-pcie-anoc", .data = &maili_pcie_anoc },
+ { .compatible = "qcom,maili-stdst-cfg", .data = &maili_stdst_cfg },
+ { .compatible = "qcom,maili-stdst-main", .data = &maili_stdst_main },
+ { .compatible = "qcom,maili-system-noc", .data = &maili_system_noc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, qnoc_of_match);
+
+static struct platform_driver qnoc_driver = {
+ .probe = qcom_icc_rpmh_probe,
+ .remove = qcom_icc_rpmh_remove,
+ .driver = {
+ .name = "qnoc-maili",
+ .of_match_table = qnoc_of_match,
+ .sync_state = icc_sync_state,
+ },
+};
+
+static int __init qnoc_driver_init(void)
+{
+ return platform_driver_register(&qnoc_driver);
+}
+core_initcall(qnoc_driver_init);
+
+static void __exit qnoc_driver_exit(void)
+{
+ platform_driver_unregister(&qnoc_driver);
+}
+module_exit(qnoc_driver_exit);
+
+MODULE_DESCRIPTION("Qualcomm Maili NoC driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related
* RE: [PATCH v2 1/7] ASoC: dt-bindings: ES8389: Add members about HPF and clock
From: Zhang Yi @ 2026-06-22 6:33 UTC (permalink / raw)
To: broonie; +Cc: conor+dt, devicetree, krzk+dt, linux-sound, robh, tiwai, zhangyi
In-Reply-To: <a619312f-55b8-41f4-b288-d7c343f5f9e9@sirena.org.uk>
> > + everest,mclk-src:
> > + $ref: /schemas/types.yaml#/definitions/uint8
> > + description:
> > + Indicates that SCLK is used as the internal clock.
> > + minimum: 0
> > + maximum: 0x01
> > + default: 0x00
>
> Could this be done by having a clock API property for the MCLK source
> and then falling back to using SCLK if that's absent? That would feel
> more natural for DT, and you'll probably want the MCLK property at some
> point. It's also a bit more of a neutral description of the hardware,
> future versions might switch dynamically between MCLK or SCLK based on
> some criteria or something.
I'm not quite sure what you mean.
Does the implementation below match what you described?
clocks:
items:
- description: clock for master clock (MCLK)
clock-names:
items:
- const: mclk
es8389->mclk = devm_clk_get_optional(component->dev, "mclk");
if (IS_ERR(es8389->mclk))
es8389->mclk_src = ES8389_SCLK_PIN;
> > + everest,hpf-frq:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + The frequency of HPF in Hz.
> > + maximum: 1020
> > + default: 16
>
> Why configure this with a fixed value in the DT - it's the sort of thing
> I'd expect to turn up as an ALSA control so the user can vary it at
> runtime if they want to?
I don't want users to be able to change the HPF value at any time,
as this would affect the codec's startup.
Or I can use SOC_SINGLE_EXT to define HPF-related controls
and write the modified values to cache when writing to the hardware is not permitted.
^ permalink raw reply
* Re: [PATCH v10 1/4] dt-bindings: clock: imx95-blk-ctl: Use single quotes consistently
From: Krzysztof Kozlowski @ 2026-06-22 6:39 UTC (permalink / raw)
To: guoniu.zhou
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Laurent Pinchart, Frank Li, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, imx, linux-media, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, Guoniu Zhou
In-Reply-To: <20260618-csi_formatter-v10-1-f23830312ba5@oss.nxp.com>
On Thu, Jun 18, 2026 at 05:41:35PM +0800, guoniu.zhou@oss.nxp.com wrote:
> From: Guoniu Zhou <guoniu.zhou@nxp.com>
>
> Change "clocks" to 'clocks' in the description to match the quote style
> used for property names like '#clock-cells' throughout the file.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
> ---
> Changes in v10:
> - New patch to fix inconsistent quote usage (Krzysztof Kozlowski)
I think this is not necessary. I comment to have consistent style for a
new code, but changing this in existing one is just too much of work for
no real benefits.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v3 0/2] arm64: dts: qcom: lemans-evk: Enable WCN6855 BT via PCIe M.2 Key E connector
From: Wei Deng @ 2026-06-22 6:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, quic_chezhou,
cheng.jiang, shuai.zhang, jinwang.li, xiuzhuo.shang, mengshi.wu,
Wei Deng, Dmitry Baryshkov, Manivannan Sadhasivam,
Bartosz Golaszewski
This series enables the WCN6855 Bluetooth/WLAN module on the lemans EVK
via the PCIe M.2 Key E connector.
Patch 1 adds the PCI-to-PCI bridge compatible to the lemans pcieport0
Root Port in the SoC dtsi, which is required to associate downstream
M.2 connector graph endpoints with their PCI devices.
Patch 2 describes the M.2 Key E connector on lemans-evk and links it
with PCIe RP0 and UART17 via graph ports/endpoints.
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
Changes in v3:
- Split the lemans.dtsi pcieport0 compatible into its own patch (Konrad)
- Send as a new thread, switch to b4 workflow (Konrad, Dmitry)
- Carry over Reviewed-by tags since the diff content is unchanged
- Link to v2: https://lore.kernel.org/all/20260615103228.3104083-1-wei.deng@oss.qualcomm.com/
Changes in v2:
- Collect Reviewed-by tag and reorganize the patch (Bartosz)
- Link to v1: https://lore.kernel.org/all/20260608091702.3797437-1-wei.deng@oss.qualcomm.com/
---
Wei Deng (2):
arm64: dts: qcom: lemans: Add compatible to the PCIe Root Port
arm64: dts: qcom: lemans-evk: Describe the PCIe M.2 Key E connector
arch/arm64/boot/dts/qcom/lemans-evk.dts | 75 +++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 1 +
2 files changed, 76 insertions(+)
---
base-commit: e503fdd88e7d8f1922426bca1602049de010a66c
change-id: 20260622-v3-lemans-split-5e372766ecb6
Best regards,
--
Wei Deng <wei.deng@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v3 1/2] arm64: dts: qcom: lemans: Add compatible to the PCIe Root Port
From: Wei Deng @ 2026-06-22 6:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, quic_chezhou,
cheng.jiang, shuai.zhang, jinwang.li, xiuzhuo.shang, mengshi.wu,
Wei Deng, Dmitry Baryshkov, Manivannan Sadhasivam,
Bartosz Golaszewski
In-Reply-To: <20260622-v3-lemans-split-v3-0-d26bb22594e3@oss.qualcomm.com>
Add 'compatible = "pciclass,0604"' to the pcieport0 node in lemans.dtsi
to allow the PCI subsystem to associate the DT node with the PCI-to-PCI
bridge device. This is required for downstream DT nodes (such as M.2
connectors described as graph endpoints of the Root Port) to be matched
to PCI devices.
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 353a6e6fd3ac..9afd6e8ebcdb 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2779,6 +2779,7 @@ pcie0: pcie@1c00000 {
status = "disabled";
pcieport0: pcie@0 {
+ compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/2] arm64: dts: qcom: lemans-evk: Describe the PCIe M.2 Key E connector
From: Wei Deng @ 2026-06-22 6:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, quic_chezhou,
cheng.jiang, shuai.zhang, jinwang.li, xiuzhuo.shang, mengshi.wu,
Wei Deng, Dmitry Baryshkov, Manivannan Sadhasivam,
Bartosz Golaszewski
In-Reply-To: <20260622-v3-lemans-split-v3-0-d26bb22594e3@oss.qualcomm.com>
The lemans EVK has the PCIe M.2 Mechanical Key E connector to connect
wireless connectivity cards over PCIe and UART interfaces. Hence,
describe the connector node and link it with the PCIe 0 Root Port and
UART17 nodes through graph port/endpoint.
The M.2 Key E connector is powered by a 3.3V fixed regulator
(vreg_wcn_3p3) which is sourced from the board's 12V DC input rail
(vreg_dcin_12v). Both regulators are always-on and are required by the
pcie-m2-e-connector binding.
Also add the serial1 = &uart17 alias, which is required for the
Bluetooth serdev device to be enumerated on the UART17 interface.
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 75 +++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index 34dfc8d22b6a..b2967cb53760 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -21,6 +21,7 @@ aliases {
ethernet0 = ðernet0;
mmc1 = &sdhc;
serial0 = &uart10;
+ serial1 = &uart17;
serial2 = &uart0;
};
@@ -88,6 +89,38 @@ usb2_con_hs_ep: endpoint {
};
};
+ connector-3 {
+ compatible = "pcie-m2-e-connector";
+ vpcie3v3-supply = <&vreg_wcn_3p3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ m2_e_pcie_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&pcieport0_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ m2_e_uart_ep: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&uart17_ep>;
+ };
+ };
+ };
+ };
+
edp0-connector {
compatible = "dp-connector";
label = "EDP0";
@@ -178,6 +211,17 @@ vmmc_sdc: regulator-vmmc-sdc {
regulator-max-microvolt = <2950000>;
};
+ vreg_dcin_12v: regulator-dcin-12v {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_DCIN_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
vreg_sdc: regulator-vreg-sdc {
compatible = "regulator-gpio";
@@ -191,6 +235,19 @@ vreg_sdc: regulator-vreg-sdc {
startup-delay-us = <100>;
};
+
+ vreg_wcn_3p3: regulator-wcn-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_WCN_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_dcin_12v>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&apps_rsc {
@@ -742,6 +799,14 @@ &pcie1_phy {
status = "okay";
};
+&pcieport0 {
+ port {
+ pcieport0_ep: endpoint {
+ remote-endpoint = <&m2_e_pcie_ep>;
+ };
+ };
+};
+
&pmm8654au_0_pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@@ -970,6 +1035,16 @@ &uart10 {
status = "okay";
};
+&uart17 {
+ status = "okay";
+
+ port {
+ uart17_ep: endpoint {
+ remote-endpoint = <&m2_e_uart_ep>;
+ };
+ };
+};
+
&ufs_mem_hc {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v6 04/21] RISC-V: Define indirect CSR access helpers
From: Charlie Jenkins @ 2026-06-22 6:42 UTC (permalink / raw)
To: Atish Patra
Cc: James Clark, Rob Herring, Arnaldo Carvalho de Melo, Jiri Olsa,
Will Deacon, Mark Rutland, Anup Patel, Namhyung Kim,
Paul Walmsley, Krzysztof Kozlowski, Ian Rogers, linux-riscv,
linux-kernel, linux-perf-users, Conor Dooley, devicetree,
linux-arm-kernel
In-Reply-To: <20260608-counter_delegation-v6-4-285b72ed65a9@meta.com>
On Mon, Jun 08, 2026 at 11:01:18PM -0700, Atish Patra wrote:
> From: Atish Patra <atishp@rivosinc.com>
>
> The indriect CSR requires multiple instructions to read/write CSR.
indirect
> Add a few helper functions for ease of usage.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> arch/riscv/include/asm/csr_ind.h | 44 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_ind.h
> new file mode 100644
> index 000000000000..6fd7d44dc640
> --- /dev/null
> +++ b/arch/riscv/include/asm/csr_ind.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2024 Rivos Inc.
I don't think it makes sense to introduce this copyright in new commits.
- Charlie
> + */
> +
> +#ifndef _ASM_RISCV_CSR_IND_H
> +#define _ASM_RISCV_CSR_IND_H
> +
> +#include <linux/irqflags.h>
> +
> +#include <asm/csr.h>
> +
> +#define csr_ind_read(iregcsr, iselbase, iseloff) ({ \
> + unsigned long __value = 0; \
> + unsigned long __flags; \
> + local_irq_save(__flags); \
> + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \
> + __value = csr_read(iregcsr); \
> + local_irq_restore(__flags); \
> + __value; \
> +})
> +
> +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({ \
> + unsigned long __flags; \
> + local_irq_save(__flags); \
> + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \
> + csr_write(iregcsr, (value)); \
> + local_irq_restore(__flags); \
> +})
> +
> +#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({ \
> + unsigned long __old_val = 0, __value = 0; \
> + unsigned long __flags; \
> + local_irq_save(__flags); \
> + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \
> + __old_val = csr_read(iregcsr); \
> + csr_write(iregcsr, (warl_val)); \
> + __value = csr_read(iregcsr); \
> + csr_write(iregcsr, __old_val); \
> + local_irq_restore(__flags); \
> + __value; \
> +})
> +
> +#endif
>
> --
> 2.53.0-Meta
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
^ permalink raw reply
* Re: [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition
From: Charlie Jenkins @ 2026-06-22 6:43 UTC (permalink / raw)
To: Atish Patra
Cc: James Clark, Rob Herring, Arnaldo Carvalho de Melo, Jiri Olsa,
Will Deacon, Mark Rutland, Anup Patel, Namhyung Kim,
Paul Walmsley, Krzysztof Kozlowski, Ian Rogers, linux-riscv,
linux-kernel, linux-perf-users, Conor Dooley, devicetree,
linux-arm-kernel
In-Reply-To: <20260608-counter_delegation-v6-7-285b72ed65a9@meta.com>
On Mon, Jun 08, 2026 at 11:01:21PM -0700, Atish Patra wrote:
> From: Kaiwen Xue <kaiwenx@rivosinc.com>
>
> This adds the scountinhibit CSR definition and S-mode accessible hpmevent
> bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop
> counters directly from S-mode without invoking SBI calls to M-mode. It is
> also used to figure out the counters delegated to S-mode by the M-mode as
> well.
>
> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
> Reviewed-by: Clément Léger <cleger@rivosinc.com>
> ---
> arch/riscv/include/asm/csr.h | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index b4551a6cf7cb..26cb78dee2fd 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -241,6 +241,31 @@
> #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
> #define SMSTATEEN0_SSTATEEN0_SHIFT 63
> #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
> +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */
> +#ifdef CONFIG_64BIT
> +#define HPMEVENT_OF (BIT_ULL(63))
> +#define HPMEVENT_MINH (BIT_ULL(62))
> +#define HPMEVENT_SINH (BIT_ULL(61))
> +#define HPMEVENT_UINH (BIT_ULL(60))
> +#define HPMEVENT_VSINH (BIT_ULL(59))
> +#define HPMEVENT_VUINH (BIT_ULL(58))
> +#else
> +#define HPMEVENTH_OF (BIT_ULL(31))
> +#define HPMEVENTH_MINH (BIT_ULL(30))
> +#define HPMEVENTH_SINH (BIT_ULL(29))
> +#define HPMEVENTH_UINH (BIT_ULL(28))
> +#define HPMEVENTH_VSINH (BIT_ULL(27))
> +#define HPMEVENTH_VUINH (BIT_ULL(26))
Since these are rv32 bits for a 32-bit register, I think these should be
BIT() instead of BIT_ULL()
> +
> +#define HPMEVENT_OF (HPMEVENTH_OF << 32)
> +#define HPMEVENT_MINH (HPMEVENTH_MINH << 32)
> +#define HPMEVENT_SINH (HPMEVENTH_SINH << 32)
> +#define HPMEVENT_UINH (HPMEVENTH_UINH << 32)
> +#define HPMEVENT_VSINH (HPMEVENTH_VSINH << 32)
> +#define HPMEVENT_VUINH (HPMEVENTH_VUINH << 32)
These definitions are identical to the rv64 ones, can these be removed
and can you move the rv64 definitions to be global?
- Charlie
> +#endif
> +
> +#define SISELECT_SSCCFG_BASE 0x40
>
> /* mseccfg bits */
> #define MSECCFG_PMM ENVCFG_PMM
> @@ -322,6 +347,7 @@
> #define CSR_SCOUNTEREN 0x106
> #define CSR_SENVCFG 0x10a
> #define CSR_SSTATEEN0 0x10c
> +#define CSR_SCOUNTINHIBIT 0x120
> #define CSR_SSCRATCH 0x140
> #define CSR_SEPC 0x141
> #define CSR_SCAUSE 0x142
>
> --
> 2.53.0-Meta
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply
* Re: [PATCH v10 2/4] media: dt-bindings: Add CSI Pixel Formatter DT bindings
From: Krzysztof Kozlowski @ 2026-06-22 6:44 UTC (permalink / raw)
To: guoniu.zhou
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Laurent Pinchart, Frank Li, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, imx, linux-media, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, Guoniu Zhou
In-Reply-To: <20260618-csi_formatter-v10-2-f23830312ba5@oss.nxp.com>
On Thu, Jun 18, 2026 at 05:41:36PM +0800, guoniu.zhou@oss.nxp.com wrote:
> From: Guoniu Zhou <guoniu.zhou@nxp.com>
>
> The i.MX95 CSI pixel formatting module uses packet info, pixel and
> non-pixel data from the CSI-2 host controller and reformat them to
> match Pixel Link(PL) definition.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
> ---
> Changes in v10:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/2] interconnect: qcom: add Maili interconnect provider driver
From: sashiko-bot @ 2026-06-22 6:44 UTC (permalink / raw)
To: Raviteja Laggyshetty; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260622-maili_icc-v2-2-18b5ac08c04f@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Use-After-Free on driver unbind/rebind due to stale pointers in statically allocated driver structures.
--
commit 9266119e904a5c675879f8849d752743c3590271
Author: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
interconnect: qcom: add Maili interconnect provider driver
Add driver for the Qualcomm interconnect buses found in Maili
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pairs.
> diff --git a/drivers/interconnect/qcom/maili.c b/drivers/interconnect/qcom/maili.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/interconnect/qcom/maili.c
[ ... ]
> +static struct platform_driver qnoc_driver = {
> + .probe = qcom_icc_rpmh_probe,
> + .remove = qcom_icc_rpmh_remove,
[Severity: High]
This isn't a bug introduced by this patch, but I noticed the framework
functions used here might leave dangling pointers in the static data structures
introduced by this patch.
During a driver unbind, qcom_icc_rpmh_remove() frees the dynamically allocated
nodes associated with the provider:
qcom_icc_rpmh_remove() {
...
icc_nodes_remove(&qp->provider);
}
However, the qn->node pointers in the statically allocated driver structures
added in this patch are never cleared. If the driver is subsequently rebound
via sysfs, qcom_icc_rpmh_probe() sees the stale pointer and skips allocation:
qcom_icc_rpmh_probe() {
...
if (!qn->node)
qn->node = icc_node_create_dyn();
node = qn->node;
...
}
Does this code result in a use-after-free when the freed node memory is
accessed during the rebind?
> + .driver = {
> + .name = "qnoc-maili",
> + .of_match_table = qnoc_of_match,
> + .sync_state = icc_sync_state,
> + },
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com?part=2
^ permalink raw reply
* Re: [PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events
From: Charlie Jenkins @ 2026-06-22 6:44 UTC (permalink / raw)
To: Atish Patra
Cc: James Clark, Rob Herring, Arnaldo Carvalho de Melo, Jiri Olsa,
Will Deacon, Mark Rutland, Anup Patel, Namhyung Kim,
Paul Walmsley, Krzysztof Kozlowski, Ian Rogers, linux-riscv,
linux-kernel, linux-perf-users, Conor Dooley, devicetree,
linux-arm-kernel
In-Reply-To: <20260608-counter_delegation-v6-17-285b72ed65a9@meta.com>
On Mon, Jun 08, 2026 at 11:01:31PM -0700, Atish Patra wrote:
> From: Atish Patra <atishp@rivosinc.com>
>
> Qemu virt machine supports a very minimal set of legacy perf events.
> Add them to the vendor table so that users can use them when
> counter delegation is enabled.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> arch/riscv/include/asm/vendorid_list.h | 4 ++++
> drivers/perf/riscv_pmu_sbi.c | 36 ++++++++++++++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> index 7f5030ee1fcf..603aa2b21c0b 100644
> --- a/arch/riscv/include/asm/vendorid_list.h
> +++ b/arch/riscv/include/asm/vendorid_list.h
> @@ -11,4 +11,8 @@
> #define SIFIVE_VENDOR_ID 0x489
> #define THEAD_VENDOR_ID 0x5b7
>
> +#define QEMU_VIRT_VENDOR_ID 0x000
> +#define QEMU_VIRT_IMPL_ID 0x000
> +#define QEMU_VIRT_ARCH_ID 0x000
Palmer proposed a change to this a while ago to set the archid for qemu
as 42 but it looks like it was never merged in qemu, but it was merged
into the riscv spec.
Here is the spec PR: https://github.com/riscv/riscv-isa-manual/pull/1213
Here is the current spec: https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
Here is the QEMU patch: https://lore.kernel.org/all/20240131182430.20174-1-palmer@rivosinc.com/
Should we follow up with this/maybe this should be accounted for here as
an alternate id?
- Charlie
> +
> #endif
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 00b84b28117a..74acac54328e 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -26,6 +26,7 @@
> #include <asm/sbi.h>
> #include <asm/cpufeature.h>
> #include <asm/vendor_extensions.h>
> +#include <asm/vendorid_list.h>
> #include <asm/vendor_extensions/andes.h>
> #include <asm/hwcap.h>
> #include <asm/csr_ind.h>
> @@ -453,7 +454,42 @@ struct riscv_vendor_pmu_events {
> .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \
> .attrs_events = _attrs },
>
> +/* QEMU virt PMU events */
> +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_MAX] = {
> + PERF_MAP_ALL_UNSUPPORTED,
> + [PERF_COUNT_HW_CPU_CYCLES] = {0x01, 0xFFFFFFF8},
> + [PERF_COUNT_HW_INSTRUCTIONS] = {0x02, 0xFFFFFFF8}
> +};
> +
> +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
> + [PERF_COUNT_HW_CACHE_OP_MAX]
> + [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
> + PERF_CACHE_MAP_ALL_UNSUPPORTED,
> + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10019, 0xFFFFFFF8},
> + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = {0x1001B, 0xFFFFFFF8},
> +
> + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10021, 0xFFFFFFF8},
> +};
> +
> +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8);
> +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8);
> +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFFF8);
> +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFFFFF8);
> +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFFF8);
> +
> +static struct attribute *qemu_virt_event_group[] = {
> + RVPMU_EVENT_ATTR_PTR(cycles),
> + RVPMU_EVENT_ATTR_PTR(instructions),
> + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss),
> + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss),
> + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss),
> + NULL,
> +};
> +
> static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = {
> + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID, QEMU_VIRT_IMPL_ID,
> + qemu_virt_hw_event_map, qemu_virt_cache_event_map,
> + qemu_virt_event_group)
> };
>
> static const struct riscv_pmu_event *current_pmu_hw_event_map;
>
> --
> 2.53.0-Meta
>
>
^ permalink raw reply
* Re: [PATCH v10 3/4] dt-bindings: clock: imx95-blk-ctl: Define formatter child node schema
From: Krzysztof Kozlowski @ 2026-06-22 6:50 UTC (permalink / raw)
To: guoniu.zhou
Cc: Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Laurent Pinchart, Frank Li, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, imx, linux-media, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, Guoniu Zhou
In-Reply-To: <20260618-csi_formatter-v10-3-f23830312ba5@oss.nxp.com>
On Thu, Jun 18, 2026 at 05:41:37PM +0800, guoniu.zhou@oss.nxp.com wrote:
> From: Guoniu Zhou <guoniu.zhou@nxp.com>
>
> The Camera CSR contains control registers for multiple CSI formatter IPs
> at different register offsets. Each formatter is an independent hardware
> block with its own clock input and media pipeline connection.
>
> Define schema to allow formatter child nodes under nxp,imx95-camera-csr,
> with 'reg' property specifying the formatter's register offset within the
> CSR address space.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
> ---
> Changes in v10:
> - Use single quotes for regex pattern to be consistent (Krzysztof Kozlowski)
> - Add formatter subnode binding and camera-csr syscon example
> - Update commit title and message
>
> Changes in v9:
> - New patch to address the issue of formatter acting as a child node of syscon
> ---
> .../bindings/clock/nxp,imx95-blk-ctl.yaml | 64 +++++++++++++++++++++-
> 1 file changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> index 534fa219d9f9..b4d0a7670fac 100644
> --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> @@ -46,7 +46,27 @@ required:
> - power-domains
> - clocks
>
> -additionalProperties: false
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nxp,imx95-camera-csr
> + then:
> + properties:
> + '#address-cells':
> + const: 1
> + '#size-cells':
> + const: 1
These should go to top-level. In if:then:else: you only narrow them,
e.g. you disallow for other variants (": false").
if:
then:
....
required:
....
else:
properties:
'#address-cells': false
> + required:
> + - '#address-cells'
> + - '#size-cells'
> + patternProperties:
> + '^formatter@[0-9a-f]+$':
> + type: object
> + $ref: /schemas/media/fsl,imx95-csi-formatter.yaml#
This as well should be in top-level and here you only disallow it for
other variants.
You can avoid cross-tree dependencies by using compatible style:
https://elixir.bootlin.com/linux/v7.1-rc6/source/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml#L41
Best regards,
Krzysztof
^ permalink raw reply
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