* Re: [PATCH v3 1/2] dt-bindings: iio: dac: Add AD5529R
From: Jonathan Cameron @ 2026-06-23 14:57 UTC (permalink / raw)
To: Rodrigo Alencar
Cc: Nuno Sá, Conor Dooley, Janani Sunil, Janani Sunil,
Lars-Peter Clausen, Michael Hennerich, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Jonathan Corbet, Shuah Khan,
linux-iio, devicetree, linux-kernel, linux-doc, Mark Brown
In-Reply-To: <5guhkvoxhkzevjm4b45hhk3772akpnz3givr3gb56x5ywamzyf@oiycreun4y62>
On Tue, 23 Jun 2026 09:09:14 +0100
Rodrigo Alencar <455.rodrigo.alencar@gmail.com> wrote:
> On 22/06/26 13:20, Nuno Sá wrote:
> > On Mon, Jun 22, 2026 at 12:51:20PM +0100, Rodrigo Alencar wrote:
> > > On 22/06/26 11:29, Nuno Sá wrote:
> > > > On Mon, Jun 22, 2026 at 10:24:05AM +0100, Rodrigo Alencar wrote:
> > > > > On 21/06/26 15:33, Jonathan Cameron wrote:
> > > > > > On Fri, 19 Jun 2026 16:54:11 +0100
> > > > > > Nuno Sá <noname.nuno@gmail.com> wrote:
> > > > > >
> > > > > > > On Fri, Jun 19, 2026 at 03:12:07PM +0100, Conor Dooley wrote:
> > > > > > > > On Fri, Jun 19, 2026 at 02:01:08PM +0100, Nuno Sá wrote:
> > > > > > > > > On Fri, Jun 19, 2026 at 12:40:54PM +0100, Conor Dooley wrote:
> > > > > > > > > > On Fri, Jun 19, 2026 at 12:36:55PM +0100, Conor Dooley wrote:
> > > > > > > > > > > On Fri, Jun 19, 2026 at 12:33:11PM +0200, Janani Sunil wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > On 6/14/26 21:44, Jonathan Cameron wrote:
> > > > > > > > > > > > > On Tue, 9 Jun 2026 16:47:23 +0200
> > > > > > > > > > > > > Janani Sunil <jan.sun97@gmail.com> wrote:
> > > > > > > > > > > > >
> > > > > > > > > > > > > > On 5/26/26 15:11, Rodrigo Alencar wrote:
> > > > > > > > > > > > > > > On 26/05/19 05:42PM, Janani Sunil wrote:
> > > > > > > > > > > > > > > > Devicetree bindings for AD5529R 16 channel 12/16 bit high voltage,
> > > > > > > > > > > > > > > > buffered voltage output digital-to-analog converter (DAC) with an
> > > > > > > > > > > > > > > > integrated precision reference.
> > > > > > > > > > > > > > > ...
> > > > > > > > > > > > > > > Probably others may comment on that, but...
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > This parent node may support device addressing for multi-device support through
> > > > > > > > > > > > > > > those ID pins. I suppose that each device may have its own power supplies or
> > > > > > > > > > > > > > > other resources like the toggle pins or reset and enable.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > That way I suppose that an example would look like...
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > +patternProperties:
> > > > > > > > > > > > > > > > + "^channel@([0-9]|1[0-5])$":
> > > > > > > > > > > > > > > > + type: object
> > > > > > > > > > > > > > > > + description: Child nodes for individual channel configuration
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + properties:
> > > > > > > > > > > > > > > > + reg:
> > > > > > > > > > > > > > > > + description: Channel number.
> > > > > > > > > > > > > > > > + minimum: 0
> > > > > > > > > > > > > > > > + maximum: 15
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + adi,output-range-microvolt:
> > > > > > > > > > > > > > > > + description: |
> > > > > > > > > > > > > > > > + Output voltage range for this channel as [min, max] in microvolts.
> > > > > > > > > > > > > > > > + If not specified, defaults to 0V to 5V range.
> > > > > > > > > > > > > > > > + oneOf:
> > > > > > > > > > > > > > > > + - items:
> > > > > > > > > > > > > > > > + - const: 0
> > > > > > > > > > > > > > > > + - enum: [5000000, 10000000, 20000000, 40000000]
> > > > > > > > > > > > > > > > + - items:
> > > > > > > > > > > > > > > > + - const: -5000000
> > > > > > > > > > > > > > > > + - const: 5000000
> > > > > > > > > > > > > > > > + - items:
> > > > > > > > > > > > > > > > + - const: -10000000
> > > > > > > > > > > > > > > > + - const: 10000000
> > > > > > > > > > > > > > > > + - items:
> > > > > > > > > > > > > > > > + - const: -15000000
> > > > > > > > > > > > > > > > + - const: 15000000
> > > > > > > > > > > > > > > > + - items:
> > > > > > > > > > > > > > > > + - const: -20000000
> > > > > > > > > > > > > > > > + - const: 20000000
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + required:
> > > > > > > > > > > > > > > > + - reg
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + additionalProperties: false
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > +required:
> > > > > > > > > > > > > > > > + - compatible
> > > > > > > > > > > > > > > > + - reg
> > > > > > > > > > > > > > > > + - vdd-supply
> > > > > > > > > > > > > > > > + - avdd-supply
> > > > > > > > > > > > > > > > + - hvdd-supply
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > +dependencies:
> > > > > > > > > > > > > > > > + spi-cpha: [ spi-cpol ]
> > > > > > > > > > > > > > > > + spi-cpol: [ spi-cpha ]
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > +allOf:
> > > > > > > > > > > > > > > > + - $ref: /schemas/spi/spi-peripheral-props.yaml#
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > +unevaluatedProperties: false
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > +examples:
> > > > > > > > > > > > > > > > + - |
> > > > > > > > > > > > > > > > + #include <dt-bindings/gpio/gpio.h>
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + spi {
> > > > > > > > > > > > > > > > + #address-cells = <1>;
> > > > > > > > > > > > > > > > + #size-cells = <0>;
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + dac@0 {
> > > > > > > > > > > > > > > > + compatible = "adi,ad5529r-16";
> > > > > > > > > > > > > > > > + reg = <0>;
> > > > > > > > > > > > > > > > + spi-max-frequency = <25000000>;
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + vdd-supply = <&vdd_regulator>;
> > > > > > > > > > > > > > > > + avdd-supply = <&avdd_regulator>;
> > > > > > > > > > > > > > > > + hvdd-supply = <&hvdd_regulator>;
> > > > > > > > > > > > > > > > + hvss-supply = <&hvss_regulator>;
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + #address-cells = <1>;
> > > > > > > > > > > > > > > > + #size-cells = <0>;
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + channel@0 {
> > > > > > > > > > > > > > > > + reg = <0>;
> > > > > > > > > > > > > > > > + adi,output-range-microvolt = <0 5000000>;
> > > > > > > > > > > > > > > > + };
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + channel@1 {
> > > > > > > > > > > > > > > > + reg = <1>;
> > > > > > > > > > > > > > > > + adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > > > > > > > > > > > > + };
> > > > > > > > > > > > > > > > +
> > > > > > > > > > > > > > > > + channel@2 {
> > > > > > > > > > > > > > > > + reg = <2>;
> > > > > > > > > > > > > > > > + adi,output-range-microvolt = <0 40000000>;
> > > > > > > > > > > > > > > > + };
> > > > > > > > > > > > > > > > + };
> > > > > > > > > > > > > > > > + };
> > > > > > > > > > > > > > > ...
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > spi {
> > > > > > > > > > > > > > > #address-cells = <1>;
> > > > > > > > > > > > > > > #size-cells = <0>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > multi-dac@0 {
> > > > > > > > > > > > > > > compatible = "adi,ad5529r-16";
> > > > > > > > > > > > > > > reg = <0>;
> > > > > > > > > > > > > > > spi-max-frequency = <25000000>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > #address-cells = <1>;
> > > > > > > > > > > > > > > #size-cells = <0>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > dac@0 {
> > > > > > > > > > > > > > > reg = <0>;
> > > > > > > > > > > > > > > vdd-supply = <&vdd_regulator>;
> > > > > > > > > > > > > > > avdd-supply = <&avdd_regulator>;
> > > > > > > > > > > > > > > hvdd-supply = <&hvdd_regulator>;
> > > > > > > > > > > > > > > hvss-supply = <&hvss_regulator>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > #address-cells = <1>;
> > > > > > > > > > > > > > > #size-cells = <0>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > channel@0 {
> > > > > > > > > > > > > > > reg = <0>;
> > > > > > > > > > > > > > > adi,output-range-microvolt = <0 5000000>;
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > channel@1 {
> > > > > > > > > > > > > > > reg = <1>;
> > > > > > > > > > > > > > > adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > channel@2 {
> > > > > > > > > > > > > > > reg = <2>;
> > > > > > > > > > > > > > > adi,output-range-microvolt = <0 40000000>;
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > > }
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > dac@1 {
> > > > > > > > > > > > > > > reg = <1>;
> > > > > > > > > > > > > > > vdd-supply = <&vdd_regulator>;
> > > > > > > > > > > > > > > avdd-supply = <&avdd_regulator>;
> > > > > > > > > > > > > > > hvdd-supply = <&hvdd_regulator>;
> > > > > > > > > > > > > > > hvss-supply = <&hvss_regulator>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > reset-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > #address-cells = <1>;
> > > > > > > > > > > > > > > #size-cells = <0>;
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > channel@0 {
> > > > > > > > > > > > > > > reg = <0>;
> > > > > > > > > > > > > > > adi,output-range-microvolt = <0 5000000>;
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > channel@1 {
> > > > > > > > > > > > > > > reg = <1>;
> > > > > > > > > > > > > > > adi,output-range-microvolt = <(-10000000) 10000000>;
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > > }
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > > };
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > then you might need something like:
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > patternProperties:
> > > > > > > > > > > > > > > "^dac@[0-3]$":
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > and put most of the things under this node pattern.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > So the main driver that you're putting together might need to handle up to four instances.
> > > > > > > > > > > > > > > Even if your current driver cannot handle this, the dt-bindings might need cover that.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Need to double check if each dac node needs a separate compatible, so you would maybe populate
> > > > > > > > > > > > > > > a platform data to be shared with the child nodes, which would be a separate driver.
> > > > > > > > > > > > > > > (not sure if it would make sense to mix and match ad5529r-16 and ad5529r-12).
> > > > > > > > > > > > > > Hi Rodrigo,
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Thank you for looking at this.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > For now, I would prefer to keep the binding scoped to a single AD5529R device instance. The current
> > > > > > > > > > > > > > hardware/use case we have only needs one device node and the driver is written around that model as well.
> > > > > > > > > > > > > > While the device addressing pins could allow multi-device topology, we do not have an actual platform using
> > > > > > > > > > > > > > that configuration at the moment, so I would prefer not to introduce an extra parent/child binding structure
> > > > > > > > > > > > > > speculatively without a validating use case.
> > > > > > > > > > > > > Interesting feature - kind of similar to address control on a typical i2c bus device, or
> > > > > > > > > > > > > looking at it another way a kind of distributed SPI mux.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Challenge of a binding is we need to anticipate the future. So I think we do need something
> > > > > > > > > > > > > like Rodrigo is suggesting even if we only (for now) support a single instance in the driver.
> > > > > > > > > > > > > That would leave the path open to supporting the addressing at a later date.
> > > > > > > > > > > > > An alternative might be to look at it like a chained device setup. In those we pretend there
> > > > > > > > > > > > > is just one device with a lot of channels etc. The snag is that here things are more loosely
> > > > > > > > > > > > > coupled whereas for those devices it tends to be you have to read / write the same register
> > > > > > > > > > > > > in all devices in the chain as one big SPI message.
> > > > > > > > > > > > >
> > > > > > > > > > > > > +CC Mark Brown as he may know of some precedence for this feature. For his reference..
> > > > > > > > > > > > > - Each of these device has 2 ID pins. The SPI transfers have to contain the 2 bit
> > > > > > > > > > > > > value that matches that or they are ignored. Thus a single bus + 1 chip select can
> > > > > > > > > > > > > be used to talk to 4 devices. Question is what that looks like in device tree + I guess
> > > > > > > > > > > > > longer term how to support it cleanly in SPI.
> > > > > > > > > > >
> > > > > > > > > > > I'd swear I have seen this before, from some Microchip devices. Let me
> > > > > > > > > > > see if I can find what I am thinking of...
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > microchip,mcp3911 and microchip,mcp3564 both seem to do this with
> > > > > > > > > > slightly different properties.
> > > > > > > > > >
> > > > > > > > > > microchip,device-addr:
> > > > > > > > > > description: Device address when multiple MCP3911 chips are present on the same SPI bus.
> > > > > > > > > > $ref: /schemas/types.yaml#/definitions/uint32
> > > > > > > > > > enum: [0, 1, 2, 3]
> > > > > > > > > > default: 0
> > > > > > > > > >
> > > > > > > > > > and
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > microchip,hw-device-address:
> > > > > > > > > > $ref: /schemas/types.yaml#/definitions/uint32
> > > > > > > > > > minimum: 0
> > > > > > > > > > maximum: 3
> > > > > > > > > > description:
> > > > > > > > > > The address is set on a per-device basis by fuses in the factory,
> > > > > > > > > > configured on request. If not requested, the fuses are set for 0x1.
> > > > > > > > > > The device address is part of the device markings to avoid
> > > > > > > > > > potential confusion. This address is coded on two bits, so four possible
> > > > > > > > > > addresses are available when multiple devices are present on the same
> > > > > > > > > > SPI bus with only one Chip Select line for all devices.
> > > > > > > > > > Each device communication starts by a CS falling edge, followed by the
> > > > > > > > > > clocking of the device address (BITS[7:6] - top two bits of COMMAND BYTE
> > > > > > > > > > which is first one on the wire).
> > > > > > > > > >
> > > > > > > > > > This sounds exactly like the sort of feature that you're dealing with
> > > > > > > > > > here?
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > The core idea yes but for this chip, things are a bit more annoying (but
> > > > > > > > > Janani can correct me if I'm wrong). Here, each device can, in theory,
> > > > > > > > > have it's own supplies, pins and at the very least, channels with maybe
> > > > > > > > > different scales. That is why Janani is proposing dac nodes. Given I
> > > > > > > > > honestly don't like much of that "adi,ad5529r-bus" compatible I wondered
> > > > > > > > > about solving this at the spi level.
> > > > > > > > >
> > > > > > > > > Ah and to make it more annoying, we can also mix 12 and 16 bits variants
> > > > > > > > > together in the same bus.
> > > > > > > >
> > > > > > > > I'm definitely missing something, because that property for the
> > > > > > > > microchip devices is not impacted what else is on the bus. AFAICT, you
> > > > > > > > could have an mcp3911 and an mcp3564 on the same bus even though both
> > > > > > > > are completely different devices with different drivers. They have
> > > > > > > > individual device nodes and their own supplies etc etc. These aren't
> > > > > > > > per-channel properties on an adc or dac, they're per child device on a
> > > > > > > > spi bus.
> > > > > > >
> > > > > > > Maybe I'm the one missing something :). IIRC, spi would not allow two
> > > > > > > devices on the same CS right? Because for this chip we would need
> > > > > > > something like:
> > > > > > >
> > > > > > > spi {
> > > > > > > dac@0 {
> > > > > > > reg = <0>;
> > > > > > > adi,pin-id = <0>;
> > > > > > > };
> > > > > > >
> > > > > > > dac@1 {
> > > > > > > reg = <0>; // which seems already problematic?
> > > > > > > adi,pin-id <1>;
> > > > > > > };
> > > > > > >
> > > > > > > ...
> > > > > > >
> > > > > > > //up to 4
> > > > > > > };
> > > > > > Yeah. It's not clear to me how that works for the microchip devices
> > > > > > (I suspect it doesn't!)
> > > > > >
> > > > > > Just thinking as I type, but could we do something a bit nasty with
> > > > > > a gpio mux that doesn't actually switch but represents the GPIO being
> > > > > > shared? Given this is all tied to the spi bus that should all happen
> > > > > > under serializing locks.
> > > > > >
> > > > > > Agreed though that this would be nicer as an SPI thing that let
> > > > > > us specify that a single CS is share by multiple devices and their
> > > > > > is some other signal acting to select which one we are talking to.
> > > > > >
> > > > >
> > > > > If the device-addressing on the same chip-select is to be handled
> > > > > by the spi framework, wouldn't we lose device-specific features?
> > > > >
> > > > > I understand that this multi-device feature is there mostly to extend the
> > > > > channel count from 16 to 32, 48 or 64. I suppose the command:
> > > > >
> > > > > "MULTI DEVICE SW LDAC MODE"
> > > > >
> > > > > exists so that software can update channel values accross multiple devices.
> > > >
> > > > Right! You do have a point! I agree the main driver for a feature like
> > > > this is likely to extend the channel count and effectively "aggregate"
> > > > devices.
> > > >
> > > > But I would say that even with the spi solution the MULTI DEVICE stuff
> > > > should be doable (as we still need a sort of adi,pin-id property).
> > >
> > > I don't think we can have something like an IIO buffer shared by multiple
> > > devices. Synchronizing separate devices would be doable with proper hardware
> > > support for this (probably involving an FGPA).
> >
> > True!
> >
> > >
> > > > But yes, I do feel that the whole feature is for aggregation so seeing
> > > > one device with 32 channels is the expectation here? Rather than seeing
> > > > two devices with 16 channels.
> > >
> > > Yes, I think aggregation is the whole point there... so that the IIO driver
> > > is multi-device-aware.
> >
> > Which makes me feel that different pins per device might be possible
> > from an HW point of view but does not make much sense. For example, for
> > the buffer example I would expect LDAC to be shared between all the
> > devices.
>
> That is why I would still suggest the multi-dac node in the middle...
> the parent node can hold shared resources, while the dac children can
> have their own, overriding or inheriting stuff.
>
Before going down that path I'd want confirmation this is something we
actually think anyone will build.
Jonathan
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: iio: dac: Add AD5529R
From: Jonathan Cameron @ 2026-06-23 14:55 UTC (permalink / raw)
To: Janani Sunil
Cc: David Lechner, Nuno Sá, Rodrigo Alencar, Conor Dooley,
Janani Sunil, Lars-Peter Clausen, Michael Hennerich, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Jonathan Corbet, Shuah Khan, linux-iio, devicetree,
linux-kernel, linux-doc, Mark Brown
In-Reply-To: <0f778d06-726f-4aec-ab3b-f6e091cc9421@gmail.com>
On Tue, 23 Jun 2026 12:07:52 +0200
Janani Sunil <jan.sun97@gmail.com> wrote:
> On 6/22/26 17:36, David Lechner wrote:
> > On 6/22/26 7:20 AM, Nuno Sá wrote:
> >> On Mon, Jun 22, 2026 at 12:51:20PM +0100, Rodrigo Alencar wrote:
> >>> On 22/06/26 11:29, Nuno Sá wrote:
> >>>> On Mon, Jun 22, 2026 at 10:24:05AM +0100, Rodrigo Alencar wrote:
> >>>>> On 21/06/26 15:33, Jonathan Cameron wrote:
> >>>>>> On Fri, 19 Jun 2026 16:54:11 +0100
> >>>>>> Nuno Sá <noname.nuno@gmail.com> wrote:
> >>>>>>
> >>>>>>> On Fri, Jun 19, 2026 at 03:12:07PM +0100, Conor Dooley wrote:
> >>>>>>>> On Fri, Jun 19, 2026 at 02:01:08PM +0100, Nuno Sá wrote:
> >>>>>>>>> On Fri, Jun 19, 2026 at 12:40:54PM +0100, Conor Dooley wrote:
> >>>>>>>>>> On Fri, Jun 19, 2026 at 12:36:55PM +0100, Conor Dooley wrote:
> >>>>>>>>>>> On Fri, Jun 19, 2026 at 12:33:11PM +0200, Janani Sunil wrote:
> >>>>>>>>>>>> On 6/14/26 21:44, Jonathan Cameron wrote:
> >>>>>>>>>>>>> On Tue, 9 Jun 2026 16:47:23 +0200
> >>>>>>>>>>>>> Janani Sunil <jan.sun97@gmail.com> wrote:
> >>>>>>>>>>>>>
> >>>>>>>>>>>>>> On 5/26/26 15:11, Rodrigo Alencar wrote:
> >>>>>>>>>>>>>>> On 26/05/19 05:42PM, Janani Sunil wrote:
> >>>>>>>>>>>>>>>> Devicetree bindings for AD5529R 16 channel 12/16 bit high voltage,
> >>>>>>>>>>>>>>>> buffered voltage output digital-to-analog converter (DAC) with an
> >>>>>>>>>>>>>>>> integrated precision reference.
> >>>>>>>>>>>>>>> ...
> >>>>>>>>>>>>>>> Probably others may comment on that, but...
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> This parent node may support device addressing for multi-device support through
> >>>>>>>>>>>>>>> those ID pins. I suppose that each device may have its own power supplies or
> >>>>>>>>>>>>>>> other resources like the toggle pins or reset and enable.
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> That way I suppose that an example would look like...
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> +patternProperties:
> >>>>>>>>>>>>>>>> + "^channel@([0-9]|1[0-5])$":
> >>>>>>>>>>>>>>>> + type: object
> >>>>>>>>>>>>>>>> + description: Child nodes for individual channel configuration
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + properties:
> >>>>>>>>>>>>>>>> + reg:
> >>>>>>>>>>>>>>>> + description: Channel number.
> >>>>>>>>>>>>>>>> + minimum: 0
> >>>>>>>>>>>>>>>> + maximum: 15
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + adi,output-range-microvolt:
> >>>>>>>>>>>>>>>> + description: |
> >>>>>>>>>>>>>>>> + Output voltage range for this channel as [min, max] in microvolts.
> >>>>>>>>>>>>>>>> + If not specified, defaults to 0V to 5V range.
> >>>>>>>>>>>>>>>> + oneOf:
> >>>>>>>>>>>>>>>> + - items:
> >>>>>>>>>>>>>>>> + - const: 0
> >>>>>>>>>>>>>>>> + - enum: [5000000, 10000000, 20000000, 40000000]
> >>>>>>>>>>>>>>>> + - items:
> >>>>>>>>>>>>>>>> + - const: -5000000
> >>>>>>>>>>>>>>>> + - const: 5000000
> >>>>>>>>>>>>>>>> + - items:
> >>>>>>>>>>>>>>>> + - const: -10000000
> >>>>>>>>>>>>>>>> + - const: 10000000
> >>>>>>>>>>>>>>>> + - items:
> >>>>>>>>>>>>>>>> + - const: -15000000
> >>>>>>>>>>>>>>>> + - const: 15000000
> >>>>>>>>>>>>>>>> + - items:
> >>>>>>>>>>>>>>>> + - const: -20000000
> >>>>>>>>>>>>>>>> + - const: 20000000
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + required:
> >>>>>>>>>>>>>>>> + - reg
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + additionalProperties: false
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> +required:
> >>>>>>>>>>>>>>>> + - compatible
> >>>>>>>>>>>>>>>> + - reg
> >>>>>>>>>>>>>>>> + - vdd-supply
> >>>>>>>>>>>>>>>> + - avdd-supply
> >>>>>>>>>>>>>>>> + - hvdd-supply
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> +dependencies:
> >>>>>>>>>>>>>>>> + spi-cpha: [ spi-cpol ]
> >>>>>>>>>>>>>>>> + spi-cpol: [ spi-cpha ]
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> +allOf:
> >>>>>>>>>>>>>>>> + - $ref: /schemas/spi/spi-peripheral-props.yaml#
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> +unevaluatedProperties: false
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> +examples:
> >>>>>>>>>>>>>>>> + - |
> >>>>>>>>>>>>>>>> + #include <dt-bindings/gpio/gpio.h>
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + spi {
> >>>>>>>>>>>>>>>> + #address-cells = <1>;
> >>>>>>>>>>>>>>>> + #size-cells = <0>;
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + dac@0 {
> >>>>>>>>>>>>>>>> + compatible = "adi,ad5529r-16";
> >>>>>>>>>>>>>>>> + reg = <0>;
> >>>>>>>>>>>>>>>> + spi-max-frequency = <25000000>;
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + vdd-supply = <&vdd_regulator>;
> >>>>>>>>>>>>>>>> + avdd-supply = <&avdd_regulator>;
> >>>>>>>>>>>>>>>> + hvdd-supply = <&hvdd_regulator>;
> >>>>>>>>>>>>>>>> + hvss-supply = <&hvss_regulator>;
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + #address-cells = <1>;
> >>>>>>>>>>>>>>>> + #size-cells = <0>;
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + channel@0 {
> >>>>>>>>>>>>>>>> + reg = <0>;
> >>>>>>>>>>>>>>>> + adi,output-range-microvolt = <0 5000000>;
> >>>>>>>>>>>>>>>> + };
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + channel@1 {
> >>>>>>>>>>>>>>>> + reg = <1>;
> >>>>>>>>>>>>>>>> + adi,output-range-microvolt = <(-10000000) 10000000>;
> >>>>>>>>>>>>>>>> + };
> >>>>>>>>>>>>>>>> +
> >>>>>>>>>>>>>>>> + channel@2 {
> >>>>>>>>>>>>>>>> + reg = <2>;
> >>>>>>>>>>>>>>>> + adi,output-range-microvolt = <0 40000000>;
> >>>>>>>>>>>>>>>> + };
> >>>>>>>>>>>>>>>> + };
> >>>>>>>>>>>>>>>> + };
> >>>>>>>>>>>>>>> ...
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> spi {
> >>>>>>>>>>>>>>> #address-cells = <1>;
> >>>>>>>>>>>>>>> #size-cells = <0>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> multi-dac@0 {
> >>>>>>>>>>>>>>> compatible = "adi,ad5529r-16";
> >>>>>>>>>>>>>>> reg = <0>;
> >>>>>>>>>>>>>>> spi-max-frequency = <25000000>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> #address-cells = <1>;
> >>>>>>>>>>>>>>> #size-cells = <0>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> dac@0 {
> >>>>>>>>>>>>>>> reg = <0>;
> >>>>>>>>>>>>>>> vdd-supply = <&vdd_regulator>;
> >>>>>>>>>>>>>>> avdd-supply = <&avdd_regulator>;
> >>>>>>>>>>>>>>> hvdd-supply = <&hvdd_regulator>;
> >>>>>>>>>>>>>>> hvss-supply = <&hvss_regulator>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> #address-cells = <1>;
> >>>>>>>>>>>>>>> #size-cells = <0>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> channel@0 {
> >>>>>>>>>>>>>>> reg = <0>;
> >>>>>>>>>>>>>>> adi,output-range-microvolt = <0 5000000>;
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> channel@1 {
> >>>>>>>>>>>>>>> reg = <1>;
> >>>>>>>>>>>>>>> adi,output-range-microvolt = <(-10000000) 10000000>;
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> channel@2 {
> >>>>>>>>>>>>>>> reg = <2>;
> >>>>>>>>>>>>>>> adi,output-range-microvolt = <0 40000000>;
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>> }
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> dac@1 {
> >>>>>>>>>>>>>>> reg = <1>;
> >>>>>>>>>>>>>>> vdd-supply = <&vdd_regulator>;
> >>>>>>>>>>>>>>> avdd-supply = <&avdd_regulator>;
> >>>>>>>>>>>>>>> hvdd-supply = <&hvdd_regulator>;
> >>>>>>>>>>>>>>> hvss-supply = <&hvss_regulator>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> reset-gpios = <&gpio0 88 GPIO_ACTIVE_LOW>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> #address-cells = <1>;
> >>>>>>>>>>>>>>> #size-cells = <0>;
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> channel@0 {
> >>>>>>>>>>>>>>> reg = <0>;
> >>>>>>>>>>>>>>> adi,output-range-microvolt = <0 5000000>;
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> channel@1 {
> >>>>>>>>>>>>>>> reg = <1>;
> >>>>>>>>>>>>>>> adi,output-range-microvolt = <(-10000000) 10000000>;
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>> }
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>> };
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> then you might need something like:
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> patternProperties:
> >>>>>>>>>>>>>>> "^dac@[0-3]$":
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> and put most of the things under this node pattern.
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> So the main driver that you're putting together might need to handle up to four instances.
> >>>>>>>>>>>>>>> Even if your current driver cannot handle this, the dt-bindings might need cover that.
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> Need to double check if each dac node needs a separate compatible, so you would maybe populate
> >>>>>>>>>>>>>>> a platform data to be shared with the child nodes, which would be a separate driver.
> >>>>>>>>>>>>>>> (not sure if it would make sense to mix and match ad5529r-16 and ad5529r-12).
> >>>>>>>>>>>>>> Hi Rodrigo,
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>> Thank you for looking at this.
> >>>>>>>>>>>>>>
> >>>>>>>>>>>>>> For now, I would prefer to keep the binding scoped to a single AD5529R device instance. The current
> >>>>>>>>>>>>>> hardware/use case we have only needs one device node and the driver is written around that model as well.
> >>>>>>>>>>>>>> While the device addressing pins could allow multi-device topology, we do not have an actual platform using
> >>>>>>>>>>>>>> that configuration at the moment, so I would prefer not to introduce an extra parent/child binding structure
> >>>>>>>>>>>>>> speculatively without a validating use case.
> >>>>>>>>>>>>> Interesting feature - kind of similar to address control on a typical i2c bus device, or
> >>>>>>>>>>>>> looking at it another way a kind of distributed SPI mux.
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Challenge of a binding is we need to anticipate the future. So I think we do need something
> >>>>>>>>>>>>> like Rodrigo is suggesting even if we only (for now) support a single instance in the driver.
> >>>>>>>>>>>>> That would leave the path open to supporting the addressing at a later date.
> >>>>>>>>>>>>> An alternative might be to look at it like a chained device setup. In those we pretend there
> >>>>>>>>>>>>> is just one device with a lot of channels etc. The snag is that here things are more loosely
> >>>>>>>>>>>>> coupled whereas for those devices it tends to be you have to read / write the same register
> >>>>>>>>>>>>> in all devices in the chain as one big SPI message.
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> +CC Mark Brown as he may know of some precedence for this feature. For his reference..
> >>>>>>>>>>>>> - Each of these device has 2 ID pins. The SPI transfers have to contain the 2 bit
> >>>>>>>>>>>>> value that matches that or they are ignored. Thus a single bus + 1 chip select can
> >>>>>>>>>>>>> be used to talk to 4 devices. Question is what that looks like in device tree + I guess
> >>>>>>>>>>>>> longer term how to support it cleanly in SPI.
> >>>>>>>>>>> I'd swear I have seen this before, from some Microchip devices. Let me
> >>>>>>>>>>> see if I can find what I am thinking of...
> >>>>>>>>>>
> >>>>>>>>>> microchip,mcp3911 and microchip,mcp3564 both seem to do this with
> >>>>>>>>>> slightly different properties.
> >>>>>>>>>>
> >>>>>>>>>> microchip,device-addr:
> >>>>>>>>>> description: Device address when multiple MCP3911 chips are present on the same SPI bus.
> >>>>>>>>>> $ref: /schemas/types.yaml#/definitions/uint32
> >>>>>>>>>> enum: [0, 1, 2, 3]
> >>>>>>>>>> default: 0
> >>>>>>>>>>
> >>>>>>>>>> and
> >>>>>>>>>>
> >>>>>>>>>>
> >>>>>>>>>> microchip,hw-device-address:
> >>>>>>>>>> $ref: /schemas/types.yaml#/definitions/uint32
> >>>>>>>>>> minimum: 0
> >>>>>>>>>> maximum: 3
> >>>>>>>>>> description:
> >>>>>>>>>> The address is set on a per-device basis by fuses in the factory,
> >>>>>>>>>> configured on request. If not requested, the fuses are set for 0x1.
> >>>>>>>>>> The device address is part of the device markings to avoid
> >>>>>>>>>> potential confusion. This address is coded on two bits, so four possible
> >>>>>>>>>> addresses are available when multiple devices are present on the same
> >>>>>>>>>> SPI bus with only one Chip Select line for all devices.
> >>>>>>>>>> Each device communication starts by a CS falling edge, followed by the
> >>>>>>>>>> clocking of the device address (BITS[7:6] - top two bits of COMMAND BYTE
> >>>>>>>>>> which is first one on the wire).
> >>>>>>>>>>
> >>>>>>>>>> This sounds exactly like the sort of feature that you're dealing with
> >>>>>>>>>> here?
> >>>>>>>>>>
> >>>>>>>>> The core idea yes but for this chip, things are a bit more annoying (but
> >>>>>>>>> Janani can correct me if I'm wrong). Here, each device can, in theory,
> >>>>>>>>> have it's own supplies, pins and at the very least, channels with maybe
> >>>>>>>>> different scales. That is why Janani is proposing dac nodes. Given I
> >>>>>>>>> honestly don't like much of that "adi,ad5529r-bus" compatible I wondered
> >>>>>>>>> about solving this at the spi level.
> >>>>>>>>>
> >>>>>>>>> Ah and to make it more annoying, we can also mix 12 and 16 bits variants
> >>>>>>>>> together in the same bus.
> >>>>>>>> I'm definitely missing something, because that property for the
> >>>>>>>> microchip devices is not impacted what else is on the bus. AFAICT, you
> >>>>>>>> could have an mcp3911 and an mcp3564 on the same bus even though both
> >>>>>>>> are completely different devices with different drivers. They have
> >>>>>>>> individual device nodes and their own supplies etc etc. These aren't
> >>>>>>>> per-channel properties on an adc or dac, they're per child device on a
> >>>>>>>> spi bus.
> >>>>>>> Maybe I'm the one missing something :). IIRC, spi would not allow two
> >>>>>>> devices on the same CS right? Because for this chip we would need
> >>>>>>> something like:
> >>>>>>>
> >>>>>>> spi {
> >>>>>>> dac@0 {
> >>>>>>> reg = <0>;
> >>>>>>> adi,pin-id = <0>;
> >>>>>>> };
> >>>>>>>
> >>>>>>> dac@1 {
> >>>>>>> reg = <0>; // which seems already problematic?
> >>>>>>> adi,pin-id <1>;
> >>>>>>> };
> >>>>>>>
> >>>>>>> ...
> >>>>>>>
> >>>>>>> //up to 4
> >>>>>>> };
> >>>>>> Yeah. It's not clear to me how that works for the microchip devices
> >>>>>> (I suspect it doesn't!)
> >>>>>>
> >>>>>> Just thinking as I type, but could we do something a bit nasty with
> >>>>>> a gpio mux that doesn't actually switch but represents the GPIO being
> >>>>>> shared? Given this is all tied to the spi bus that should all happen
> >>>>>> under serializing locks.
> >>>>>>
> >>>>>> Agreed though that this would be nicer as an SPI thing that let
> >>>>>> us specify that a single CS is share by multiple devices and their
> >>>>>> is some other signal acting to select which one we are talking to.
> >>>>>>
> >>>>> If the device-addressing on the same chip-select is to be handled
> >>>>> by the spi framework, wouldn't we lose device-specific features?
> >>>>>
> >>>>> I understand that this multi-device feature is there mostly to extend the
> >>>>> channel count from 16 to 32, 48 or 64. I suppose the command:
> >>>>>
> >>>>> "MULTI DEVICE SW LDAC MODE"
> >>>>>
> >>>>> exists so that software can update channel values accross multiple devices.
> >>>> Right! You do have a point! I agree the main driver for a feature like
> >>>> this is likely to extend the channel count and effectively "aggregate"
> >>>> devices.
> >>>>
> >>>> But I would say that even with the spi solution the MULTI DEVICE stuff
> >>>> should be doable (as we still need a sort of adi,pin-id property).
> >>> I don't think we can have something like an IIO buffer shared by multiple
> >>> devices. Synchronizing separate devices would be doable with proper hardware
> >>> support for this (probably involving an FGPA).
> >> True!
> >>
> >>>
> >>>> But yes, I do feel that the whole feature is for aggregation so seeing
> >>>> one device with 32 channels is the expectation here? Rather than seeing
> >>>> two devices with 16 channels.
> >>> Yes, I think aggregation is the whole point there... so that the IIO driver
> >>> is multi-device-aware.
> >> Which makes me feel that different pins per device might be possible
> >> from an HW point of view but does not make much sense. For example, for
> >> the buffer example I would expect LDAC to be shared between all the
> >> devices.
> >>
> >> - Nuno Sá
> > I think I mentioned this on a previous revision, but I still think the
> > simplest way to go about it would be to assume that all chips treated
> > as an aggregate device have everything wired in parallel and just add
> > support for per-chip wiring on an as-needed basis. This is how we have
> > handled daisy-chained devices so far.
>
> Hi David,
>
> One thing about this approach is that is does not cover a combination of 12 and 16 bit parts in the chain,
> since the compatible string would be at the top level and apply to all chips. To handle this without per chip child nodes or per-chip compatible,
> I propose an "adi, resolution" property as an integer array, indexed by the device position:
>
To me mixed parts, smells like a case that we will probably never see. If
a customer actually has a design doing that we can add optional dt
bindings at that time.
So I'd stick to separate compatibles.
>
> dac@0 {
> compatible = "adi,ad5529r";
> reg = <0>;
> adi,device-addrs = <0 1>;
> adi,resolution = <16 12>; /* per-chip, indexed by position */
> reset-gpios = <&gpio0 87 GPIO_ACTIVE_LOW>;
> vdd-supply = <&vdd_reg>;
> hvdd-supply = <&hvdd_reg>;
>
> channel@0 { reg = <0>; adi,output-range-microvolt = <0 5000000>; };
> channel@16 { reg = <16>; adi,output-range-microvolt = <0 40000000>; };
> };
>
>
> 1) This follows the daisy-chain/aggregated model as you suggested, exposing N*16 channels as a single IIO device.
> 2) Keeps the binding flat- no phantom compatible at a parent bus node, no per-chip child nodes.
> 3) Enables a 12 bit + 16 bit device combination in the chain, without needing a per-chip compatible.
> 4) adi, device-addrs specifies the HW address, allowing the driver to encode it into the SPI frame.
> 5) Supplies and GPIOs remain simple- assuming parallel wiring across all chips.
>
> Jonathan, you had earlier suggested using separate compatibles
> (adi,ad5529r-16 and adi,ad5529r-12) to handle the
> resolution difference.
> However, with the aggregated flat binding model,
> separate per-chip compatibles would require child nodes which brings
> back the phantom compatible problem at the parent level. The
> adi,resolution array is intended as an alternative that achieves the
> same goal-expressing per-chip resolution, without needing a per-chip
> compatible or child node structure.
>
> Does this look reasonable?
>
> Best Regards,
> Janani Sunil
>
>
^ permalink raw reply
* [RFC 10/12] i2c: acpi: Also register ACPI i2c_clients for adapters with a secondary ACPI fwnode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
In DT-ACPI hybrid mode the primary fwnode of an i2c_adapter will be a DT/of
node and the secondary fwnode may point to an ACPI fwnode.
i2c_acpi_register_devices() exits early if has_acpi_companion() returns
false and has_acpi_companion() only checks the primary fwnode. Switch to
is_acpi_device_node_any() to also check the secondary.
The rest of the code to register ACPI i2c_clients uses
device_match_acpi_handle() which already handles this correctly.
Also adjust i2c_acpi_find_bus_speed() to use to_acpi_device_node_any()
to als make it work in DT-ACPI hybrid mode.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/i2c/i2c-core-acpi.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/i2c-core-acpi.c b/drivers/i2c/i2c-core-acpi.c
index 28c0e4884a7f..995bd88ad09f 100644
--- a/drivers/i2c/i2c-core-acpi.c
+++ b/drivers/i2c/i2c-core-acpi.c
@@ -322,7 +322,7 @@ void i2c_acpi_register_devices(struct i2c_adapter *adap)
struct acpi_device *adev;
acpi_status status;
- if (!has_acpi_companion(&adap->dev))
+ if (!is_acpi_device_node_any(adap->dev.fwnode))
return;
status = acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
@@ -413,13 +413,15 @@ u32 i2c_acpi_find_bus_speed(struct device *dev)
{
struct i2c_acpi_lookup lookup;
struct i2c_board_info dummy;
+ struct acpi_device *adev;
acpi_status status;
- if (!has_acpi_companion(dev))
+ adev = to_acpi_device_node_any(dev->fwnode);
+ if (!adev)
return 0;
memset(&lookup, 0, sizeof(lookup));
- lookup.search_handle = ACPI_HANDLE(dev);
+ lookup.search_handle = adev->handle;
lookup.min_speed = UINT_MAX;
lookup.info = &dummy;
lookup.index = -1;
--
2.54.0
^ permalink raw reply related
* [RFC 12/12] arm64: dts: qcom: x1e78100-thinkpad-t14s: Move keyb and touchpad to ACPI enumeration
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
Add acpi-path properties for DT-ACPI hybrid mode and remove the keyboard
and touchpad description switching to relying on ACPI to enumerate these.
Also drop the clock-frequency this is also provided by ACPI now.
FIXME: Needs DT-bindings patch as pre-req
Note this depends on these 2 patch-series for working PDC support on Hamoa:
https://lore.kernel.org/linux-arm-msm/20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com/
https://lore.kernel.org/linux-arm-msm/20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com/
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
.../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 59 +------------------
1 file changed, 3 insertions(+), 56 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi
index 2fc01e8e8c04..a73576ec238d 100644
--- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi
@@ -1017,57 +1017,8 @@ &gpu_zap_shader {
};
&i2c0 {
- clock-frequency = <400000>;
-
- pinctrl-0 = <&qup_i2c0_data_clk>, <&tpad_default>;
- pinctrl-names = "default";
-
+ acpi-path = "\\_SB.I2C1";
status = "okay";
-
- /* ELAN06E2 or ELAN06E3 */
- touchpad@15 {
- compatible = "hid-over-i2c";
- reg = <0x15>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
-
- vdd-supply = <&vreg_misc_3p3>;
- vddl-supply = <&vreg_l12b_1p2>;
-
- wakeup-source;
- };
-
- /* SYNA8022 or SYNA8024 */
- touchpad@2c {
- compatible = "hid-over-i2c";
- reg = <0x2c>;
-
- hid-descr-addr = <0x20>;
- interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
-
- vdd-supply = <&vreg_misc_3p3>;
- vddl-supply = <&vreg_l12b_1p2>;
-
- wakeup-source;
- };
-
- /* ELAN06F1 or SYNA06F2 */
- keyboard@3a {
- compatible = "hid-over-i2c";
- reg = <0x3a>;
-
- hid-descr-addr = <0x1>;
- interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
-
- vdd-supply = <&vreg_misc_3p3>;
- vddl-supply = <&vreg_l15b_1p8>;
-
- pinctrl-0 = <&kybd_default>;
- pinctrl-names = "default";
-
- wakeup-source;
- };
};
&i2c3 {
@@ -1598,6 +1549,8 @@ wcd_tx: codec@0,3 {
};
&tlmm {
+ acpi-path = "\\_SB.GIO0";
+
gpio-reserved-ranges = <34 2>, /* Unused */
<44 4>, /* SPI (TPM) */
<72 2>, /* Secure EC I2C connection (?) */
@@ -1655,12 +1608,6 @@ hdmi_hpd_default: hdmi-hpd-default-state {
bias-disable;
};
- tpad_default: tpad-default-state {
- pins = "gpio3";
- function = "gpio";
- bias-pull-up;
- };
-
nvme_reg_en: nvme-reg-en-state {
pins = "gpio18";
function = "gpio";
--
2.54.0
^ permalink raw reply related
* [RFC 11/12] i2c: qcom-geni: Fall back to i2c_acpi_find_bus_speed()
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
Fall back to i2c_acpi_find_bus_speed() to get the bus-frequency if there
is no "clock-frequency" property to get the bus-frequency from ACPI if
available there.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/i2c/busses/i2c-qcom-geni.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 2138fcffdaf3..97a538cd9455 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -1024,8 +1024,14 @@ static int geni_i2c_probe(struct platform_device *pdev)
ret = device_property_read_u32(dev, "clock-frequency",
&gi2c->clk_freq_out);
if (ret) {
- dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
- gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
+ ret = i2c_acpi_find_bus_speed(dev);
+ if (ret) {
+ dev_info(dev, "Using ACPI Bus frequency: %d\n", ret);
+ gi2c->clk_freq_out = ret;
+ } else {
+ dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
+ gi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;
+ }
}
gi2c->irq = platform_get_irq(pdev, 0);
--
2.54.0
^ permalink raw reply related
* [RFC 07/12] ACPI: Make device_match_acpi_handle() also check the secondary fwnode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
In DT-ACPI hybrid mode the secondary fwnode of a device may point to
an ACPI fwnode instead of the primary.
device_match_acpi_handle() is used to find parent GPIO/I2C/SPI controllers
when resolving ACPI device resources from (_CRS) in this case we always
want to also check the secondary fwnode to help find the parent.
Modify the existing device_match_acpi_handle() function to also check
the secondary fwnode.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/base/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index bd2ddf2aab50..2573253f5815 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -5357,7 +5357,9 @@ EXPORT_SYMBOL(device_match_acpi_dev);
int device_match_acpi_handle(struct device *dev, const void *handle)
{
- return handle && ACPI_HANDLE(dev) == handle;
+ struct acpi_device *adev = to_acpi_device_node_any(dev->fwnode);
+
+ return handle && adev && adev->handle == handle;
}
EXPORT_SYMBOL(device_match_acpi_handle);
--
2.54.0
^ permalink raw reply related
* [RFC 09/12] pinctrl: qcom: Add support for WoA ACPI tables virtual TLMM pin numbers
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
The ACPI tabled on Windows on ARM laptops use TLMM pin numbers outside of
the actual TLMM pin number range. These are a rather convoluted way to let
the Windows Qualcomm GPIO driver now to use the PDC for some pins because
these are wakeup sources.
This adds support for translating the magic Windows virtual GPIOs for these
back to a regular TLMM GPIO so that ACPI described devices using these
virtual GPIOs can work with Linux.
For now this code only tries to do this mapping when booting in DT-ACPI
hybrid mode which is only used on some WoA devices so this should not
impact any other use-cases.
The new functions use woa_acpi in their name to make clear that these
are for dealing with the ACPI tables found on WoA devices, rather then
ACPI tables found on other devices, like ARM system ready devices which
also use ACPI.
Note that simply mapping these virtual GPIOs back to TLMM pin numbers can
safely be done on Linux, because Linux always uses the PDC for GPIO IRQs
where possible.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/pinctrl/qcom/Makefile | 4 +-
drivers/pinctrl/qcom/pinctrl-msm-acpi.c | 196 ++++++++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-msm.c | 47 +++++-
drivers/pinctrl/qcom/pinctrl-msm.h | 35 +++++
4 files changed, 278 insertions(+), 4 deletions(-)
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm-acpi.c
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 84bda3ada874..9029d99190d2 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
# Qualcomm pin control drivers
-obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
+obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm-core.o
+pinctrl-msm-core-y := pinctrl-msm.o
+pinctrl-msm-core-$(CONFIG_ACPI) += pinctrl-msm-acpi.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm-acpi.c b/drivers/pinctrl/qcom/pinctrl-msm-acpi.c
new file mode 100644
index 000000000000..df180fd04749
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm-acpi.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ACPI GPIO lookup handling for WoA (Windows on ARM) laptop ACPI tables.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/acpi.h>
+#include <linux/device.h>
+#include <linux/dev_printk.h>
+#include <linux/gpio/driver.h>
+#include <linux/list.h>
+#include <linux/math.h>
+#include "pinctrl-msm.h"
+
+#define MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK 64
+#define MSM_GPIO_WOA_ACPI_IRQ_OFFSET 32
+#define MSM_GPIO_WOA_ACPI_INVALID_GPIO ~0U
+#define MSM_GPIO_WOA_ACPI_MAX_PDC_RANGES 16
+
+#define PDC_RANGE_PIN_BASE 0
+#define PDC_RANGE_GIC_BASE 1
+#define PDC_RANGE_COUNT 2
+#define PDC_RANGE_ELEMENTS 3
+
+/**
+ * struct msm_gpio_woa_acpi_parse_data - Data for parsing WoA ACPI GPIO ctl resources
+ * @chip: gpiochip handle
+ * @data: Data for mapping virtual WoA ACPI PDC IRQ GPIOs
+ * @soc_data: Reference to soc_data of platform specific data
+ * @pdc_range: PDC GIC to PDC map ranges
+ * @pdc_range_count: PDC GIC to PDC map range-count
+ */
+struct msm_gpio_woa_acpi_parse_data {
+ struct gpio_chip *chip;
+ struct msm_gpio_woa_acpi_data *data;
+ const struct msm_pinctrl_soc_data *soc_data;
+ u32 pdc_range[MSM_GPIO_WOA_ACPI_MAX_PDC_RANGES][PDC_RANGE_ELEMENTS];
+ unsigned int pdc_range_count;
+};
+
+/*
+ * Mapping does not need translating the acpi_resource in to a regular resoure
+ * and adding it to the resource list. Always return 1 to disable this.
+ */
+static int msm_gpio_woa_acpi_resource(struct acpi_resource *ares, void *_parse)
+{
+ struct msm_gpio_woa_acpi_parse_data *parse = _parse;
+ const struct msm_pinctrl_soc_data *soc_data = parse->soc_data;
+ struct msm_gpio_woa_acpi_data *data = parse->data;
+ struct gpio_chip *chip = parse->chip;
+ u32 gic_irq, pdc_pin;
+
+ if (ares->type != ACPI_RESOURCE_TYPE_EXTENDED_IRQ ||
+ ares->data.extended_irq.interrupt_count != 1)
+ return 1;
+
+ if (data->nmap == MSM_GPIO_WOA_ACPI_MAX_VIRT_GPIOS) {
+ dev_err(chip->parent, "ACPI resources contain more than %d IRQs\n",
+ MSM_GPIO_WOA_ACPI_MAX_VIRT_GPIOS);
+ return 1;
+ }
+
+ /*
+ * Windows ACPI tables divide GPIOs into banks of 64 pins with one IRQ
+ * per bank. The resources start with listing the real TLMM IRQ for
+ * as many banks as are necessary to cover the real GPIOs. The Windows
+ * virtual GPIO indexes skip these banks, mark them as unavailable.
+ */
+ if (data->nmap < DIV_ROUND_UP(chip->ngpio, MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK)) {
+ data->map[data->nmap++] = MSM_GPIO_WOA_ACPI_INVALID_GPIO;
+ return 1;
+ }
+
+ /*
+ * Use the "pdc-ranges" property on the PDC to translate the GIC IRQ
+ * from the acpi_resource to a PDC pin.
+ */
+ gic_irq = ares->data.extended_irq.interrupts[0] - MSM_GPIO_WOA_ACPI_IRQ_OFFSET;
+ pdc_pin = MSM_GPIO_WOA_ACPI_INVALID_GPIO;
+ for (unsigned int i = 0; i < parse->pdc_range_count; i++) {
+ u32 gic_base = parse->pdc_range[i][PDC_RANGE_GIC_BASE];
+ u32 count = parse->pdc_range[i][PDC_RANGE_COUNT];
+ if (gic_irq >= gic_base && gic_irq < (gic_base + count)) {
+ pdc_pin = parse->pdc_range[i][PDC_RANGE_PIN_BASE] +
+ gic_irq - gic_base;
+ break;
+ }
+ }
+ if (pdc_pin == MSM_GPIO_WOA_ACPI_INVALID_GPIO)
+ goto no_map;
+
+ /* Use wakeirq-map to map PDC pin to TLMM pin */
+ for (unsigned int i = 0; i < soc_data->nwakeirq_map; i++) {
+ if (soc_data->wakeirq_map[i].wakeirq == pdc_pin) {
+ data->map[data->nmap++] = soc_data->wakeirq_map[i].gpio;
+ return 1;
+ }
+ }
+
+no_map:
+ dev_warn(chip->parent, "Cannot map GIC IRQ %u to TLMM pin\n", gic_irq);
+ data->map[data->nmap++] = MSM_GPIO_WOA_ACPI_INVALID_GPIO;
+ return 1;
+}
+
+int msm_gpio_woa_acpi_init(struct gpio_chip *chip, struct msm_gpio_woa_acpi_data *data,
+ const struct msm_pinctrl_soc_data *soc_data)
+{
+ struct msm_gpio_woa_acpi_parse_data parse;
+ struct fwnode_handle *fwnode;
+ struct device_node *pdc_np;
+ LIST_HEAD(resources);
+ unsigned int ngpio;
+ int ret;
+
+ /* WoA ACPI tables are only used in DT-ACPI hybrid mode */
+ fwnode = chip->parent->fwnode;
+ if (!is_of_node(fwnode) || !is_acpi_device_node(fwnode->secondary))
+ return 0;
+
+ parse.chip = chip;
+ parse.data = data;
+ parse.soc_data = soc_data;
+
+ /* Get PDC ranges, the PDC is the TLMM's wakeup-parent. */
+ pdc_np = of_parse_phandle(chip->parent->of_node, "wakeup-parent", 0);
+ if (!pdc_np)
+ return 0;
+
+ ret = of_property_count_elems_of_size(pdc_np, "qcom,pdc-ranges", sizeof(u32));
+ if (ret <= 0 || ret % PDC_RANGE_ELEMENTS ||
+ ret > (MSM_GPIO_WOA_ACPI_MAX_PDC_RANGES * PDC_RANGE_ELEMENTS))
+ goto err_pdc_ranges;
+
+ parse.pdc_range_count = ret / PDC_RANGE_ELEMENTS;
+ ret = of_property_read_u32_array(pdc_np, "qcom,pdc-ranges",
+ &parse.pdc_range[0][0], ret);
+ if (ret)
+ goto err_pdc_ranges;
+
+ ret = acpi_dev_get_resources(to_acpi_device_node(fwnode->secondary), &resources,
+ msm_gpio_woa_acpi_resource, &parse);
+ if (ret < 0)
+ return ret;
+
+ acpi_dev_free_resource_list(&resources);
+
+ ngpio = data->nmap * MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK + 1;
+ chip->ngpio = max(chip->ngpio, ngpio);
+
+ for (unsigned int i = 0; i < data->nmap; i++) {
+ if (data->map[i] != MSM_GPIO_WOA_ACPI_INVALID_GPIO) {
+ /* TODO lower log level to dev_dbg() */
+ dev_info(chip->parent, "mapped GPIO 0x%03x to TLMM pin %u\n",
+ i * MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK, data->map[i]);
+ }
+ }
+
+ return 0;
+
+err_pdc_ranges:
+ dev_err(chip->parent, "Error invalid pdc-ranges\n");
+ return 0; /* Continue without mapping */
+}
+
+void msm_gpio_woa_acpi_valid_mask(struct gpio_chip *chip,
+ struct msm_gpio_woa_acpi_data *data,
+ unsigned long *valid_mask,
+ unsigned int soc_ngpio)
+{
+ /* First mark all virtual ACPI PDC GPIOs (if any) as invalid */
+ bitmap_clear(valid_mask, soc_ngpio, chip->ngpio - soc_ngpio);
+
+ /*
+ * WoA ACPI tables list 1 Interrupt resource per PDC pin and use
+ * a 1 interrupt per bank model. So each PDC pin gets its own bank,
+ * with only pin 0 of that bank used for that PDC pin.
+ */
+ for (unsigned int i = 0; i < data->nmap; i++) {
+ if (data->map[i] != MSM_GPIO_WOA_ACPI_INVALID_GPIO)
+ set_bit(i * MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK, valid_mask);
+ }
+}
+
+unsigned int msm_gpio_woa_acpi_map(struct msm_gpio_woa_acpi_data *data, unsigned int offset)
+{
+ unsigned int bank = offset / MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK;
+
+ /* msm_gpio_woa_acpi_valid_mask() should ensure this never happens */
+ if (WARN_ON(offset % MSM_GPIO_WOA_ACPI_GPIOS_PER_BANK || bank >= data->nmap ||
+ data->map[bank] == MSM_GPIO_WOA_ACPI_INVALID_GPIO))
+ return 0;
+
+ return data->map[bank];
+}
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index f780bab51d9c..60ba0da95634 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -45,6 +45,7 @@
* @pctrl: pinctrl handle.
* @chip: gpiochip handle.
* @desc: pin controller descriptor
+ * @woa_acpi: data for mapping virtual WoA ACPI PDC IRQ GPIOs
* @irq: parent irq for the TLMM irq_chip.
* @intr_target_use_scm: route irq to application cpu using scm calls
* @lock: Spinlock to protect register resources as well
@@ -64,6 +65,7 @@ struct msm_pinctrl {
struct pinctrl_dev *pctrl;
struct gpio_chip chip;
struct pinctrl_desc desc;
+ struct msm_gpio_woa_acpi_data woa_acpi;
int irq;
@@ -553,6 +555,16 @@ static const struct pinconf_ops msm_pinconf_ops = {
.pin_config_group_set = msm_config_group_set,
};
+static unsigned int msm_gpio_map(struct gpio_chip *chip, unsigned int offset)
+{
+ struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
+
+ if (offset < pctrl->soc->ngpios)
+ return offset;
+
+ return msm_gpio_woa_acpi_map(&pctrl->woa_acpi, offset);
+}
+
static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
const struct msm_pingroup *g;
@@ -560,6 +572,8 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
unsigned long flags;
u32 val;
+ offset = msm_gpio_map(chip, offset);
+
g = &pctrl->soc->groups[offset];
raw_spin_lock_irqsave(&pctrl->lock, flags);
@@ -580,6 +594,8 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
unsigned long flags;
u32 val;
+ offset = msm_gpio_map(chip, offset);
+
g = &pctrl->soc->groups[offset];
raw_spin_lock_irqsave(&pctrl->lock, flags);
@@ -606,6 +622,8 @@ static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
const struct msm_pingroup *g;
u32 val;
+ offset = msm_gpio_map(chip, offset);
+
g = &pctrl->soc->groups[offset];
val = msm_readl_ctl(pctrl, g);
@@ -620,6 +638,8 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
u32 val;
+ offset = msm_gpio_map(chip, offset);
+
g = &pctrl->soc->groups[offset];
val = msm_readl_io(pctrl, g);
@@ -633,6 +653,8 @@ static int msm_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
unsigned long flags;
u32 val;
+ offset = msm_gpio_map(chip, offset);
+
g = &pctrl->soc->groups[offset];
raw_spin_lock_irqsave(&pctrl->lock, flags);
@@ -717,10 +739,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
+ struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned gpio = chip->base;
unsigned i;
- for (i = 0; i < chip->ngpio; i++, gpio++)
+ for (i = 0; i < pctrl->soc->ngpios; i++, gpio++)
msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
}
@@ -738,6 +761,10 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
const int *reserved = pctrl->soc->reserved_gpios;
u16 *tmp;
+ /* WOA ACPI handles virtual PDC GPIO range, only handle real GPIOs here */
+ ngpios = pctrl->soc->ngpios;
+ msm_gpio_woa_acpi_valid_mask(gc, &pctrl->woa_acpi, valid_mask, ngpios);
+
/* Remove driver-provided reserved GPIOs from valid_mask */
if (reserved) {
for (i = 0; reserved[i] >= 0; i++) {
@@ -1046,6 +1073,10 @@ static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc,
const struct msm_pingroup *g;
int i;
+ /* WOA ACPI handles virtual PDC GPIO range, only handle real GPIOs here */
+ ngpios = pctrl->soc->ngpios;
+ msm_gpio_woa_acpi_valid_mask(gc, &pctrl->woa_acpi, valid_mask, ngpios);
+
for (i = 0; i < ngpios; i++) {
g = &pctrl->soc->groups[i];
@@ -1387,6 +1418,9 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
if (pctrl->soc->reserved_gpios)
return true;
+ if (pctrl->chip.ngpio != pctrl->soc->ngpios)
+ return true;
+
return device_property_count_u16(pctrl->dev, "gpios") > 0;
}
@@ -1428,8 +1462,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;
chip->owner = THIS_MODULE;
- if (msm_gpio_needs_valid_mask(pctrl))
- chip->init_valid_mask = msm_gpio_init_valid_mask;
np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
if (np) {
@@ -1450,6 +1482,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
}
}
+ ret = msm_gpio_woa_acpi_init(chip, &pctrl->woa_acpi, pctrl->soc);
+ if (ret)
+ return ret;
+
+ if (msm_gpio_needs_valid_mask(pctrl))
+ chip->init_valid_mask = msm_gpio_init_valid_mask;
+
girq = &chip->irq;
gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip);
girq->parent_handler = msm_gpio_irq_handler;
@@ -1463,6 +1502,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
girq->handler = handle_bad_irq;
girq->parents[0] = pctrl->irq;
girq->init_valid_mask = msm_gpio_irq_init_valid_mask;
+ if (pctrl->chip.ngpio != pctrl->soc->ngpios)
+ girq->child_offset_to_irq = msm_gpio_map;
ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
if (ret) {
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 4fbff61de6bb..3a8a55a6d8c1 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -10,6 +10,7 @@
#include <linux/pinctrl/pinctrl.h>
+struct gpio_chip;
struct platform_device;
struct pinctrl_pin_desc;
@@ -181,9 +182,43 @@ struct msm_pinctrl_soc_data {
unsigned int egpio_func;
};
+#define MSM_GPIO_WOA_ACPI_MAX_VIRT_GPIOS 32
+
+/**
+ * struct msm_gpio_woa_acpi_data - Data for mapping virtual WoA ACPI PDC IRQ GPIOs
+ * @map: Map to translate virtual ACPI GPIO offsets to TLMM pin offsets
+ * @nmap: Number of valid entried in @map
+ */
+struct msm_gpio_woa_acpi_data {
+ unsigned int map[MSM_GPIO_WOA_ACPI_MAX_VIRT_GPIOS];
+ unsigned int nmap;
+};
+
extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data);
+#ifdef CONFIG_ACPI
+int msm_gpio_woa_acpi_init(struct gpio_chip *chip, struct msm_gpio_woa_acpi_data *data,
+ const struct msm_pinctrl_soc_data *soc_data);
+void msm_gpio_woa_acpi_valid_mask(struct gpio_chip *chip,
+ struct msm_gpio_woa_acpi_data *data,
+ unsigned long *valid_mask,
+ unsigned int soc_ngpio);
+unsigned int msm_gpio_woa_acpi_map(struct msm_gpio_woa_acpi_data *data, unsigned int offset);
+#else
+static inline int
+msm_gpio_woa_acpi_init(struct gpio_chip *chip, struct msm_gpio_woa_acpi_data *data,
+ const struct msm_pinctrl_soc_data *soc_data)
+{ return 0; }
+static inline void msm_gpio_woa_acpi_valid_mask(struct gpio_chip *chip,
+ struct msm_gpio_woa_acpi_data *data,
+ unsigned long *valid_mask,
+ unsigned int soc_ngpio) { }
+static inline unsigned int
+msm_gpio_woa_acpi_map(struct msm_gpio_woa_acpi_data *data, unsigned int offset)
+{ return 0; }
#endif
+
+#endif /* ifndef __PINCTRL_MSM_H__ */
--
2.54.0
^ permalink raw reply related
* [RFC 08/12] irqchip/gic-v3: Always call acpi_set_irq_model()
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
The gic-v3 code used to only call acpi_set_irq_model() when the GIC is
enumerated through ACPI.
This causes problems for DT-ACPI hybrid mode, where the GIC might be
described in DT but then a driver using info from the ACPI tables might
call acpi_dev_get_irqresource(), which results in a NULL pointer deref
when acpi_set_irq_model() has not been called.
Always call acpi_set_irq_model() when CONFIG_ACPI is enabled to fix this.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/irqchip/irq-gic-v3.c | 29 ++++++++++++++++++++---------
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 99444a1b2ffa..2ccd04689a04 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1974,6 +1974,23 @@ static void gic_enable_nmi_support(void)
gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
}
+#ifdef CONFIG_ACPI
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
+{
+ return gsi_domain_handle;
+}
+
+static void gic_set_acpi_irq_model(struct fwnode_handle *handle)
+{
+ gsi_domain_handle = handle;
+ acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id);
+}
+#else
+static void gic_set_acpi_irq_model(struct fwnode_handle *handle) { }
+#endif
+
static int __init gic_init_bases(phys_addr_t dist_phys_base,
void __iomem *dist_base,
struct redist_region *rdist_regs,
@@ -2063,6 +2080,9 @@ static int __init gic_init_bases(phys_addr_t dist_phys_base,
gicv2m_init(handle, gic_data.domain);
}
+ /* Also do this when enumerated through DT for DT-ACPI hybrid mode */
+ gic_set_acpi_irq_model(handle);
+
return 0;
out_free:
@@ -2534,13 +2554,6 @@ static void __init gic_acpi_setup_kvm_info(void)
vgic_set_kvm_info(&gic_v3_kvm_info);
}
-static struct fwnode_handle *gsi_domain_handle;
-
-static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
-{
- return gsi_domain_handle;
-}
-
static int __init
gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
{
@@ -2588,8 +2601,6 @@ gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
if (err)
goto out_fwhandle_free;
- acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id);
-
if (static_branch_likely(&supports_deactivate_key))
gic_acpi_setup_kvm_info();
--
2.54.0
^ permalink raw reply related
* [RFC 06/12] ACPI: scan: Retry acpi_device_notify() in DT-ACPI hybrid mode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
of_platform_default_populate_init creates DT platform devices from
an arch_initcall(), so before acpi_scan_init() runs this causing
acpi_device_notify() to be unable to honor "acpi-path" properties
in DT-ACPI hybrid mode.
Re-call acpi_device_notify() at the end of scanning ACPI devices to
fix this up.
Note this relies on the driver which may use the bound ACPI fwnode
to only register after subsys_initcall(acpi_init) has run.
TODO: It is probably better to add an acpi_platform_device_pre_probe()
function and call that from drivers/base/platform.c:platform_probe() and
dot the setting of the secondary fwnode for platform-devices with
an "acpi-path" property there. Basically moving the "if (acpi_dt_hybrid)"
block in acpi_device_notify() to a new acpi_platform_device_pre_probe().
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/acpi/scan.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 4836286968e8..b305c03e8504 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -21,6 +21,7 @@
#include <linux/dmi.h>
#include <linux/dma-map-ops.h>
#include <linux/platform_data/x86/apple.h>
+#include <linux/platform_device.h>
#include <linux/pgtable.h>
#include <linux/crc32.h>
#include <linux/dma-direct.h>
@@ -2818,6 +2819,22 @@ static void __init acpi_get_spcr_uart_addr(void)
acpi_put_table((struct acpi_table_header *)spcr_ptr);
}
+static int acpi_scan_retry_of_acpi_binding(struct device *dev, void *data)
+{
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ const char *acpi_path;
+
+ /* Check primary fwnode is OF and secondary fwnode is not yet ACPI */
+ if (!is_of_node(fwnode) || is_acpi_device_node(fwnode->secondary))
+ return 0;
+
+ /* If there is an "acpi-path" property retry binding ACPI fwnode */
+ if (of_property_read_string(dev->of_node, "acpi-path", &acpi_path) == 0)
+ acpi_device_notify(dev);
+
+ return 0;
+}
+
static bool acpi_scan_initialized;
void __init acpi_scan_init(void)
@@ -2881,6 +2898,18 @@ void __init acpi_scan_init(void)
if (!acpi_gbl_reduced_hardware)
acpi_bus_scan_fixed();
+ /*
+ * of_platform_default_populate_init creates DT platform devices from
+ * an arch_initcall(), so before acpi_scan_init() runs this causing
+ * acpi_device_notify() to be unable to honor "acpi-path" properties
+ * in DT-ACPI hybrid mode. Re-call acpi_device_notify() to fix this up.
+ * Note this relies on the driver which may use the bound ACPI fwnode
+ * to only register after subsys_initcall(acpi_init) has run.
+ */
+ if (acpi_dt_hybrid)
+ bus_for_each_dev(&platform_bus_type, NULL, NULL,
+ acpi_scan_retry_of_acpi_binding);
+
acpi_turn_off_unused_power_resources();
acpi_scan_initialized = true;
--
2.54.0
^ permalink raw reply related
* [RFC 05/12] ACPI: glue: Implement setting secondary-fwnode for DT-ACPI hybrid mode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
In DT-ACPI hybrid mode devices are instantiated from device tree and
a device's primary firmware-node will normally be an of fwnode.
Add support to the ACPI glue code to check the new "acpi-path" DT property
and when this is set lookup the handle for the specified path and set
the secondary-fwnode of the device to point to the handle's ACPI fwnode.
Also create a firmware_node and physical_node links/entries as normal.
When e.g. an "acpi-path" property is specified for e.g. an i2c-adapter
then the normal ACPI i2c-client enumeration will happen for any ACPI
fwnodes with an I2CSerialBus resource pointing to the i2c-adapter, these
ACPI instantiated i2c_clients will have an ACPI fwnode as primary fwnode.
The normal acpi_device_notify[_remove]() paths will be used for these.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/acpi/glue.c | 70 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 60 insertions(+), 10 deletions(-)
diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c
index b1776809279d..fef450d5cb7d 100644
--- a/drivers/acpi/glue.c
+++ b/drivers/acpi/glue.c
@@ -225,6 +225,15 @@ static void acpi_physnode_link_name(char *buf, unsigned int node_id)
strcpy(buf, PHYSICAL_NODE_STRING);
}
+/* Like ACPI_COMPANION_SET() but set secondary fwnode if primary is an of_node */
+static void acpi_companion_set_any(struct device *dev, struct acpi_device *adev)
+{
+ if (is_of_node(dev->fwnode))
+ set_secondary_fwnode(dev, adev ? acpi_fwnode_handle(adev) : NULL);
+ else
+ set_primary_fwnode(dev, adev ? acpi_fwnode_handle(adev) : NULL);
+}
+
int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
{
struct acpi_device_physical_node *physical_node, *pn;
@@ -233,12 +242,12 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
unsigned int node_id;
int retval = -EINVAL;
- if (has_acpi_companion(dev)) {
+ if (is_acpi_device_node_any(dev->fwnode)) {
if (acpi_dev) {
dev_warn(dev, "ACPI companion already set\n");
return -EINVAL;
} else {
- acpi_dev = ACPI_COMPANION(dev);
+ acpi_dev = to_acpi_device_node_any(dev->fwnode);
}
}
if (!acpi_dev)
@@ -267,7 +276,7 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
dev_warn(dev, "Already associated with ACPI node\n");
kfree(physical_node);
- if (ACPI_COMPANION(dev) != acpi_dev)
+ if (to_acpi_device_node_any(dev->fwnode) != acpi_dev)
goto err;
put_device(dev);
@@ -285,8 +294,8 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
list_add(&physical_node->node, physnode_list);
acpi_dev->physical_node_count++;
- if (!has_acpi_companion(dev))
- ACPI_COMPANION_SET(dev, acpi_dev);
+ if (!is_acpi_device_node_any(dev->fwnode))
+ acpi_companion_set_any(dev, acpi_dev);
acpi_physnode_link_name(physical_node_name, node_id);
retval = sysfs_create_link(&acpi_dev->dev.kobj, &dev->kobj,
@@ -303,13 +312,14 @@ int acpi_bind_one(struct device *dev, struct acpi_device *acpi_dev)
mutex_unlock(&acpi_dev->physical_node_lock);
- if (acpi_dev->wakeup.flags.valid)
+ /* Don't set wakeup flag for devices where ACPI fwnode is secondary */
+ if (acpi_dev->wakeup.flags.valid && has_acpi_companion(dev))
device_set_wakeup_capable(dev, true);
return 0;
err:
- ACPI_COMPANION_SET(dev, NULL);
+ acpi_companion_set_any(dev, NULL);
put_device(dev);
acpi_dev_put(acpi_dev);
return retval;
@@ -318,7 +328,7 @@ EXPORT_SYMBOL_GPL(acpi_bind_one);
int acpi_unbind_one(struct device *dev)
{
- struct acpi_device *acpi_dev = ACPI_COMPANION(dev);
+ struct acpi_device *acpi_dev = to_acpi_device_node_any(dev->fwnode);
struct acpi_device_physical_node *entry;
if (!acpi_dev)
@@ -336,7 +346,7 @@ int acpi_unbind_one(struct device *dev)
acpi_physnode_link_name(physnode_name, entry->node_id);
sysfs_remove_link(&acpi_dev->dev.kobj, physnode_name);
sysfs_remove_link(&dev->kobj, "firmware_node");
- ACPI_COMPANION_SET(dev, NULL);
+ acpi_companion_set_any(dev, NULL);
/* Drop references taken by acpi_bind_one(). */
put_device(dev);
acpi_dev_put(acpi_dev);
@@ -354,6 +364,40 @@ void acpi_device_notify(struct device *dev)
struct acpi_device *adev;
int ret;
+ if (acpi_dt_hybrid && is_of_node(dev->fwnode)) {
+ const char *acpi_path;
+ acpi_status status;
+ acpi_handle handle;
+
+ ret = of_property_read_string(dev->of_node, "acpi-path", &acpi_path);
+ if (ret)
+ return;
+
+ status = acpi_get_handle(NULL, acpi_path, &handle);
+ if (ACPI_FAILURE(status))
+ goto err_hybrid;
+
+ adev = acpi_fetch_acpi_dev(handle);
+ if (!adev)
+ goto err_hybrid;
+
+ /*
+ * set_secondary_fwnode() + pass NULL to make this work for
+ * child devices which share the fwnode with their parent.
+ */
+ set_secondary_fwnode(dev, acpi_fwnode_handle(adev));
+ ret = acpi_bind_one(dev, NULL);
+ if (ret)
+ goto err_hybrid;
+
+ /* TODO change to dev_dbg() when DT-ACPI hybrid support is stable */
+ dev_info(dev, "Set secondary fwnode to acpi-path '%s'\n", acpi_path);
+ return;
+err_hybrid:
+ dev_warn(dev, "Failed to set ACPI fwnode for acpi-path '%s'\n", acpi_path);
+ return;
+ }
+
ret = acpi_bind_one(dev, NULL);
if (ret) {
struct acpi_bus_type *type = acpi_get_bus_type(dev);
@@ -400,8 +444,14 @@ void acpi_device_notify(struct device *dev)
void acpi_device_notify_remove(struct device *dev)
{
- struct acpi_device *adev = ACPI_COMPANION(dev);
+ struct acpi_device *adev;
+ if (acpi_dt_hybrid && is_of_node(dev->fwnode)) {
+ acpi_unbind_one(dev);
+ return;
+ }
+
+ adev = ACPI_COMPANION(dev);
if (!adev)
return;
--
2.54.0
^ permalink raw reply related
* [RFC 04/12] ACPI: Add helpers for dealing with ACPI fwnode as secondary fwnode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
In DT-ACPI hybrid mode in some cases code calling is_acpi_device_node() or
to_acpi_device_node() may also want the secondary fwnode to be used.
DT-ACPI hybrid mode is something which subsystems / drivers should opt-in
to, so it is undesirable to make existing helpers use the secondary fwnode.
Add new is_acpi_device_node_any() and to_acpi_device_node_any() helpers
which also use the secondary fwnode.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
drivers/acpi/property.c | 13 +++++++++++++
include/acpi/acpi_bus.h | 16 ++++++++++++++++
include/linux/acpi.h | 10 ++++++++++
3 files changed, 39 insertions(+)
diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c
index 8ee5a1f0eb48..fb555e50ce83 100644
--- a/drivers/acpi/property.c
+++ b/drivers/acpi/property.c
@@ -1775,6 +1775,19 @@ bool is_acpi_device_node(const struct fwnode_handle *fwnode)
}
EXPORT_SYMBOL(is_acpi_device_node);
+/* Like is_acpi_device_node() but also check the secondary fwnode */
+bool is_acpi_device_node_any(const struct fwnode_handle *fwnode)
+{
+ if (IS_ERR_OR_NULL(fwnode))
+ return false;
+
+ if (fwnode->ops == &acpi_device_fwnode_ops)
+ return true;
+
+ return is_acpi_device_node(fwnode->secondary);
+}
+EXPORT_SYMBOL(is_acpi_device_node_any);
+
bool is_acpi_data_node(const struct fwnode_handle *fwnode)
{
return !IS_ERR_OR_NULL(fwnode) && fwnode->ops == &acpi_data_fwnode_ops;
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index c41d9a7565cf..bfc3883765f1 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -515,6 +515,7 @@ extern const struct fwnode_operations acpi_data_fwnode_ops;
extern const struct fwnode_operations acpi_static_fwnode_ops;
bool is_acpi_device_node(const struct fwnode_handle *fwnode);
+bool is_acpi_device_node_any(const struct fwnode_handle *fwnode);
bool is_acpi_data_node(const struct fwnode_handle *fwnode);
static inline bool is_acpi_node(const struct fwnode_handle *fwnode)
@@ -532,6 +533,21 @@ static inline bool is_acpi_node(const struct fwnode_handle *fwnode)
NULL; \
})
+/* Like to_acpi_device_node() but also check the secondary fwnode */
+#define to_acpi_device_node_any(__fwnode) \
+ ({ \
+ typeof(__fwnode) __to_acpi_device_node_fwnode = __fwnode; \
+ \
+ IS_ERR_OR_NULL(__to_acpi_device_node_fwnode) ? NULL : \
+ is_acpi_device_node(__to_acpi_device_node_fwnode) ? \
+ container_of(__to_acpi_device_node_fwnode, \
+ struct acpi_device, fwnode) : \
+ is_acpi_device_node(__to_acpi_device_node_fwnode->secondary) ? \
+ container_of(__to_acpi_device_node_fwnode->secondary, \
+ struct acpi_device, fwnode) : \
+ NULL; \
+ })
+
#define to_acpi_data_node(__fwnode) \
({ \
typeof(__fwnode) __to_acpi_data_node_fwnode = __fwnode; \
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 67effb91fa98..bb84774f61df 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -865,11 +865,21 @@ static inline bool is_acpi_device_node(const struct fwnode_handle *fwnode)
return false;
}
+static inline bool is_acpi_device_node_any(const struct fwnode_handle *fwnode)
+{
+ return false;
+}
+
static inline struct acpi_device *to_acpi_device_node(const struct fwnode_handle *fwnode)
{
return NULL;
}
+static inline struct acpi_device *to_acpi_device_node_any(const struct fwnode_handle *fwnode)
+{
+ return NULL;
+}
+
static inline bool is_acpi_data_node(const struct fwnode_handle *fwnode)
{
return false;
--
2.54.0
^ permalink raw reply related
* [RFC 03/12] arm64: acpi: add acpi=hybrid support
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
By default when a non stub DT is given to the kernel when booting, ACPI
gets fully disabled.
Add support for selecting a new APCI-DT hybrid mode where the kernel
booting in DT mode still loads and parses the ACPI tables, without taking
any further actions like creating devices.
This will parse ACPI tables and populate /sys/firmware/acpi and
/sys/bus/acpi/devices, which can be useful to e.g. get an acpidump .
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
arch/arm64/include/asm/acpi.h | 2 +-
arch/arm64/kernel/acpi.c | 16 ++++++++++++----
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 3116bb872f47..8f8a0b9e49c3 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -76,10 +76,10 @@ typedef u64 phys_cpuid_t;
#define PHYS_CPUID_INVALID INVALID_HWID
#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
-#define acpi_dt_hybrid 0 /* No DT-ACPI hybrid mode on ARM64 */
extern int acpi_disabled;
extern int acpi_noirq;
extern int acpi_pci_disabled;
+extern int acpi_dt_hybrid;
static inline void disable_acpi(void)
{
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 06ab3a9da64b..9d2c42375afe 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -43,11 +43,14 @@ EXPORT_SYMBOL(acpi_disabled);
int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */
EXPORT_SYMBOL(acpi_pci_disabled);
+int acpi_dt_hybrid; /* disable ACPI-DT hybrid mode */
+
enum acpi_mode_t {
acpi_mode_unset,
acpi_mode_off,
acpi_mode_on,
acpi_mode_force,
+ acpi_mode_hybrid,
};
static enum acpi_mode_t param_acpi_mode __initdata;
@@ -65,6 +68,8 @@ static int __init parse_acpi(char *arg)
param_acpi_mode = acpi_mode_on;
else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */
param_acpi_mode = acpi_mode_force;
+ else if (strcmp(arg, "hybrid") == 0) /* ACPI-DT hybrid mode */
+ param_acpi_mode = acpi_mode_hybrid;
else if (strcmp(arg, "nospcr") == 0) /* disable SPCR as default console */
param_acpi_nospcr = true;
else
@@ -203,7 +208,7 @@ static int __init acpi_fadt_sanity_check(void)
void __init acpi_boot_table_init(void)
{
/*
- * When no ACPI mode (acpi=off|on|force) has been specified,
+ * When no ACPI mode (acpi=off|on|force|hybrid) has been specified,
* enable ACPI if the device tree is empty (it only has a /chosen
* node, and a /hypervisor node when running on Xen).
*/
@@ -230,6 +235,9 @@ void __init acpi_boot_table_init(void)
pr_err("Failed to init ACPI tables\n");
if (param_acpi_mode != acpi_mode_force)
disable_acpi();
+ } else if (param_acpi_mode == acpi_mode_hybrid) {
+ acpi_dt_hybrid = 1;
+ disable_acpi();
}
done:
@@ -257,10 +265,10 @@ void __init acpi_boot_table_init(void)
*/
acpi_parse_spcr(earlycon_acpi_spcr_enable,
!param_acpi_nospcr);
-
- if (IS_ENABLED(CONFIG_ACPI_BGRT))
- acpi_table_parse(ACPI_SIG_BGRT, acpi_parse_bgrt);
}
+
+ if ((!acpi_disabled || acpi_dt_hybrid) && IS_ENABLED(CONFIG_ACPI_BGRT))
+ acpi_table_parse(ACPI_SIG_BGRT, acpi_parse_bgrt);
}
static pgprot_t __acpi_get_writethrough_mem_attribute(void)
--
2.54.0
^ permalink raw reply related
* [RFC 02/12] arm64: acpi: Cleanup acpi=[on|off|force] handling
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
acpi=[on|off|force] are 3 values of a single "should ACPI be enabled"
setting. Instead of storing these in 3 separate booleans, introduce a new
acpi_mode_t enum for this and store these in a single param varialable.
This is a preparation patch for adding acpi=hybrid support to enable the
new DT-ACPI hybrid mode, which makes the kernel booting in DT mode still
load and parse the ACPI tables, without taking any further actions.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
arch/arm64/kernel/acpi.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 5891f92c2035..06ab3a9da64b 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -43,9 +43,14 @@ EXPORT_SYMBOL(acpi_disabled);
int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */
EXPORT_SYMBOL(acpi_pci_disabled);
-static bool param_acpi_off __initdata;
-static bool param_acpi_on __initdata;
-static bool param_acpi_force __initdata;
+enum acpi_mode_t {
+ acpi_mode_unset,
+ acpi_mode_off,
+ acpi_mode_on,
+ acpi_mode_force,
+};
+
+static enum acpi_mode_t param_acpi_mode __initdata;
static bool param_acpi_nospcr __initdata;
static int __init parse_acpi(char *arg)
@@ -55,11 +60,11 @@ static int __init parse_acpi(char *arg)
/* "acpi=off" disables both ACPI table parsing and interpreter */
if (strcmp(arg, "off") == 0)
- param_acpi_off = true;
+ param_acpi_mode = acpi_mode_off;
else if (strcmp(arg, "on") == 0) /* prefer ACPI over DT */
- param_acpi_on = true;
+ param_acpi_mode = acpi_mode_on;
else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */
- param_acpi_force = true;
+ param_acpi_mode = acpi_mode_force;
else if (strcmp(arg, "nospcr") == 0) /* disable SPCR as default console */
param_acpi_nospcr = true;
else
@@ -198,14 +203,14 @@ static int __init acpi_fadt_sanity_check(void)
void __init acpi_boot_table_init(void)
{
/*
- * Enable ACPI instead of device tree unless
- * - ACPI has been disabled explicitly (acpi=off), or
- * - the device tree is not empty (it has more than just a /chosen node,
- * and a /hypervisor node when running on Xen)
- * and ACPI has not been [force] enabled (acpi=on|force)
+ * When no ACPI mode (acpi=off|on|force) has been specified,
+ * enable ACPI if the device tree is empty (it only has a /chosen
+ * node, and a /hypervisor node when running on Xen).
*/
- if (param_acpi_off ||
- (!param_acpi_on && !param_acpi_force && !dt_is_stub()))
+ if (!param_acpi_mode)
+ param_acpi_mode = dt_is_stub() ? acpi_mode_on : acpi_mode_off;
+
+ if (param_acpi_mode == acpi_mode_off)
goto done;
/*
@@ -223,7 +228,7 @@ void __init acpi_boot_table_init(void)
*/
if (acpi_table_init() || acpi_fadt_sanity_check()) {
pr_err("Failed to init ACPI tables\n");
- if (!param_acpi_force)
+ if (param_acpi_mode != acpi_mode_force)
disable_acpi();
}
--
2.54.0
^ permalink raw reply related
* [RFC 01/12] ACPI: Introduce DT-ACPI hybrid mode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <20260623145225.143218-1-johannes.goede@oss.qualcomm.com>
ATM on platforms which support DT or ACPI as firmware interfaces ACPI gets
fully disabled when DT is in use.
In some cases it is interesting to at least parse the ACPI tables and
possibly also use parts of them.
One specific example of this is Windows on Arm laptops with Qualcomm
Snapdragon processors where Windows boots using information from the ACPI
tables but Linux uses a device-tree description of the hardware instead.
Since Windows is the factory OS, these DT descriptions need to be created
by hand.
Having the ACPI tables available at runtime allows the kernel to use some
information from these ACPI tables while still using device-tree as its
main information source.
Having the tables available at runtime can also help with creating and
improving these DT descriptions.
This patch prepares for a new DT-ACPI hybrid mode controlled by a new
acpi_dt_hybrid flag. When enabled this makes the kernel booting in DT
mode still load and parse the ACPI tables, without taking any further
actions like creating devices.
In this case the ACPI subsys will still parse ACPI tables and populate
/sys/firmware/acpi and /sys/bus/acpi/devices.
Note this patch itself is a no-op, since all the arch/*/include/asm/acpi.h
files define the new acpi_dt_hybrid variable to 0. All the added extra
"if (acpi_disabled)" checks are in paths which already check for this
earlier in the code-path. The new checks only come into play when
acpi_dt_hybrid is set to 1.
Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com>
---
arch/arm64/include/asm/acpi.h | 1 +
arch/loongarch/include/asm/acpi.h | 1 +
arch/riscv/include/asm/acpi.h | 3 ++-
arch/x86/include/asm/acpi.h | 1 +
drivers/acpi/acpi_apd.c | 3 +++
drivers/acpi/acpi_memhotplug.c | 3 +++
drivers/acpi/acpi_processor.c | 3 +++
drivers/acpi/arm64/init.c | 2 ++
drivers/acpi/bus.c | 6 +++---
drivers/acpi/scan.c | 4 ++++
drivers/acpi/tables.c | 4 ++--
drivers/firmware/efi/efi-bgrt.c | 2 +-
12 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
index 8a54ca6ba602..3116bb872f47 100644
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@@ -76,6 +76,7 @@ typedef u64 phys_cpuid_t;
#define PHYS_CPUID_INVALID INVALID_HWID
#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
+#define acpi_dt_hybrid 0 /* No DT-ACPI hybrid mode on ARM64 */
extern int acpi_disabled;
extern int acpi_noirq;
extern int acpi_pci_disabled;
diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h
index eda9d4d0a493..5f725bba6e87 100644
--- a/arch/loongarch/include/asm/acpi.h
+++ b/arch/loongarch/include/asm/acpi.h
@@ -12,6 +12,7 @@
#include <asm/suspend.h>
#ifdef CONFIG_ACPI
+#define acpi_dt_hybrid 0 /* No DT-ACPI hybrid mode on loongarch */
extern int acpi_strict;
extern int acpi_disabled;
extern int acpi_pci_disabled;
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
index 26ab37c171bc..b72586fe650e 100644
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@ -22,7 +22,8 @@ typedef u64 phys_cpuid_t;
void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size);
#define acpi_os_ioremap acpi_os_ioremap
-#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */
+#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */
+#define acpi_dt_hybrid 0 /* No DT-ACPI hybrid mode on RISC-V */
extern int acpi_disabled;
extern int acpi_noirq;
extern int acpi_pci_disabled;
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index a03aa6f999d1..ae1d3d588c06 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -25,6 +25,7 @@
#endif
#ifdef CONFIG_ACPI
+#define acpi_dt_hybrid 0 /* No DT-ACPI hybrid mode on x86 */
extern int acpi_lapic;
extern int acpi_ioapic;
extern int acpi_noirq;
diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c
index bed0791c17fc..0f9e22046e0a 100644
--- a/drivers/acpi/acpi_apd.c
+++ b/drivers/acpi/acpi_apd.c
@@ -263,5 +263,8 @@ static struct acpi_scan_handler apd_handler = {
void __init acpi_apd_init(void)
{
+ if (acpi_disabled)
+ return;
+
acpi_scan_add_handler(&apd_handler);
}
diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c
index 1d7dfe4ee9a6..00469a4b8897 100644
--- a/drivers/acpi/acpi_memhotplug.c
+++ b/drivers/acpi/acpi_memhotplug.c
@@ -361,6 +361,9 @@ static struct acpi_scan_handler memory_device_handler = {
void __init acpi_memory_hotplug_init(void)
{
+ if (acpi_disabled)
+ return;
+
acpi_scan_add_handler(&memory_device_handler);
}
diff --git a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c
index 00775b91bd41..f4ddd5e126e3 100644
--- a/drivers/acpi/acpi_processor.c
+++ b/drivers/acpi/acpi_processor.c
@@ -785,6 +785,9 @@ bool acpi_duplicate_processor_id(int proc_id)
void __init acpi_processor_init(void)
{
+ if (acpi_disabled)
+ return;
+
acpi_processor_check_duplicates();
acpi_scan_add_handler_with_hotplug(&processor_handler, "processor");
acpi_scan_add_handler(&processor_container_handler);
diff --git a/drivers/acpi/arm64/init.c b/drivers/acpi/arm64/init.c
index 7a47d8095a7d..9826c0b35715 100644
--- a/drivers/acpi/arm64/init.c
+++ b/drivers/acpi/arm64/init.c
@@ -4,6 +4,8 @@
void __init acpi_arch_init(void)
{
+ if (acpi_disabled)
+ return;
if (IS_ENABLED(CONFIG_ACPI_AGDI))
acpi_agdi_init();
if (IS_ENABLED(CONFIG_ACPI_APMT))
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 2ec095e2009e..1d5ea66cb99e 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1290,7 +1290,7 @@ void __init acpi_early_init(void)
{
acpi_status status;
- if (acpi_disabled)
+ if (acpi_disabled && !acpi_dt_hybrid)
return;
pr_info("Core revision %08x\n", ACPI_CA_VERSION);
@@ -1361,7 +1361,7 @@ void __init acpi_subsystem_init(void)
{
acpi_status status;
- if (acpi_disabled)
+ if (acpi_disabled && !acpi_dt_hybrid)
return;
status = acpi_enable_subsystem(~ACPI_NO_ACPI_ENABLE);
@@ -1494,7 +1494,7 @@ static int __init acpi_init(void)
{
int result;
- if (acpi_disabled) {
+ if (acpi_disabled && !acpi_dt_hybrid) {
pr_info("Interpreter disabled.\n");
return -ENODEV;
}
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 530547cda8b2..4836286968e8 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -2253,6 +2253,10 @@ static void acpi_default_enumeration(struct acpi_device *device)
ACPI_RECONFIG_DEVICE_ADD, device);
return;
}
+
+ if (acpi_dt_hybrid)
+ return;
+
if (match_string(acpi_system_dev_ids, -1, acpi_device_hid(device)) >= 0) {
struct acpi_scan_system_dev *sd;
diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c
index 4286e4af1092..6aec547c0872 100644
--- a/drivers/acpi/tables.c
+++ b/drivers/acpi/tables.c
@@ -247,7 +247,7 @@ int __init_or_acpilib acpi_table_parse_entries_array(
int count;
u32 instance = 0;
- if (acpi_disabled)
+ if (acpi_disabled && !acpi_dt_hybrid)
return -ENODEV;
if (!id)
@@ -330,7 +330,7 @@ int __init acpi_table_parse(char *id, acpi_tbl_table_handler handler)
{
struct acpi_table_header *table = NULL;
- if (acpi_disabled)
+ if (acpi_disabled && !acpi_dt_hybrid)
return -ENODEV;
if (!id || !handler)
diff --git a/drivers/firmware/efi/efi-bgrt.c b/drivers/firmware/efi/efi-bgrt.c
index 1da451582812..dc69342cdb38 100644
--- a/drivers/firmware/efi/efi-bgrt.c
+++ b/drivers/firmware/efi/efi-bgrt.c
@@ -31,7 +31,7 @@ void __init efi_bgrt_init(struct acpi_table_header *table)
struct acpi_table_bgrt *bgrt = &bgrt_tab;
int mem_type;
- if (acpi_disabled)
+ if (acpi_disabled && !acpi_dt_hybrid)
return;
if (!efi_enabled(EFI_MEMMAP) && !efi_enabled(EFI_PARAVIRT))
--
2.54.0
^ permalink raw reply related
* [RFC 00/12] RFC: Devicetree-ACPI hybrid mode
From: Hans de Goede @ 2026-06-23 14:52 UTC (permalink / raw)
To: Rafael J . Wysocki, Bjorn Andersson, Konrad Dybcio
Cc: Hans de Goede, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
Hi All,
Currently as soon as the kernel boots with a populated DT provided then
the arch/arm64 code sets acpi_disabled=1 and the complete ACPI subsystem
gets disabled. On WoA Snapdragon laptops where the factory Windows OS
actually boots using these tables this is not necessarily desirable.
It might still be interesting to at least parse the ACPI tables and make
the ACPI fwnodes available for device-drivers to use. I call this DT-ACPI
hybrid mode.
This mainly is an experiment for now and possibly a method for accelerating
the ongoing effort to run Linux on currently available Snapdragon laptops.
On current laptops Linux cannot boot using ACPI due to some information
missing from the ACPI tables. People are working on changing this so that
for future WoA Snapdragon laptops Linux can boot using ACPI only without
requiring Devicetree.
There are a couple of scenarios where DT-ACPI hybrid mode is useful:
a) This leads to a populated /sys/firmware/acpi/tables allowing one to run
acpidump, which is useful to grab info from the ACPI tables when e.g.
creating a DT for a new laptop model. As a bonus /sys/firmware/acpi/bgrt
is also populated allowing the boot-splash to show the vendor logo.
b) It might be useful for device-drivers to be able to access ACPI data
for the device even when running in DT mode. E.g. Srini Kandagatla first
got me thinking about this because he wants to use the ACPI MIPI SDCA
tables for audio codec routing when booting Linux on Windows Qualcomm X2
(Glymur) laptops.
c) It is also possible to go truely hybrid and use ACPI to instantiate
some of the kernel device objects representing the hardware. For example
the last patch in this RFC series switches to using ACPI instantiation for
the I2C clients for the keyboard and touchpad on the Snapdragon X1E Lenovo
ThinkPad T14s gen 6.
d) This may help identify shortcomings in the current ACPI tables which
need to be fixed to allow future laptop generations to use ACPI only.
Upstreaming of these patches (to upstream or not to upstream?).
1. The first couple of patches in this series mainly implement a) + b) from
above. This seems like something genuinely useful to have; and except for
missing DT-bindings for hybrid mode this seems mostly ready to go upstream.
2. I see c) as a way to slowly evolve support for current Snapdragon laptops
to use more and more info from ACPI and get closer to a point where we only
need a single DT describing the SoC and any info related to laptop model
specific bits outside of the SoC can be read from the ACPI tables.
As mentioned above work is being done to have Linux boot on future laptop
generations using ACPI only, so all this applies to currently available
Snapdragon laptop generations only.
The question is what to do wrt upstreaming patches necessary for c) though
(patches 7-12) are we going to allow new Devicetree files for not yet
supported laptop models to partially rely on ACPI?
The current demo ACPI usage in this RFC series just instantiates I2C-HID
devices from ACPI. More interesting would be to hookup the embedded
controller (EC) handling in the ACPI tables instead of having to write
a special EC driver for each laptop model separately. For the EC parts
I believe that it might be worthwhile to implement c).
This new DT-ACPI hybrid mode works as follows:
1. A new global ACPI subsys flag called acpi_dt_hybrid is introduced which
can be set to 1 combined with acpi_disabled=1. When this is done, then
despite acpi_disabled being set the ACPI tables will still get parsed and
/sys/firmware/acpi (tables) and /sys/bus/acpi/devices (fwnodes) will still
get populated. No devices will be instantiated, no fwnodes will get
attached to any other (e.g. PCI, USB) devices and no other actions will
be taken.
2. Add acpi=hybrid kernel-commandline option to the arch/arm64 code.
TODO: Add a DT-binding for selecting hybrid mode from Devicetree.
3. drivers/acpi/glue.c changes to support devices with an of_node as
primary fwnode having a "acpi-path" string property and when present look
up the ACPI fwnode for that path, e.g. "\\_SB.GIO0", "\\_SB.I2C1" and
set that fwnode as secondary node.
4. pinctrl-msm changes to map special WoA ACPI table virtual GPIO numbers
for PDC pins back to regular TLMM GPIO numbers.
5. Tiny drivers/i2c/i2c-core-acpi.c change to make it instantiate ACPI
described I2C clients under a DT instantiated I2C adapter if that
adapter has an ACPI secondary fwnode.
With this I can drop the DT description of the ThinkPad T14s gen 6
keyboard and touchpad and instead have these be instantiated by ACPI,
as shown in patch 12/12.
Comments, thoughts ?
Regards,
Hans
Hans de Goede (12):
ACPI: Introduce DT-ACPI hybrid mode
arm64: acpi: Cleanup acpi=[on|off|force] handling
arm64: acpi: add acpi=hybrid support
ACPI: Add helpers for dealing with ACPI fwnode as secondary fwnode
ACPI: glue: Implement setting secondary-fwnode for DT-ACPI hybrid mode
ACPI: scan: Retry acpi_device_notify() in DT-ACPI hybrid mode
ACPI: Make device_match_acpi_handle() also check the secondary fwnode
irqchip/gic-v3: Always call acpi_set_irq_model()
pinctrl: qcom: Add support for WoA ACPI tables virtual TLMM pin
numbers
i2c: acpi: Also register ACPI i2c_clients for adapters with a
secondary ACPI fwnode
i2c: qcom-geni: Fall back to i2c_acpi_find_bus_speed()
arm64: dts: qcom: x1e78100-thinkpad-t14s: Move keyb and touchpad to
ACPI enumeration
.../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 61 +-----
arch/arm64/include/asm/acpi.h | 1 +
arch/arm64/kernel/acpi.c | 47 +++--
arch/loongarch/include/asm/acpi.h | 1 +
arch/riscv/include/asm/acpi.h | 3 +-
arch/x86/include/asm/acpi.h | 1 +
drivers/acpi/acpi_apd.c | 3 +
drivers/acpi/acpi_memhotplug.c | 3 +
drivers/acpi/acpi_processor.c | 3 +
drivers/acpi/arm64/init.c | 2 +
drivers/acpi/bus.c | 6 +-
drivers/acpi/glue.c | 70 ++++++-
drivers/acpi/property.c | 13 ++
drivers/acpi/scan.c | 33 +++
drivers/acpi/tables.c | 4 +-
drivers/base/core.c | 4 +-
drivers/firmware/efi/efi-bgrt.c | 2 +-
drivers/i2c/busses/i2c-qcom-geni.c | 10 +-
drivers/i2c/i2c-core-acpi.c | 8 +-
drivers/irqchip/irq-gic-v3.c | 29 ++-
drivers/pinctrl/qcom/Makefile | 4 +-
drivers/pinctrl/qcom/pinctrl-msm-acpi.c | 196 ++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-msm.c | 47 ++++-
drivers/pinctrl/qcom/pinctrl-msm.h | 35 ++++
include/acpi/acpi_bus.h | 16 ++
include/linux/acpi.h | 10 +
26 files changed, 502 insertions(+), 110 deletions(-)
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm-acpi.c
--
2.54.0
^ permalink raw reply
* Re: [PATCH v3 7/7] ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4
From: sashiko-bot @ 2026-06-23 14:44 UTC (permalink / raw)
To: Grégoire Layet; +Cc: robh, devicetree, conor+dt
In-Reply-To: <86fc0b2a105a16ceb301ba53fadd096877455bb8.1782224060.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [Low] Adding `aspeed,vuart-over-pci` to nodes with multiple compatible strings violates the `const` constraint in the YAML binding, causing a schema validation failure.
Pre-existing issues:
- [High] Probe error paths fail to unregister the 8250 port and remove the sysfs group, resulting in a use-after-free of the devm-allocated driver state and resource leaks.
--
commit 3ce60a66a65e6d307209da21c88e6e5c758ddf74
Author: Grégoire Layet <gregoire.layet@9elements.com>
Date: Tue Jun 23 14:25:45 2026 +0000
ARM: dts: aspeed: g6: add aspeed,vuart-over-pci prop to vuart3 and 4
The VUART 3 and 4 are VUART over PCI.
This flag indicates this information.
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> index 5ff52697e8bb4..b33468288d4a5 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> @@ -714,6 +714,7 @@ vuart3: serial@1e787800 {
> interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&syscon ASPEED_CLK_APB2>;
> no-loopback-test;
> + aspeed,vuart-over-pci;
[Severity: Low]
Does adding this property cause a device tree schema validation failure?
Looking at Documentation/devicetree/bindings/serial/8250.yaml, the schema
restricts the compatible property to a single string when
aspeed,vuart-over-pci is present:
compatible:
const: aspeed,ast2600-vuart
Since the vuart3 node uses multiple compatible strings
("aspeed,ast2600-vuart", "aspeed,ast2500-vuart"), does this violate the
constraint and cause dtbs_check to fail?
[Severity: High]
This isn't a bug introduced by this patch, but adding this property appears
to trigger a pre-existing resource leak and use-after-free in the driver's
error path.
In drivers/tty/serial/8250/8250_aspeed_vuart.c, if
aspeed_ast2600_vuart_over_pci_set_enabled() fails during
aspeed_vuart_probe(), the function returns directly:
rc = aspeed_ast2600_vuart_over_pci_set_enabled(pdev);
if (rc) {
dev_err(dev, "could not enable VUART over PCI\n");
return rc;
}
Does this bypass calling serial8250_unregister_port() and
sysfs_remove_group() after a successful serial8250_register_8250_port()?
Since the devm-allocated driver state is freed on probe failure, does the
UART core retain a registered port pointing to freed memory?
> status = "disabled";
> };
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=7
^ permalink raw reply
* Re: [PATCH v3 6/7] ARM: dts: aspeed: g6: Change vuart compatible string for ast2600
From: sashiko-bot @ 2026-06-23 14:42 UTC (permalink / raw)
To: Grégoire Layet; +Cc: robh, conor+dt, devicetree
In-Reply-To: <30aedaa9ffd5ba2d763d8802a07b77ef2d5bfcf0.1782224060.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
New issues:
- [High] Newly introduced error path completely bypasses all probe cleanup.
- [High] Modifying a static global array when MSI allocation fails causes state corruption.
- [High] Assuming index 16 and 17 are unconditionally valid for partially allocated MSI vectors.
- [Medium] Device Tree Binding Schema Validation Failure
- [Medium] Using the 'clocks' property as a syscon phandle violates DT semantics.
Pre-existing issues:
- [High] Probe error paths fail to unregister the 8250 serial port, leading to Use-After-Free.
--
commit cd4f0040d97e2d9918c8ecf27108ed2de48871b7
Author: Grégoire Layet <gregoire.layet@9elements.com>
ARM: dts: aspeed: g6: Change vuart compatible string for ast2600
Use the ast2600 compatible string.
This makes it more precise and enables specific ast2600 properties.
Still use the ast2500 compatible string as a fallback.
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index bb7b9c87a8072..b03797f4674d4 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -23,7 +23,17 @@ allOf:
> then:
> properties:
> compatible:
> - const: aspeed,ast2500-vuart
> + anyOf:
> + - const: aspeed,ast2500-vuart
> + - const: aspeed,ast2600-vuart
[ ... ]
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> index 189bc3bbb47c9..5ff52697e8bb4 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> @@ -698,7 +698,7 @@ emmc: sdhci@1e750100 {
> };
>
> vuart1: serial@1e787000 {
> - compatible = "aspeed,ast2500-vuart";
> + compatible = "aspeed,ast2600-vuart", "aspeed,ast2500-vuart";
[Severity: Medium]
Will this pass device tree schema validation (dtbs_check)? The binding in
8250.yaml defines the compatible property as anyOf with single const strings,
meaning it expects exactly one of those strings. The device tree uses an array
of two strings. Should the schema be updated with an items array definition to
accept this combination?
[ ... ]
> diff --git a/drivers/soc/aspeed/aspeed-host-bmc-dev.c b/drivers/soc/aspeed/aspeed-host-bmc-dev.c
> new file mode 100644
> index 0000000000000..3160b6aedb5b6
> --- /dev/null
> +++ b/drivers/soc/aspeed/aspeed-host-bmc-dev.c
[ ... ]
> +static int vuart_msi_index[2] = { 16, 17 };
[ ... ]
> +static void aspeed_pci_setup_irq_resource(struct pci_dev *pdev)
> +{
> + struct aspeed_pci_bmc_dev *pci_bmc_dev = pci_get_drvdata(pdev);
> +
> + pci_bmc_dev->msi_idx_table = vuart_msi_index;
> +
> + if (pci_alloc_irq_vectors(pdev, 1, BMC_MULTI_MSI, PCI_IRQ_INTX | PCI_IRQ_MSI) <= 1)
> + /* If pci_alloc fail, set all msi index to the first vector */
> + memset(pci_bmc_dev->msi_idx_table, 0, sizeof(vuart_msi_index));
[Severity: High]
Does this code inadvertently corrupt global state for all driver instances?
Since pci_bmc_dev->msi_idx_table points to vuart_msi_index (a static global
array), calling memset on it will permanently zero out the MSI indices
system-wide if any device fails to allocate multiple MSI vectors.
Also, does the threshold check protect against partial allocations falling
short of index 17?
If pci_alloc_irq_vectors() successfully allocates an intermediate number of
vectors (e.g., 4 or 8), the '<= 1' check evaluates to false. The driver
retains indices 16 and 17 and attempts to fetch them via pci_irq_vector()
below, which triggers an out-of-bounds warning and returns -EINVAL.
[ ... ]
> +static int aspeed_pci_bmc_device_setup_vuart(struct pci_dev *pdev, int idx)
> +{
> + struct aspeed_pci_bmc_dev *pci_bmc_dev = pci_get_drvdata(pdev);
[ ... ]
> + uart->port.irq = pci_irq_vector(pdev, pci_bmc_dev->msi_idx_table[idx]);
[Severity: High]
If a partial allocation leaves us with fewer vectors than the index stored in
msi_idx_table[idx], pci_irq_vector() returns a negative error code like
-EINVAL. Could this error code be incorrectly passed as the IRQ number here,
causing interrupt registration to fail later?
[ ... ]
> diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c
> index 26fc0464f1cc2..e204e26fa173b 100644
> --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c
> +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c
[ ... ]
> +static int aspeed_ast2600_vuart_over_pci_set_enabled(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
[ ... ]
> + scu = syscon_regmap_lookup_by_phandle(dev->of_node, "clocks");
[Severity: Medium]
Is it semantically correct to use the "clocks" property as a syscon phandle?
The "clocks" property specifies clock providers and specifiers, not raw syscon
phandles. Piggybacking on this to extract a syscon regmap leverages an
implementation detail of syscon_regmap_lookup_by_phandle() and violates
device tree semantics.
[ ... ]
> @@ -540,6 +617,15 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
> aspeed_vuart_set_host_tx_discard(vuart, true);
> platform_set_drvdata(pdev, vuart);
>
> + if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-vuart") &&
> + of_property_read_bool(dev->of_node, "aspeed,vuart-over-pci")) {
> + rc = aspeed_ast2600_vuart_over_pci_set_enabled(pdev);
> + if (rc) {
> + dev_err(dev, "could not enable VUART over PCI\n");
> + return rc;
[Severity: High]
Does returning directly here skip probe cleanup? Bypassing the err_sysfs_remove
label leaves sysfs groups, timers, and the 8250 serial port registered while
devres frees the underlying vuart structure. Does this leak the sysfs groups
and timers, and potentially cause a use-after-free if the 8250 core accesses
the unregistered port?
> + }
> + }
> +
> return 0;
>
> err_sysfs_remove:
> sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
> return rc;
[Severity: High]
This isn't a bug introduced by this patch, but does the err_sysfs_remove path
fail to unregister the 8250 port? If probe fails after port registration,
serial8250_unregister_port() is missed. The 8250 core will later dereference
the freed vuart pointer via port.private_data, causing a use-after-free.
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=6
^ permalink raw reply
* Re: [PATCH v3 3/7] serial: 8250_aspeed_vuart: add aspeed,ast2600-vuart compatible string
From: sashiko-bot @ 2026-06-23 14:41 UTC (permalink / raw)
To: Grégoire Layet; +Cc: devicetree, conor+dt, robh
In-Reply-To: <56c378923566ea0be831f58fd7c2f186ab3f5cba.1782224059.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
New issues:
- [High] Direct return in the newly added AST2600 PCI initialization logic bypasses all resource cleanup.
Pre-existing issues:
- [High] Missing serial port unregistration and timer cleanup on probe error paths causes resource leaks and a Use-After-Free.
- [High] Sysfs attributes are created prematurely in probe() and removed late in remove(), allowing NULL pointer dereference and unmapped memory access.
- [High] Incorrect teardown order in remove() deletes the timer before unregistering the port, allowing the timer to be re-armed.
--
commit 0b81ae92f1a0f52b8cec821070559651477025dd
Author: Grégoire Layet <gregoire.layet@9elements.com>
serial: 8250_aspeed_vuart: add aspeed,ast2600-vuart compatible string
Makes the driver compatible with the ast2600-vuart.
This enables specific configuration for the AST2600.
> diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c
> index 26fc0464f1cc2..6afa2f4057e1b 100644
> --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c
> +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c
> @@ -560,6 +560,7 @@ static void aspeed_vuart_remove(struct platform_device *pdev)
> static const struct of_device_id aspeed_vuart_table[] = {
> { .compatible = "aspeed,ast2400-vuart" },
> { .compatible = "aspeed,ast2500-vuart" },
> + { .compatible = "aspeed,ast2600-vuart" },
[Severity: High]
Does the AST2600 PCI initialization logic bypass the error handling labels
in aspeed_vuart_probe()?
If aspeed_ast2600_vuart_over_pci_set_enabled() fails, the code returns
directly:
drivers/tty/serial/8250/8250_aspeed_vuart.c:aspeed_vuart_probe() {
...
if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-vuart") &&
of_property_read_bool(dev->of_node, "aspeed,vuart-over-pci")) {
rc = aspeed_ast2600_vuart_over_pci_set_enabled(pdev);
if (rc) {
dev_err(dev, "could not enable VUART over PCI\n");
return rc;
}
}
return 0;
err_sysfs_remove:
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
return rc;
}
This direct return bypasses the err_sysfs_remove cleanup label, which would
leave the sysfs group leaked and the UART port and timer active with
pointers to the devm-freed vuart structure.
[Severity: High]
This isn't a bug introduced by this patch, but does aspeed_vuart_probe()
leak resources and cause a use-after-free on other error paths?
If the probe fails and jumps to err_sysfs_remove, it removes the sysfs
group but fails to call serial8250_unregister_port() or timer_delete_sync():
drivers/tty/serial/8250/8250_aspeed_vuart.c:aspeed_vuart_probe() {
...
rc = serial8250_register_8250_port(&port);
...
err_sysfs_remove:
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
return rc;
}
Because vuart is devm-allocated, it will be freed upon probe failure,
leaving the UART port registered with private_data pointing to freed memory.
[Severity: High]
This is a pre-existing issue, but are the sysfs attributes exposed too
early in probe() and removed too late in remove()?
In aspeed_vuart_probe(), sysfs_create_group() is called before the
driver data is set via platform_set_drvdata():
drivers/tty/serial/8250/8250_aspeed_vuart.c:aspeed_vuart_probe() {
...
rc = sysfs_create_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
...
platform_set_drvdata(pdev, vuart);
...
}
If userspace reads attributes like lpc_address during this window,
dev_get_drvdata() returns NULL which is then dereferenced in the callback.
Additionally, in aspeed_vuart_remove(), sysfs_remove_group() is called
after serial8250_unregister_port():
drivers/tty/serial/8250/8250_aspeed_vuart.c:aspeed_vuart_remove() {
...
serial8250_unregister_port(vuart->line);
sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
}
Because unregistering the port calls iounmap(), any concurrent sysfs access
in this window could access unmapped I/O memory.
[Severity: High]
This is also a pre-existing issue, but does aspeed_vuart_remove() delete
the unthrottle timer before disabling the interrupt source that re-arms it?
drivers/tty/serial/8250/8250_aspeed_vuart.c:aspeed_vuart_remove() {
...
timer_delete_sync(&vuart->unthrottle_timer);
aspeed_vuart_set_enabled(vuart, false);
serial8250_unregister_port(vuart->line);
...
}
At the point timer_delete_sync() is called, the UART port is still active.
If an RX interrupt triggers concurrently, aspeed_vuart_handle_irq() can
call mod_timer() and re-arm it. The re-armed timer could then fire after
the devm-allocated vuart structure is freed.
> { },
> };
> MODULE_DEVICE_TABLE(of, aspeed_vuart_table);
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=3
^ permalink raw reply
* Re: [PATCH v3 4/7] serial: 8250_aspeed_vuart: add VUART over PCI
From: sashiko-bot @ 2026-06-23 14:41 UTC (permalink / raw)
To: Grégoire Layet; +Cc: robh, conor+dt, devicetree
In-Reply-To: <c3e1136d3565216c254db138e29299c2a3c6499f.1782224059.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
New issues:
- [High] The newly added error path directly returns on failure, bypassing sysfs cleanup and leaving the hardware enabled and port registered.
- [Medium] Brittle lookup of the SCU syscon regmap by parsing the "clocks" property.
- [Medium] Setting untested and reserved bits in SCU registers.
Pre-existing issues:
- [High] Preexisting error paths fail to unregister the 8250 serial port and delete the timer on probe failure, leading to a Use-After-Free.
- [High] Unprotected Read-Modify-Write operations on shared hardware registers.
- [High] Sysfs files and TTY port are exposed to userspace before driver data is initialized.
--
commit 277ed031956064f236c5536027c1f37b4a76d71d
Author: Grégoire Layet <gregoire.layet@9elements.com>
serial: 8250_aspeed_vuart: add VUART over PCI
This commit adds support for VUART over PCI on the AST2600 platform. It
configures the BMC PCI device enables, sets the PCI class code to MFD, and
configures MSI interrupts based on the silicon revision.
> diff --git a/drivers/tty/serial/8250/8250_aspeed_vuart.c b/drivers/tty/serial/8250/8250_aspeed_vuart.c
> index 6afa2f4057e1b..e204e26fa173b 100644
> --- a/drivers/tty/serial/8250/8250_aspeed_vuart.c
> +++ b/drivers/tty/serial/8250/8250_aspeed_vuart.c
[ ... ]
> @@ -412,6 +433,62 @@ static int aspeed_vuart_map_irq_polarity(u32 dt)
> +static int aspeed_ast2600_vuart_over_pci_set_enabled(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + u32 silicon_revision_id;
> + struct regmap *scu;
> + int rc;
> +
> + u32 pcie_config_ctl = SCU_PCIE_CONF_BMC_DEV_EN_IRQ |
> + SCU_PCIE_CONF_BMC_DEV_EN_MMIO |
> + SCU_PCIE_CONF_BMC_DEV_EN_MSI |
> + SCU_PCIE_CONF_BMC_DEV_EN_PCIE_BUS_MASTER |
> + SCU_PCIE_CONF_BMC_DEV_EN_E2L |
> + SCU_PCIE_CONF_BMC_DEV_EN_LPC_DECODE |
> + SCU_PCIE_CONF_BMC_DEV_EN;
> +
> + scu = syscon_regmap_lookup_by_phandle(dev->of_node, "clocks");
> + if (IS_ERR(scu)) {
[Severity: Medium]
Will this break if any clock multiplexer or intermediate clock controller is
inserted between the SCU and the VUART?
This code uses syscon_regmap_lookup_by_phandle() to fetch the SCU regmap by
parsing the "clocks" property. While this may happen to work if the SCU is
the direct clock provider, does this conflate the clock provider bindings
with syscon mappings?
> + dev_err(&pdev->dev, "failed to find SCU regmap\n");
> + return PTR_ERR(scu);
> + }
[ ... ]
> + if (silicon_revision_id == AST2600A3_REVISION_ID)
> + rc = regmap_update_bits(scu, ASPEED_SCUC24,
> + ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN | ASPEED_SCUC24_MSI_ROUTING_MASK,
> + ASPEED_SCUC24_PCIDEV1_INTX_MSI_HOST2BMC_EN | ASPEED_SCUC24_MSI_ROUTING_PCIe2LPC_PCIDEV1);
> + else
> + rc = regmap_update_bits(scu, ASPEED_SCUC24,
> + /* The bit 14 is reserved in the Datasheet, so we can't say what it does. This revision has not been tested */
> + ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN | BIT(14) | ASPEED_SCUC24_MSI_ROUTING_MASK,
[Severity: Medium]
Is it safe to write BIT(14) into ASPEED_SCUC24 when it is undocumented and
reserved?
The comment indicates the bit's purpose is unknown and this revision is
untested. Can setting this undocumented, reserved bit trigger unpredictable
hardware behavior on other silicon revisions?
> + ASPEED_SCUC24_PCIDEV1_INTX_MSI_SCU560_EN | BIT(14) | ASPEED_SCUC24_MSI_ROUTING_PCIe2LPC_PCIDEV1);
> + if (rc) {
> + dev_err(dev, "could not set PCI device 1 MSI interrupt routing\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
[ ... ]
> @@ -540,6 +617,15 @@ static int aspeed_vuart_probe(struct platform_device *pdev)
> aspeed_vuart_set_host_tx_discard(vuart, true);
[Severity: High]
This isn't a bug introduced by this patch, but can concurrent access
clobber register modifications?
Functions like aspeed_vuart_set_host_tx_discard() and
aspeed_vuart_set_sirq_polarity() perform read-modify-write operations on
ASPEED_VUART_GCRA. Does a concurrent sysfs write and TTY port open/close
cause a race condition here, since these are invoked from contexts with
different locks (or no locks)?
> platform_set_drvdata(pdev, vuart);
[Severity: High]
This isn't a bug introduced by this patch, but does the delay in calling
platform_set_drvdata() expose userspace to a null pointer dereference?
In aspeed_vuart_probe(), sysfs_create_group() is called very early.
If a concurrent userspace process reads the sysfs files, invoking
lpc_address_show() before platform_set_drvdata() is called here, it will
retrieve a null pointer and immediately dereference it.
>
> + if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-vuart") &&
> + of_property_read_bool(dev->of_node, "aspeed,vuart-over-pci")) {
> + rc = aspeed_ast2600_vuart_over_pci_set_enabled(pdev);
> + if (rc) {
> + dev_err(dev, "could not enable VUART over PCI\n");
> + return rc;
[Severity: High]
Does this direct return bypass necessary cleanup logic and leave the
hardware enabled?
By returning rc directly instead of jumping to a cleanup label, the sysfs
group aspeed_vuart_attr_group is leaked. Furthermore, does this bypass
unregistering the 8250 port and leave the VUART active despite probe
failure, since aspeed_vuart_set_enabled(vuart, true) was called earlier?
> + }
> + }
> +
> return 0;
>
> err_sysfs_remove:
> sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group);
> return rc;
> }
[Severity: High]
This isn't a bug introduced by this patch, but does this error path lead
to a use-after-free?
The err_sysfs_remove block cleans up sysfs attributes but entirely omits
calling serial8250_unregister_port() and timer_delete_sync(). Because the
driver uses devres, the vuart structure will be freed upon probe failure.
Since the port remains actively registered, any subsequent access to the
port via TTY operations will dereference this freed memory.
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=4
^ permalink raw reply
* Re: [PATCH v3 5/7] soc: aspeed: add host-side PCIe BMC device driver
From: sashiko-bot @ 2026-06-23 14:40 UTC (permalink / raw)
To: Grégoire Layet; +Cc: robh, devicetree, conor+dt
In-Reply-To: <8746971524bf4186c9a393dab637ad4e27ce4563.1782224059.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Modifying a shared static global array on IRQ allocation fallback permanently corrupts the driver state for all subsequent devices and creates a data race.
- [High] The driver mishandles `pci_alloc_irq_vectors()` return values, leading to silent probe successes with invalid IRQs or out-of-bounds vector accesses that trigger kernel warnings.
- [Medium] Truncation of a 64-bit PCI physical address due to storing it in an `unsigned long` on 32-bit architectures.
--
commit 64de7243e0e8e8cd9ac72d04be5ef937e8143347
Author: Grégoire Layet <gregoire.layet@9elements.com>
soc: aspeed: add host-side PCIe BMC device driver
Add support for VUART over PCIe between BMC and host.
This configures the PCIe and sets up two 8250 compatible VUART ports.
> diff --git a/drivers/soc/aspeed/aspeed-host-bmc-dev.c b/drivers/soc/aspeed/aspeed-host-bmc-dev.c
> new file mode 100644
> index 0000000000000..3160b6aedb5b6
> --- /dev/null
> +++ b/drivers/soc/aspeed/aspeed-host-bmc-dev.c
[ ... ]
> +static int vuart_msi_index[2] = { 16, 17 };
> +static int vuart_port_addr[2] = {0x3f8, 0x2f8};
> +
> +struct aspeed_pci_bmc_dev {
> + struct device *dev;
> + kernel_ulong_t driver_data;
> + int id;
> +
> + unsigned long message_bar_base;
[Severity: Medium]
Does storing the BAR address in an unsigned long truncate 64-bit physical
addresses on 32-bit architectures with PAE/LPAE?
pci_resource_start() returns a resource_size_t, which could be 64-bit,
potentially leading to incorrect I/O memory mapping here.
> +
> + struct uart_8250_port uart[2];
> + int uart_line[2];
> +
> + int *msi_idx_table;
> +};
> +
> +static void aspeed_pci_setup_irq_resource(struct pci_dev *pdev)
> +{
> + struct aspeed_pci_bmc_dev *pci_bmc_dev = pci_get_drvdata(pdev);
> +
> + pci_bmc_dev->msi_idx_table = vuart_msi_index;
> +
> + if (pci_alloc_irq_vectors(pdev, 1, BMC_MULTI_MSI, PCI_IRQ_INTX | PCI_IRQ_MSI) <= 1)
[Severity: High]
Can this condition mishandle partial allocations and negative error codes?
If pci_alloc_irq_vectors() partially succeeds and returns a value between
2 and 16, the <= 1 check evaluates to false. This leaves the indices at 16
and 17, but pci_irq_vector() will later trigger a WARN_ON_ONCE out-of-bounds
check in the PCI core when it tries to access index 16.
Additionally, if it fails entirely and returns a negative error, the check
passes, but the probe doesn't abort. Does this result in silently registering
the 8250 UART with an invalid IRQ?
> + /* If pci_alloc fail, set all msi index to the first vector */
> + memset(pci_bmc_dev->msi_idx_table, 0, sizeof(vuart_msi_index));
[Severity: High]
Does this memset corrupt the driver state for all subsequent instances?
Because pci_bmc_dev->msi_idx_table points directly to the static global array
vuart_msi_index, writing zeroes here permanently overwrites the shared array.
If multiple ASPEED PCI devices are probed, or if the device is probed again
later, will the indices be permanently stuck at 0?
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=5
^ permalink raw reply
* Re: [PATCH v3 2/7] dt-bindings: serial: 8250: aspeed: add aspeed,vuart-over-pci bool prop
From: sashiko-bot @ 2026-06-23 14:38 UTC (permalink / raw)
To: Grégoire Layet; +Cc: conor+dt, devicetree, robh
In-Reply-To: <73b2bd81ce70814612e6d3cb689c3296de742aaf.1782224059.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing `aspeed,ast2600-vuart` in the top-level `compatible` property schema definition, causing `dt_binding_check` failures.
--
commit 33747bb385812ccb653177817f0ed8cba28dbdec
Author: Grégoire Layet <gregoire.layet@9elements.com>
dt-bindings: serial: 8250: aspeed: add aspeed,vuart-over-pci bool prop
The ASPEED AST2600 has 2 VUART accessible over PCI.
This boolean can be set to specify if the VUART is used over PCI.
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index 3cbd0f532e151..b03797f4674d4 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -26,6 +26,14 @@ allOf:
> anyOf:
> - const: aspeed,ast2500-vuart
> - const: aspeed,ast2600-vuart
> + - if:
> + anyOf:
> + - required:
> + - aspeed,vuart-over-pci
> + then:
> + properties:
> + compatible:
> + const: aspeed,ast2600-vuart
[Severity: Low]
Should aspeed,ast2600-vuart also be explicitly added to the top-level
properties: compatible: oneOf: block?
Documentation/devicetree/bindings/serial/8250.yaml:properties.compatible.oneOf:
properties:
compatible:
oneOf:
- const: ns8250
- const: ns16450
- const: ns16550
- const: ns16550a
- const: ns16850
- const: aspeed,ast2400-vuart
- const: aspeed,ast2500-vuart
Device tree nodes using compatible = "aspeed,ast2600-vuart" will be rejected by
make dt_binding_check because the string is missing from this top-level
definition.
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=2
^ permalink raw reply
* Re: [PATCH 1/1] iio: health: add MAX86150 ECG and PPG biosensor driver
From: Joshua Crofts @ 2026-06-23 14:38 UTC (permalink / raw)
To: Md Shofiqul Islam
Cc: linux-iio, jic23, dlechner, nuno.sa, robh, krzk+dt, devicetree
In-Reply-To: <20260623140113.12574-2-shofiqtest@gmail.com>
On Tue, 23 Jun 2026 17:01:13 +0300
Md Shofiqul Islam <shofiqtest@gmail.com> wrote:
> The MAX86150 (Maxim/Analog Devices) integrates two PPG optical channels
> (Red/IR LED) and one ECG biopotential channel in a single I2C device.
> Data is captured via a 32-entry hardware FIFO with a configurable
> almost-full interrupt.
>
> The driver exposes three IIO channels:
> - in_intensity_red_raw (PPG Red, 19-bit unsigned)
> - in_intensity_ir_raw (PPG IR, 19-bit unsigned)
> - in_voltage0_raw (ECG, 18-bit signed)
>
> A hardware trigger is registered when an interrupt GPIO is provided in
> the device tree, enabling the IIO triggered buffer path for continuous
> low-overhead capture.
>
> FIFO reads use regmap_noinc_read() to burst-read 9 bytes (3 slots x
> 3 bytes) from the streaming FIFO_DATA register in a single I2C
> transaction.
>
> Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
> ---
> .../bindings/iio/health/maxim,max86150.yaml | 67 +++
> drivers/iio/health/Kconfig | 23 +
> drivers/iio/health/Makefile | 1 +
> drivers/iio/health/max86150.c | 512 ++++++++++++++++++
> 4 files changed, 603 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/iio/health/maxim,max86150.yaml
> create mode 100755 drivers/iio/health/max86150.c
>
> diff --git a/Documentation/devicetree/bindings/iio/health/maxim,max86150.yaml b/Documentation/devicetree/bindings/iio/health/maxim,max86150.yaml
> new file mode 100755
> index 000000000000..1bf10fd1a3d2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/health/maxim,max86150.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/health/maxim,max86150.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
Split this into 2 patches - one for the new dt-binding and one for the
actual driver, KConfig and Makefile.
Additionally, since you're adding a brand new driver, a MAINTAINERS entry
is required.
Kind regards
CJD
^ permalink raw reply
* Re: [PATCH 1/9] dt-bindings: nvmem: imx-ocotp: Add support for secure-enclave
From: Frank Li @ 2026-06-23 14:36 UTC (permalink / raw)
To: Peng Fan
Cc: Frieder Schrempf, Krzysztof Kozlowski, Frieder Schrempf,
Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, devicetree, imx, linux-arm-kernel,
linux-kernel
In-Reply-To: <ajoJFt6c1cKELlH6@shlinux89>
On Tue, Jun 23, 2026 at 12:18:30PM +0800, Peng Fan wrote:
> On Mon, Jun 22, 2026 at 09:14:43AM -0500, Frank Li wrote:
> >On Wed, Jun 17, 2026 at 01:36:30PM +0200, Frieder Schrempf wrote:
> >> On 17.06.26 12:49, Krzysztof Kozlowski wrote:
> >> > On Tue, Jun 16, 2026 at 01:52:16PM +0200, Frieder Schrempf wrote:
> >> >> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> >> >>
> >> >> Some SoCs like the i.MX9 family allow full access to the fuses only
> >> >> through the secure enclave firmware API. Add a property to reference
> >> >> the secure enclave node and let the driver use the API.
> >> >>
> >> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> >> >> ---
> >> >> Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml | 4 ++++
> >> >> 1 file changed, 4 insertions(+)
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml
> >> >> index a8076d0e2737..14a6429f4a4c 100644
> >> >> --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml
> >> >> +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml
> >> >> @@ -53,6 +53,10 @@ properties:
> >> >> reg:
> >> >> maxItems: 1
> >> >>
> >> >> + secure-enclave:
> >> >> + $ref: /schemas/types.yaml#/definitions/phandle
> >> >> + description: A phandle to the secure enclave node
> >> >
> >> > Two things here:
> >> > 1. Here you describe what for is that phandle, how it is used by the
> >> > hardware. Currently the description repeats the property name and type,
> >> > so not much useful.
> >>
> >> Ok, agree.
> >>
> >> >
> >> > 2. If you access OTP via firmware, then this is completely different
> >> > interface than MMIO, thus:
> >> > A. reg is not appropriate
> >> > B. Device is very different thus it has different compatible and I even
> >> > claim should be in different binding. Devices having completely
> >> > different SW interface should not be in the same binding, at least
> >> > usually.
> >> >
> >> > If any of above is not accurate, then your commit msg should answer why
> >> > and give some background.
> >>
> >> Thanks for the feedback!
> >>
> >> The driver currently uses the limited MMIO (FSB) interface to access the
> >> OTPs. The intention is to support the firmware interface alongside the
> >> MMIO interface so the driver can pick the interface that is available
> >> (firmware might not be loaded) and fallback to MMIO.
> >
> >Does ELE and MMIO access the same bank of fuse? If access the same bank,
>
> Some fuse banks are only accessible through ELE firmware. Some fuse banks
> are accessible using MMIO. In theory, ELE firmware are able to access all
> fuse banks.
So use two driver for it, one use current MMIO ot access part of fuse box.
use ELE access the left part, which MMIO can't access.
MMIO should be simple and quick than go through ELE.
Frank
>
> Regards
> Peng
>
> >why not always use MMIO. Any beneafit from ELE firmware?
>
> >
> >Frank
> >>
> >> Following your argument would mean a driver deciding by itself which
> >> interface to use at runtime is not something we want to have in general,
> >> right?
> >>
> >> In turn this would mean we need two drivers, or at least two
> >> compatibles/bindings for something that is effectively the same hardware.
> >>
> >> Actually, my first RFC approach [1] was to create a separate driver. But
> >> in the end it seemed very weird to have two drivers and two DT nodes for
> >> the same hardware block. Also I have no idea what happens if both
> >> interfaces are used at the same time.
> >>
> >> The other idea from back then was to replace the MMIO (FSB) interface
> >> with ELE, but this would mean that we rely on the proprietary ELE
> >> firmware to be available for simple things like reading a MAC address,
> >> which is not desirable either, I guess.
> >>
> >> In which direction should I move on with this?
> >>
> >> [1]
> >> https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250416142715.1042363-1-frieder@fris.de/
> >>
^ permalink raw reply
* Re: [PATCH v3 1/7] dt-bindings: serial: 8250: aspeed: add compatible string for ast2600
From: sashiko-bot @ 2026-06-23 14:35 UTC (permalink / raw)
To: Grégoire Layet; +Cc: devicetree, robh, conor+dt
In-Reply-To: <80d983887dfdfc7e70a6db95f8cb95b7312f3044.1782224059.git.gregoire.layet@9elements.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly introduced compatible string `aspeed,ast2600-vuart` is missing from the top-level `properties: compatible: oneOf:` allowed list. While it was correctly added to the `allOf` conditional blocks, its absence from the main enumeration will cause device tree schema validation (`dt_binding_check` and `dtbs_check`) to fail for any device tree node utilizing this compatible string.
--
commit 6f7f111bc5bb5cca5a6591d60c1457c4bf00cb3e
Author: Grégoire Layet <gregoire.layet@9elements.com>
dt-bindings: serial: 8250: aspeed: add compatible string for ast2600
The ast2600 was using the ast2500 vuart compatible string.
This change makes it possible to have ast2600-specific properties.
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index bb7b9c87a8072..3cbd0f532e151 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -23,7 +23,9 @@ allOf:
> then:
> properties:
> compatible:
> - const: aspeed,ast2500-vuart
> + anyOf:
> + - const: aspeed,ast2500-vuart
> + - const: aspeed,ast2600-vuart
[Severity: Low]
Does this compatible string also need to be added to the top-level properties
enumeration?
While it is added here in the allOf conditional block, it appears to be missing
from the main allowed list, which currently looks like this:
properties:
compatible:
oneOf:
- const: ns8250
- const: ns16450
- const: ns16550
- const: ns16550a
- const: ns16850
- const: aspeed,ast2400-vuart
- const: aspeed,ast2500-vuart
Will this omission cause a regression during device tree schema validation
for device trees using the new aspeed,ast2600-vuart compatible string?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782224059.git.gregoire.layet@9elements.com?part=1
^ permalink raw reply
* Re: [PATCH V2 1/8] PCI: imx6: Add skip_pwrctrl_off flag support
From: Frank Li @ 2026-06-23 14:32 UTC (permalink / raw)
To: Sherry Sun (OSS)
Cc: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
amitkumar.karwar, neeraj.sanjaykale, marcel, luiz.dentz,
hongxing.zhu, l.stach, lpieralisi, kwilczynski, mani, bhelgaas,
brgl, imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel,
linux-bluetooth, linux-pm, sherry.sun
In-Reply-To: <20260623030736.1421537-2-sherry.sun@oss.nxp.com>
On Tue, Jun 23, 2026 at 11:07:28AM +0800, Sherry Sun (OSS) wrote:
> From: Sherry Sun <sherry.sun@nxp.com>
>
> Use dw_pcie_rp::skip_pwrctrl_off to avoid powering off devices during
> suspend to preserve wakeup capability of the devices and also not to power
> on the devices in the init path.
> This allows controller power-off to be skipped when some devices(e.g. M.2
> cards key E without auxiliary power) required to support PCIe L2 link state
> and wake-up mechanisms.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 36 +++++++++++++++++----------
> 1 file changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 0fa716d1ed75..ff5a9565dbbf 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1382,16 +1382,20 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> }
> }
>
> - ret = pci_pwrctrl_create_devices(dev);
> - if (ret) {
> - dev_err(dev, "failed to create pwrctrl devices\n");
> - goto err_reg_disable;
> + if (!pci->suspended) {
> + ret = pci_pwrctrl_create_devices(dev);
Is possible move pci_pwrctrl_create_devices() of pci_pwrctrl_create_devices
and call it direct at probe() function, like other regulator_get function.
Frank
> + if (ret) {
> + dev_err(dev, "failed to create pwrctrl devices\n");
> + goto err_reg_disable;
> + }
> }
>
> - ret = pci_pwrctrl_power_on_devices(dev);
> - if (ret) {
> - dev_err(dev, "failed to power on pwrctrl devices\n");
> - goto err_pwrctrl_destroy;
> + if (!pp->skip_pwrctrl_off) {
> + ret = pci_pwrctrl_power_on_devices(dev);
> + if (ret) {
> + dev_err(dev, "failed to power on pwrctrl devices\n");
> + goto err_pwrctrl_destroy;
> + }
> }
>
> ret = imx_pcie_clk_enable(imx_pcie);
> @@ -1460,9 +1464,10 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> err_clk_disable:
> imx_pcie_clk_disable(imx_pcie);
> err_pwrctrl_power_off:
> - pci_pwrctrl_power_off_devices(dev);
> + if (!pp->skip_pwrctrl_off)
> + pci_pwrctrl_power_off_devices(dev);
> err_pwrctrl_destroy:
> - if (ret != -EPROBE_DEFER)
> + if (ret != -EPROBE_DEFER && !pci->suspended)
> pci_pwrctrl_destroy_devices(dev);
> err_reg_disable:
> if (imx_pcie->vpcie)
> @@ -1482,7 +1487,8 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp)
> }
> imx_pcie_clk_disable(imx_pcie);
>
> - pci_pwrctrl_power_off_devices(pci->dev);
> + if (!pci->pp.skip_pwrctrl_off)
> + pci_pwrctrl_power_off_devices(pci->dev);
> if (imx_pcie->vpcie)
> regulator_disable(imx_pcie->vpcie);
> }
> @@ -1990,12 +1996,16 @@ static int imx_pcie_probe(struct platform_device *pdev)
> static void imx_pcie_shutdown(struct platform_device *pdev)
> {
> struct imx_pcie *imx_pcie = platform_get_drvdata(pdev);
> + struct dw_pcie *pci = imx_pcie->pci;
> + struct dw_pcie_rp *pp = &pci->pp;
>
> /* bring down link, so bootloader gets clean state in case of reboot */
> imx_pcie_assert_core_reset(imx_pcie);
> imx_pcie_assert_perst(imx_pcie, true);
> - pci_pwrctrl_power_off_devices(&pdev->dev);
> - pci_pwrctrl_destroy_devices(&pdev->dev);
> + if (!pp->skip_pwrctrl_off)
> + pci_pwrctrl_power_off_devices(&pdev->dev);
> + if (!pci->suspended)
> + pci_pwrctrl_destroy_devices(&pdev->dev);
> }
>
> static const struct imx_pcie_drvdata drvdata[] = {
> --
> 2.50.1
>
>
^ permalink raw reply
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