* [PATCH v5 02/12] i3c: master: Use unified device property interface
From: Akhil R @ 2026-06-24 10:20 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Frank Li, Miquel Raynal, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Guenter Roeck, Philipp Zabel, Jon Hunter,
Thierry Reding, linux-i3c, devicetree, linux-hwmon, linux-tegra,
linux-kernel, Akhil R
In-Reply-To: <20260624102153.1770072-1-akhilrajeev@nvidia.com>
Replace all OF-specific functions with unified device property functions
as a prerequisite to support both ACPI and device tree.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
drivers/i3c/master.c | 78 +++++++++++++++++++++-----------------
include/linux/i3c/master.h | 5 ++-
2 files changed, 47 insertions(+), 36 deletions(-)
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index f1be38a640ca..b20f56f7b68e 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -13,10 +13,12 @@
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/export.h>
+#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/pm_runtime.h>
+#include <linux/property.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
@@ -491,7 +493,7 @@ static void i3c_bus_cleanup(struct i3c_bus *i3cbus)
mutex_unlock(&i3c_core_lock);
}
-static int i3c_bus_init(struct i3c_bus *i3cbus, struct device_node *np)
+static int i3c_bus_init(struct i3c_bus *i3cbus, struct fwnode_handle *fwnode)
{
int ret, start, end, id = -1;
@@ -501,8 +503,8 @@ static int i3c_bus_init(struct i3c_bus *i3cbus, struct device_node *np)
i3c_bus_init_addrslots(i3cbus);
i3cbus->mode = I3C_BUS_MODE_PURE;
- if (np)
- id = of_alias_get_id(np, "i3c");
+ if (fwnode && is_of_node(fwnode))
+ id = of_alias_get_id(to_of_node(fwnode), "i3c");
mutex_lock(&i3c_core_lock);
if (id >= 0) {
@@ -837,7 +839,7 @@ static void i3c_masterdev_release(struct device *dev)
WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c));
i3c_bus_cleanup(bus);
- of_node_put(dev->of_node);
+ fwnode_handle_put(dev->fwnode);
}
static const struct device_type i3c_masterdev_type = {
@@ -1044,7 +1046,7 @@ static void i3c_device_release(struct device *dev)
WARN_ON(i3cdev->desc);
- of_node_put(i3cdev->dev.of_node);
+ fwnode_handle_put(dev->fwnode);
kfree(i3cdev);
}
@@ -1928,7 +1930,8 @@ i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
desc->info.pid);
if (desc->boardinfo)
- desc->dev->dev.of_node = desc->boardinfo->of_node;
+ device_set_node(&desc->dev->dev,
+ fwnode_handle_get(desc->boardinfo->fwnode));
ret = device_register(&desc->dev->dev);
if (ret) {
@@ -2620,8 +2623,8 @@ EXPORT_SYMBOL_GPL(i3c_master_do_daa);
#define OF_I3C_REG1_IS_I2C_DEV BIT(31)
static int
-of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
- struct device_node *node, u32 *reg)
+i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
+ struct fwnode_handle *fwnode, u32 *reg)
{
struct i2c_dev_boardinfo *boardinfo;
struct device *dev = &master->dev;
@@ -2631,9 +2634,13 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
if (!boardinfo)
return -ENOMEM;
- ret = of_i2c_get_board_info(dev, node, &boardinfo->base);
- if (ret)
- return ret;
+ if (is_of_node(fwnode)) {
+ ret = of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base);
+ if (ret)
+ return ret;
+ } else {
+ return -EINVAL;
+ }
/*
* The I3C Specification does not clearly say I2C devices with 10-bit
@@ -2649,14 +2656,14 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
boardinfo->lvr = reg[2];
list_add_tail(&boardinfo->node, &master->boardinfo.i2c);
- of_node_get(node);
+ fwnode_handle_get(fwnode);
return 0;
}
static int
-of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
- struct device_node *node, u32 *reg)
+i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
+ struct fwnode_handle *fwnode, u32 *reg)
{
struct i3c_dev_boardinfo *boardinfo;
struct device *dev = &master->dev;
@@ -2679,7 +2686,7 @@ of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
boardinfo->static_addr = reg[0];
- if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) {
+ if (!fwnode_property_read_u32(fwnode, "assigned-address", &init_dyn_addr)) {
if (init_dyn_addr > I3C_MAX_ADDR)
return -EINVAL;
@@ -2696,14 +2703,14 @@ of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
return -EINVAL;
boardinfo->init_dyn_addr = init_dyn_addr;
- boardinfo->of_node = of_node_get(node);
+ boardinfo->fwnode = fwnode_handle_get(fwnode);
list_add_tail(&boardinfo->node, &master->boardinfo.i3c);
return 0;
}
-static int of_i3c_master_add_dev(struct i3c_master_controller *master,
- struct device_node *node)
+static int i3c_master_add_dev(struct i3c_master_controller *master,
+ struct fwnode_handle *fwnode)
{
u32 reg[3];
int ret;
@@ -2711,7 +2718,7 @@ static int of_i3c_master_add_dev(struct i3c_master_controller *master,
if (!master)
return -EINVAL;
- ret = of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg));
+ ret = fwnode_property_read_u32_array(fwnode, "reg", reg, ARRAY_SIZE(reg));
if (ret)
return ret;
@@ -2720,25 +2727,25 @@ static int of_i3c_master_add_dev(struct i3c_master_controller *master,
* dealing with an I2C device.
*/
if (!reg[1])
- ret = of_i3c_master_add_i2c_boardinfo(master, node, reg);
+ ret = i3c_master_add_i2c_boardinfo(master, fwnode, reg);
else
- ret = of_i3c_master_add_i3c_boardinfo(master, node, reg);
+ ret = i3c_master_add_i3c_boardinfo(master, fwnode, reg);
return ret;
}
-static int of_populate_i3c_bus(struct i3c_master_controller *master)
+static int fwnode_populate_i3c_bus(struct i3c_master_controller *master)
{
struct device *dev = &master->dev;
- struct device_node *i3cbus_np = dev->of_node;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
int ret;
u32 val;
- if (!i3cbus_np)
+ if (!fwnode)
return 0;
- for_each_available_child_of_node_scoped(i3cbus_np, node) {
- ret = of_i3c_master_add_dev(master, node);
+ fwnode_for_each_available_child_node_scoped(fwnode, child) {
+ ret = i3c_master_add_dev(master, child);
if (ret)
return ret;
}
@@ -2748,10 +2755,10 @@ static int of_populate_i3c_bus(struct i3c_master_controller *master)
* on the bus are not supporting typical rates, or if the bus topology
* prevents it from using max possible rate.
*/
- if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val))
+ if (!device_property_read_u32(dev, "i2c-scl-hz", &val))
master->bus.scl_rate.i2c = val;
- if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val))
+ if (!device_property_read_u32(dev, "i3c-scl-hz", &val))
master->bus.scl_rate.i3c = val;
return 0;
@@ -2806,7 +2813,7 @@ static u8 i3c_master_i2c_get_lvr(struct i2c_client *client)
u8 lvr = I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE;
u32 reg[3];
- if (!of_property_read_u32_array(client->dev.of_node, "reg", reg, ARRAY_SIZE(reg)))
+ if (!fwnode_property_read_u32_array(client->dev.fwnode, "reg", reg, ARRAY_SIZE(reg)))
lvr = reg[2];
return lvr;
@@ -2925,7 +2932,8 @@ static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master);
struct i2c_dev_desc *i2cdev;
struct i2c_dev_boardinfo *i2cboardinfo;
- int ret, id;
+ struct fwnode_handle *fwnode = dev_fwnode(&master->dev);
+ int ret, id = -1;
adap->dev.parent = master->dev.parent;
adap->owner = master->dev.parent->driver->owner;
@@ -2934,7 +2942,9 @@ static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
adap->timeout = HZ;
adap->retries = 3;
- id = of_alias_get_id(master->dev.of_node, "i2c");
+ if (fwnode && is_of_node(fwnode))
+ id = of_alias_get_id(to_of_node(fwnode), "i2c");
+
if (id >= 0) {
adap->nr = id;
ret = i2c_add_numbered_adapter(adap);
@@ -3235,7 +3245,7 @@ int i3c_master_register(struct i3c_master_controller *master,
return ret;
master->dev.parent = parent;
- master->dev.of_node = of_node_get(parent->of_node);
+ device_set_node(&master->dev, fwnode_handle_get(dev_fwnode(parent)));
master->dev.bus = &i3c_bus_type;
master->dev.type = &i3c_masterdev_type;
master->dev.release = i3c_masterdev_release;
@@ -3254,13 +3264,13 @@ int i3c_master_register(struct i3c_master_controller *master,
master->dev.coherent_dma_mask = parent->coherent_dma_mask;
master->dev.dma_parms = parent->dma_parms;
- ret = i3c_bus_init(i3cbus, master->dev.of_node);
+ ret = i3c_bus_init(i3cbus, dev_fwnode(&master->dev));
if (ret)
goto err_put_dev;
dev_set_name(&master->dev, "i3c-%d", i3cbus->id);
- ret = of_populate_i3c_bus(master);
+ ret = fwnode_populate_i3c_bus(master);
if (ret)
goto err_put_dev;
diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
index 4d2a68793324..a16deb04b2e1 100644
--- a/include/linux/i3c/master.h
+++ b/include/linux/i3c/master.h
@@ -177,7 +177,8 @@ struct i3c_device_ibi_info {
* @pid: I3C Provisioned ID exposed by the device. This is a unique identifier
* that may be used to attach boardinfo to i3c_dev_desc when the device
* does not have a static address
- * @of_node: optional DT node in case the device has been described in the DT
+ * @fwnode: Firmware node (DT or ACPI) in case the device has been
+ * described in firmware
*
* This structure is used to attach board-level information to an I3C device.
* Not all I3C devices connected on the bus will have a boardinfo. It's only
@@ -189,7 +190,7 @@ struct i3c_dev_boardinfo {
u8 init_dyn_addr;
u8 static_addr;
u64 pid;
- struct device_node *of_node;
+ struct fwnode_handle *fwnode;
};
/**
--
2.43.0
^ permalink raw reply related
* [PATCH v5 01/12] dt-bindings: i3c: Add mipi-i3c-static-method to support SETAASA
From: Akhil R @ 2026-06-24 10:20 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Frank Li, Miquel Raynal, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Guenter Roeck, Philipp Zabel, Jon Hunter,
Thierry Reding, linux-i3c, devicetree, linux-hwmon, linux-tegra,
linux-kernel, Akhil R
In-Reply-To: <20260624102153.1770072-1-akhilrajeev@nvidia.com>
Add the 'mipi-i3c-static-method' property mentioned in the MIPI I3C
Discovery and Configuration Specification [1] to specify which discovery
method an I3C device supports during bus initialization. The property is
a bitmap, where a bit value of 1 indicates support for that method, and 0
indicates lack of support.
Bit 0: SETDASA CCC (Direct)
Bit 1: SETAASA CCC (Broadcast)
Bit 2: Other CCC (vendor / standards extension)
All other bits are reserved.
It is specifically needed when an I3C device requires SETAASA for the
address assignment. SETDASA will be supported by default if this property
is absent, which means for now the property just serves as a flag to
enable SETAASA, but keep the property as a bitmap to align with the
specifications.
[1] https://www.mipi.org/mipi-disco-for-i3c-download
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
.../devicetree/bindings/i3c/i3c.yaml | 36 ++++++++++++++++---
include/dt-bindings/i3c/i3c.h | 4 +++
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation/devicetree/bindings/i3c/i3c.yaml
index e25fa72fd785..5603f2e7807d 100644
--- a/Documentation/devicetree/bindings/i3c/i3c.yaml
+++ b/Documentation/devicetree/bindings/i3c/i3c.yaml
@@ -31,10 +31,12 @@ properties:
described in the device tree, which in turn means we have to describe
I3C devices.
- Another use case for describing an I3C device in the device tree is when
- this I3C device has a static I2C address and we want to assign it a
- specific I3C dynamic address before the DAA takes place (so that other
- devices on the bus can't take this dynamic address).
+ Other use-cases for describing an I3C device in the device tree are:
+ - When the I3C device has a static I2C address and we want to assign
+ it a specific I3C dynamic address before the DAA takes place (so
+ that other devices on the bus can't take this dynamic address).
+ - When the I3C device requires SETAASA for its discovery and uses a
+ pre-defined static address.
"#size-cells":
const: 0
@@ -145,7 +147,31 @@ patternProperties:
Dynamic address to be assigned to this device. In case static address is
present (first cell of the reg property != 0), this address is assigned
through SETDASA. If static address is not present, this address is assigned
- through SETNEWDA after assigning a temporary address via ENTDAA.
+ through SETNEWDA after assigning a temporary address via ENTDAA. If
+ SETAASA is used, this property is not used, and the static address itself
+ becomes the dynamic address.
+
+ mipi-i3c-static-method:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x1
+ maximum: 0x7
+ default: 1
+ description: |
+ Bitmap describing which methods of Dynamic Address Assignment from a
+ static address are supported by this I3C Target. For each defined bit
+ position, a set bit indicates support for that method and a cleared
+ bit indicates lack of support.
+
+ Bit 0: SETDASA CCC (Direct)
+ Bit 1: SETAASA CCC (Broadcast)
+ Bit 2: Other CCC (vendor / standards extension)
+ All other bits are reserved.
+
+ This property follows the MIPI I3C specification. The primary use
+ of this property is to indicate support for SETAASA, i.e Bit 1, but
+ will allow other values mentioned in the specification so that it
+ mirrors the specification. SETDASA will remain as the default method
+ even if this property is not present.
required:
- reg
diff --git a/include/dt-bindings/i3c/i3c.h b/include/dt-bindings/i3c/i3c.h
index 373439218bba..78b8c634aad8 100644
--- a/include/dt-bindings/i3c/i3c.h
+++ b/include/dt-bindings/i3c/i3c.h
@@ -13,4 +13,8 @@
#define I2C_NO_FILTER_HIGH_FREQUENCY (1 << 5)
#define I2C_NO_FILTER_LOW_FREQUENCY (2 << 5)
+#define I3C_ADDR_METHOD_SETDASA (1 << 0)
+#define I3C_ADDR_METHOD_SETAASA (1 << 1)
+#define I3C_ADDR_METHOD_VENDOR (1 << 2)
+
#endif
--
2.43.0
^ permalink raw reply related
* [PATCH v5 00/12] Support ACPI and SETAASA device discovery
From: Akhil R @ 2026-06-24 10:20 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Frank Li, Miquel Raynal, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Guenter Roeck, Philipp Zabel, Jon Hunter,
Thierry Reding, linux-i3c, devicetree, linux-hwmon, linux-tegra,
linux-kernel, Akhil R
This patch series adds SETAASA device discovery to the I3C subsystem,
enabling support for SPD5118 temperature sensors found on DDR5 memory
modules. The changes also add ACPI support for all existing DAA
methods like SETDASA, SETNEWDA as well as I2C devices on I3C bus.
SPD5118 and similar devices on DDR5 memory modules differ from typical
I3C devices in their initialization. They use SETAASA broadcast CCC
instead of ENTDAA for address assignment, and per JEDEC specification,
are not required to have a Provisioned ID or implement standard device
information CCC commands (GETPID, GETDCR, GETBCR).
The series enables describing all I3C and I2C devices on both Device
Tree and the ACPI table, using unified device property APIs throughout
the I3C core and the Synopsys DesignWare I3C master driver.
Please note that the series modifies drivers across multiple subsystems,
like Device Tree bindings, ACPI, I3C and HWMON.
v4->v5:
* Free ACPI I2C boardinfo when an ACPI child without an I2C resource is
ignored.
* Issue RSTDAA if SETAASA device attach fails after the static address is
used as the dynamic address.
* Emit OF and ACPI modaliases for firmware-matched I3C devices.
* Make the DesignWare core clock optional and use "clock-frequency" as
the fallback when core_clk is absent.
* Keep DesignWare pclk, reset, and match-data handling on their existing
optional paths.
v3->v4:
* Clarify mipi-i3c-static-method bit semantics and assigned-address
* Add I3C_ADDR_METHOD_VENDOR
* Fix fwnode reference handling while converting child property parsing
to use unified firmware-node APIs.
* Align ACPI child enumeration with the I2C core for multiple
I2cSerialBus resources, ignore ACPI child entries without an I2C
resource, and populate I2C modalias information from ACPI.
* Update SETAASA handling to use the static address as the dynamic
address, skip device-info retrieval for SETAASA devices, and tolerate
M2 for SETHID/SETAASA similarly to ENTDAA.
* Reorder DesignWare I3C clock/reset to include optional clock in the
ACPI skip clock/reset quirk.
* Add prints for missing ACPI clock-frequency and SPD5118 I3C
device type read failures.
* Fix grammar in comments and commit messages.
v2->v3:
* Fix maximum value and indent bit list for mipi-i3c-static-method.
* Move I3C_ADDR_METHOD_* macros to dt-bindings header.
* Drop ACPICA commit IDs, keep only the Link: tags.
* Revert the change which proceeds to register other devices if SETAASA
is not supported so that it aligns with the rest of the driver and to
avoid the issues pointed by Sashiko.
* Rework multiple commit messages.
v1->v2:
* Added patch to remove 16-bit addressing support for SPD5118
* Guard ACPI calls with #ifdef CONFIG_ACPI
* Remove CONFIG_OF guard for of_alias_get_highest_id()
* Mask mipi-i3c-static-method in the driver to select only valid values.
* Proceed to register other devices if SETAASA is not supported.
* Update commit message and links in the description of multiple commits.
Akhil R (12):
dt-bindings: i3c: Add mipi-i3c-static-method to support SETAASA
i3c: master: Use unified device property interface
i3c: master: Support ACPI enumeration of child devices
i3c: master: Add support for devices using SETAASA
i3c: master: Add support for devices without PID
i3c: master: match I3C device through DT and ACPI
i3c: dw-i3c-master: Add SETAASA as supported CCC
i3c: dw-i3c-master: Add ACPI core clock frequency quirk
i3c: dw-i3c-master: Add ACPI ID for Tegra410
hwmon: spd5118: Remove 16-bit addressing
hwmon: spd5118: Add I3C support
arm64: defconfig: Enable I3C and SPD5118 hwmon
.../devicetree/bindings/i3c/i3c.yaml | 36 +-
arch/arm64/configs/defconfig | 3 +
drivers/hwmon/Kconfig | 9 +-
drivers/hwmon/spd5118.c | 119 +++---
drivers/i3c/master.c | 382 +++++++++++++++---
drivers/i3c/master/dw-i3c-master.c | 36 +-
include/dt-bindings/i3c/i3c.h | 4 +
include/linux/i3c/ccc.h | 1 +
include/linux/i3c/master.h | 20 +-
9 files changed, 476 insertions(+), 134 deletions(-)
--
2.43.0
^ permalink raw reply
* Re: [PATCH v6 02/10] arm64: tegra: Remove fallback compatible for GPCDMA
From: Thierry Reding @ 2026-06-24 10:22 UTC (permalink / raw)
To: Rob Herring
Cc: Akhil R, Thierry Reding, Vinod Koul, Frank Li,
Krzysztof Kozlowski, Conor Dooley, Jonathan Hunter,
Laxman Dewangan, Philipp Zabel, dmaengine, devicetree,
linux-tegra, linux-kernel
In-Reply-To: <CAL_Jsq+bbYZnE=Asv=2VnvTpSsLfKtdpcLvfPzn85hyiyp85cA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 828 bytes --]
On Tue, Jun 23, 2026 at 09:02:39AM -0500, Rob Herring wrote:
> On Tue, Mar 31, 2026 at 5:24 AM Akhil R <akhilrajeev@nvidia.com> wrote:
> >
> > Remove the fallback compatible string "nvidia,tegra186-gpcdma" for GPCDMA
> > in Tegra264. Tegra186 compatible cannot work on Tegra264 because of the
> > register offset changes and absence of the reset property.
> >
> > Fixes: 65ef237e4810 ("arm64: tegra: Add Tegra264 support")
> > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> > ---
> > arch/arm64/boot/dts/nvidia/tegra264.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Thierry, Are you going to apply this? The binding change has been
> picked up and now there's a warning.
Yes, I have this in my tree of fixes for 7.1 and plan to send it out
towards the end of this week.
Thierry
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [PATCH 2/2] arm64: dts: axiado: Add initial support for AX3005 SoC and eval board
From: Swark Yang @ 2026-06-24 10:21 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah
Cc: devicetree, linux-arm-kernel, linux-kernel, Swark Yang
In-Reply-To: <20260624-upstream-axiado-ax3005-upstream-v1-0-c05bd0bc9124@axiado.com>
Add initial device tree support for the AX3005 SoC and its evaluation
board. The AX3005 is a multi-core SoC featuring 4 Cortex-A53 cores, and
this adds the CPUs, timer, GPIO, UART, I2C, I3C, SPI and USB
controllers.
The AX3005 groups its low-speed controllers into four Slow Peripheral
(SP) blocks (SP0-SP3), each exposing its own I2C/I3C, SPI and UART
instances. The controllers are numbered by their per-SP hardware
instance ID, so the i2cN/spiN/uartN labels and their aliases are
intentionally non-contiguous and do not increase monotonically with
the register address.
Signed-off-by: Swark Yang <syang@axiado.com>
---
arch/arm64/boot/dts/axiado/Makefile | 1 +
arch/arm64/boot/dts/axiado/ax3005-evk.dts | 327 ++++++++++++
arch/arm64/boot/dts/axiado/ax3005.dtsi | 843 ++++++++++++++++++++++++++++++
3 files changed, 1171 insertions(+)
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
index 6676ad07db61..e71a0850a451 100644
--- a/arch/arm64/boot/dts/axiado/Makefile
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
+dtb-$(CONFIG_ARCH_AXIADO) += ax3005-evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3005-evk.dts b/arch/arm64/boot/dts/axiado/ax3005-evk.dts
new file mode 100644
index 000000000000..9187057eb7a5
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3005-evk.dts
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DTS file for Axiado AX3005 SoC based EVK
+ * Copyright (c) 2026 Axiado Corporation.
+ */
+
+/dts-v1/;
+
+#include "ax3005.dtsi"
+
+/ {
+ model = "Axiado AX3005 EVK";
+ compatible = "axiado,ax3005-evk", "axiado,ax3005";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i3c12;
+ i2c13 = &i3c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ i2c16 = &i2c16;
+ i2c17 = &i2c17;
+ i2c18 = &i2c18;
+ i2c19 = &i2c19;
+ i2c20 = &i2c20;
+ i2c21 = &i2c21;
+ i2c22 = &i2c22;
+ i2c23 = &i2c23;
+ i2c24 = &i2c24;
+ i2c25 = &i2c25;
+ i2c26 = &i2c26;
+ i2c27 = &i2c27;
+ i2c28 = &i2c28;
+ i2c29 = &i2c29;
+ i2c30 = &i2c30;
+ i2c31 = &i2c31;
+ i2c32 = &i2c32;
+ i2c33 = &i2c33;
+ i2c34 = &i2c34;
+ i2c35 = &i2c35;
+ i2c36 = &i2c36;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi5 = &spi5;
+ spi6 = &spi6;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* Cortex-A53 will use following memory map */
+ reg = <0x0 0x81000000 0x0 0x7f000000>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i3c12 {
+ status = "okay";
+};
+
+&i3c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&i2c16 {
+ status = "okay";
+};
+
+&i2c17 {
+ status = "okay";
+};
+
+&i2c18 {
+ status = "okay";
+};
+
+&i2c19 {
+ status = "okay";
+};
+
+&i2c20 {
+ status = "okay";
+};
+
+&i2c21 {
+ status = "okay";
+};
+
+&i2c22 {
+ status = "okay";
+};
+
+&i2c23 {
+ status = "okay";
+};
+
+&i2c24 {
+ status = "okay";
+};
+
+&i2c25 {
+ status = "okay";
+};
+
+&i2c26 {
+ status = "okay";
+};
+
+&i2c27 {
+ status = "okay";
+};
+
+&i2c28 {
+ status = "okay";
+};
+
+&i2c29 {
+ status = "okay";
+};
+
+&i2c30 {
+ status = "okay";
+};
+
+&i2c31 {
+ status = "okay";
+};
+
+&i2c32 {
+ status = "okay";
+};
+
+&i2c33 {
+ status = "okay";
+};
+
+&i2c34 {
+ status = "okay";
+};
+
+&i2c35 {
+ status = "okay";
+};
+
+&i2c36 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+};
+
+&spi3 {
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+};
+
+&spi6 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart6 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart8 {
+ status = "okay";
+};
+
+&usb2_0 {
+ status = "okay";
+};
+
+&usb2_1 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3005.dtsi b/arch/arm64/boot/dts/axiado/ax3005.dtsi
new file mode 100644
index 000000000000..3c2ce18082a9
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3005.dtsi
@@ -0,0 +1,843 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2026 Axiado Corporation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/memreserve/ 0x80002fa0 0x00000008;
+/ {
+ model = "Axiado AX3005";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ clocks {
+ refclk: clock-125000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ pclk: clock-100000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ sysclk: clock-200000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ spiclk: clock-400000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+ ranges;
+
+ gic500: interrupt-controller@40400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x40400000 0x0 0x10000>,
+ <0x0 0x40500000 0x0 0xc0000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* GPIO Controller banks 0 - 7 */
+ gpio0: gpio-controller@33000000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33000000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@33080000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33080000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@33100000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33100000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@33180000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33180000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@33200000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33200000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@33280000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33280000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@33300000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33300000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@33380000 {
+ compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33380000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@33000400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33000400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@33000800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33000800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@33080400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33080400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@33080800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33080800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@33100400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33100400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@33100800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33100800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@33200400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33200400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@33200800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33200800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@33280400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33280400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@33280800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33280800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c12: i3c@33300400 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x0 0x33300400 0x0 0x400>;
+ clock-names = "pclk", "sysclk";
+ clocks = <&pclk &sysclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c13: i3c@33300800 {
+ compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
+ reg = <0x0 0x33300800 0x0 0x400>;
+ clock-names = "pclk", "sysclk";
+ clocks = <&pclk &sysclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@33380400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33380400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@33380800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33380800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c16: i2c@33120400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33120400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@33021400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33021400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c18: i2c@33021800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33021800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@330c0400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x330c0400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c20: i2c@330c0800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x330c0800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c21: i2c@330c0c00 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x330c0c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c22: i2c@331a0800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x331a0800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c23: i2c@33302800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33302800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c24: i2c@33302c00 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33302c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c25: i2c@33303000 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33303000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c26: i2c@33382000 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33382000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c27: i2c@33382400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33382400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c28: i2c@33382800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33382800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c29: i2c@33382c00 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33382c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c30: i2c@33383000 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33383000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c31: i2c@33383400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33383400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c32: i2c@33383800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33383800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c33: i2c@33282400 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33282400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c34: i2c@33282800 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33282800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c35: i2c@33282c00 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33282c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c36: i2c@33283000 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x33283000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@33010000 {
+ compatible = "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x33010000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi1: spi@33090000 {
+ compatible = "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x33090000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi2: spi@333c0000 {
+ compatible = "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x333c0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi3: spi@330e0000 {
+ compatible = "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x330e0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi5: spi@33390000 {
+ compatible = "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x33390000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi6: spi@333a0000 {
+ compatible = "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x333a0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart0: serial@33020000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33020000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart1: serial@330a0000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x330a0000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart2: serial@33120000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33120000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart3: serial@33020800 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33020800 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart4: serial@331a0400 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x331a0400 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart5: serial@33381d00 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33381d00 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart6: serial@33381e00 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33381e00 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart7: serial@33381f00 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33381f00 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart8: serial@330c0000 {
+ compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x330c0000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ usb2_0: usb@41000000 {
+ compatible = "generic-xhci";
+ reg = <0x0 0x41000000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb2_1: usb@41100000 {
+ compatible = "generic-xhci";
+ reg = <0x0 0x41100000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb3_0: usb@41400000 {
+ compatible = "generic-xhci";
+ reg = <0x0 0x41400000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb3_1: usb@41500000 {
+ compatible = "generic-xhci";
+ reg = <0x0 0x41500000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: arm: axiado: add AX3005 EVK
From: Swark Yang @ 2026-06-24 10:21 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah
Cc: devicetree, linux-arm-kernel, linux-kernel, Swark Yang
In-Reply-To: <20260624-upstream-axiado-ax3005-upstream-v1-0-c05bd0bc9124@axiado.com>
Add device tree binding schema for the Axiado AX3005 SoC and its
associated evaluation board. This binding will be used for the
board-level DTS files that support the AX3005 platforms.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/arm/axiado.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/axiado.yaml b/Documentation/devicetree/bindings/arm/axiado.yaml
index bfabe7b32e65..008d2b1d4e62 100644
--- a/Documentation/devicetree/bindings/arm/axiado.yaml
+++ b/Documentation/devicetree/bindings/arm/axiado.yaml
@@ -20,4 +20,10 @@ properties:
- axiado,ax3000-evk # Axiado AX3000 Evaluation Board
- const: axiado,ax3000 # Axiado AX3000 SoC
+ - description: AX3005 based boards
+ items:
+ - enum:
+ - axiado,ax3005-evk # Axiado AX3005 Evaluation Board
+ - const: axiado,ax3005 # Axiado AX3005 SoC
+
additionalProperties: true
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] arm64: Add Axiado AX3005 SoC and EVK support
From: Swark Yang @ 2026-06-24 10:21 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah
Cc: devicetree, linux-arm-kernel, linux-kernel, Swark Yang
This series adds initial device tree support for the Axiado AX3005 SoC
and its evaluation board (EVK).
The AX3005 uses Cadence-derived UART/I2C/I3C/GPIO and Synopsys
DesignWare SPI IP blocks. These are already described by
existing bindings, so the device tree reuses the "axiado,ax3000-*",
"cdns,*" and "snps,*" compatible strings; only a new SoC/board
level compatible is added.
Patch 1 adds the AX3005 board/SoC compatible strings to the Axiado
platform binding.
Patch 2 adds the AX3005 SoC dtsi, the EVK board dts, and the Makefile
entry. The EVK enables the CPUs, timer, GPIO, UART, I2C, I3C, SPI and
USB controllers.
Validated with:
- make CHECK_DTBS=y axiado/ax3005-evk.dtb
- make dt_binding_check DT_SCHEMA_FILES=axiado.yaml
- boot-tested on the AX3005 EVK (to init CLI via ramfs)
Signed-off-by: Swark Yang <syang@axiado.com>
---
Swark Yang (2):
dt-bindings: arm: axiado: add AX3005 EVK
arm64: dts: axiado: Add initial support for AX3005 SoC and eval board
Documentation/devicetree/bindings/arm/axiado.yaml | 6 +
arch/arm64/boot/dts/axiado/Makefile | 1 +
arch/arm64/boot/dts/axiado/ax3005-evk.dts | 327 +++++++++
arch/arm64/boot/dts/axiado/ax3005.dtsi | 843 ++++++++++++++++++++++
4 files changed, 1177 insertions(+)
---
base-commit: 2b414a95b8f7307d42173ba9e580d6d3e2bcbfce
change-id: 20260617-upstream-axiado-ax3005-upstream-bb09780a2fdf
Best regards,
--
Swark Yang <syang@axiado.com>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: glymur: Add label properties to CoreSight devices
From: sashiko-bot @ 2026-06-24 10:18 UTC (permalink / raw)
To: Jie Gan; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260624-add-label-node-for-glymur-v1-1-87576107b999@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message incorrectly references the 'hamoa' device tree instead of 'glymur'.
--
commit 71aa487b99d4969110406291654e33f858011262
Author: Jie Gan <jie.gan@oss.qualcomm.com>
arm64: dts: qcom: glymur: Add label properties to CoreSight devices
This commit adds label properties to TPDM and CTI nodes to provide
human-readable identifiers for each CoreSight device.
> Add label properties to TPDM and CTI nodes in the hamoa device tree to
> provide human-readable identifiers for each CoreSight device. These
> labels allow userspace tools and the CoreSight framework to identify
> devices by name rather than by base address.
[Severity: Medium]
This isn't a bug, but the commit message explicitly states it is modifying
the "hamoa" device tree, while the patch subject and the actual modified
file (arch/arm64/boot/dts/qcom/glymur.dtsi) target "glymur". Could this
reference to "hamoa" be a copy-paste error from a similar patch?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260624-add-label-node-for-glymur-v1-1-87576107b999@oss.qualcomm.com?part=1
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: socfpga: agilex7-gen2: Add initial device tree
From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-06-24 10:17 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: dinguyen@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20260624-infallible-diligent-bulldog-bcbab2@quoll>
On 24/6/2026 3:57 pm, Krzysztof Kozlowski wrote:
> On Tue, Jun 23, 2026 at 04:17:16AM -0700, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> +
>> + psci {
>> + compatible = "arm,psci-0.2";
>> + method = "smc";
>> + };
>> +
>> + intc: interrupt-controller@7000000 {
>
> MMIO goes to MMIO, please read writing bindings and submitting patches docs in DT dir.
>
> I think this also fails tests (W=1). If that is true, then review should
> finish here, because instead of using machine to find issues you use
> community.
>
>> + compatible = "arm,gic-v3";
>> + reg = <0x0 0x7000000 0x0 0x10000>,
>> + <0x0 0x7080000 0x0 0x100000>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x40000>;
>> +
>> + its: msi-controller@7040000 {
>> + compatible = "arm,gic-v3-its";
>> + reg = <0x0 0x7040000 0x0 0x20000>;
>> + msi-controller;
>> + #msi-cells = <1>;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + compatible = "simple-bus";
>> + ranges = <0 0 0 0xffffffff>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + device_type = "soc";
>> + interrupt-parent = <&intc>;
>> +
>> + smmu: iommu@c100000 {
>> + compatible = "arm,smmu-v3";
>> + reg = <0x0c100000 0x30000>;
>> + interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "eventq", "gerror", "priq";
>> + dma-coherent;
>> + #iommu-cells = <1>;
>> + };
>> +
>> + ocram: sram@0 {
>> + compatible = "mmio-sram";
>> + reg = <0x00000000 0x80000>;
>> + ranges = <0 0 0x80000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> SoC without any interface, serial or storage or network, is close to
> useless one.
>
> I don't see a point in having it in mainline. Serial is usually ABSOLUTE
> minimum.
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
Thank you for the review and fast response!
I ran both dt_binding_check and dtbs_check (with CHECK_DTBS=y) locally —
both passed without errors. Could you clarify which specific test you
believe is failing?
Regarding "MMIO goes to MMIO" — are you referring to the GIC
(interrupt-controller@7000000) being placed at the root level instead of
under the soc bus node?
Regarding the serial console — the platform clock driver is not yet
upstream, so the UART depends on clkmgr. Would adding the UART with
clock-frequency be acceptable as an interim solution?
BR,
Nazim
^ permalink raw reply
* Re: [PATCH] dma-iommu: Introduce API to reserve IOVA regions for dynamically created devices
From: Krzysztof Kozlowski @ 2026-06-24 10:16 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Vishnu Reddy, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree, Vikash Garodia, Robin Murphy, joro, will,
m.szyprowski, iommu, linux-kernel, dikshita.agarwal
In-Reply-To: <20260618151745.GD231643@ziepe.ca>
On 18/06/2026 17:17, Jason Gunthorpe wrote:
> On Thu, Jun 18, 2026 at 01:57:40PM +0200, Krzysztof Kozlowski wrote:
>
>> Same with interrupt-map.
>
>> There are PCIe controller nodes which have interrupt-map and no
>> interrupts property ever uses them.
>
> PCIe is quite a different situation because we expect Linux to
> dynamically create the child nodes based on PCIe discovery, and the
> various maps are all searched based on the PCI BDF based on HW
> properties of real discovered child devices.
>
> Here they created "vpu_bus" and create a bunch of devices for some
> reason, but they are all hard coded in the driver. It is not a dynamic
> discovery, and it is not creating "real" child devices.
Yes, true.
>
>> Because DT person - me - told that creating child device nodes just to
>> configure iommus is abuse of DT. There are no child devices in terms of
>> hardware or firmware. The iommu ranges here are no real hardware.
>
> That doesn't seem to be what Vishnu is saying. Review the earlier two
> emails explaining what the HW issue is here:
>
> https://lore.kernel.org/all/bb59f07e-ca7e-f012-6a4b-0a148350b69c@oss.qualcomm.com/
> https://lore.kernel.org/all/cb37e7cc-4fb0-4c24-8f89-f6f9eb08a107@oss.qualcomm.com/
>
> The VPU HW diagram with different IOVA requirements for different
> stream IDs seems to be an entirely HW based thing: "each context bank
> enforces a different IOVA range"
>
> The original patches just created a 0 based IOVA space per stream and
> justified that by increasing the IOVA address space (make sense). The
> email above now says some of the streams only function with a limited
> range of IOVA because the HW uses the IOVA itself to select the
> streams (insane!)
>
> IOW this entire device is completely mis-designed if it is going to
> easially support the Linux DMA API :( That's all HW mess, which is
> motivating hacks to try to make the Linux DMA API do something usable
> by this device.
>
> Anyhow..
>
> In Linux if you use DT iommus the SW sets things up so every stream
> shares the same translation. If your driver/device doesn't like that
> there is no SW way to opt out of sharing. I think that is the first
> core issue that VPU was struggling with.
>
> If you have one "device" then I would argue the DT should describe all
> its streams using iommus in the normal way. The introduction of
> iommu-map for VPU is only being done because that is a convenient hack
> to allow Linux to unbundle the streams. It would be much harder to
> unbunble the streams directly from the DT iommus property, but that
> would probably be the cleanest, software agnostic, DT modeling.
>
> So, if we are going to do a hack in DT to accomodate Linux, I argue to
> choose explicit child devices so VPU does not need to create a special
> bus, call of_dma_configue, or hack in new DMA API things that only it
> will ever use. Then the explicit children can properly describe how
> the HW decodes IOVA into each streams in the DT (which sounds very
> much like a HW property to me) so that Linux produces IOVA that the HW
> mangling properly routes to the expected stream.
>
> Then the VPU driver just has to assemble itself from many struct
> devices, which I admit is also a troublesome task.
>
>> However, said all this, since I pushed folks to come with the iommu-map
>> approach, I will revoke my disagreement to child device nodes in DT, if
>> you really believe that is the approach. IOW, I will agree to device
>> nodes in DT representing fake hardware-children, just for the sake of
>> Linux driver model limitations.
>
> I would wait for Robin, he knows this better, but I belive this was
> broadly his point in the original email..
Thanks Jason for context and detailed arguments. Robin did not chime in
yet, but from what I understood the DT-child-node approach will be the
way we should go here.
I accept above point of view and I am fine with this, thus Vishnu and
Vikash - please go ahead with DT-child-node solution we had some time ago.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH net] net: ethernet: qualcomm: ppe: Demote from supported and fix maintainer addresses
From: Jie Luo @ 2026-06-24 10:16 UTC (permalink / raw)
To: Andrew Lunn
Cc: Krzysztof Kozlowski, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Brian Masney, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Lei Wei, Suruchi Agarwal, Pavithra R,
linux-kernel, linux-arm-msm, linux-clk, devicetree, netdev,
Kiran Kumar C.S.K, quic_linchen
In-Reply-To: <7095f7ba-bacb-4d03-89cf-ed43882d8213@lunn.ch>
On 6/23/2026 7:31 PM, Andrew Lunn wrote:
> On Tue, Jun 23, 2026 at 05:42:34PM +0800, Jie Luo wrote:
>>
>>
>> On 6/23/2026 4:10 PM, Andrew Lunn wrote:
>>>> Driver is not supported - in terms of how netdev understands supported
>>>> commitment - if maintainer does not care to receive the patches for its
>>>> code, so demote it to "maintained" to reflect true status.
>>>
>>> Maybe "Orphan" would be better, if the listed Maintainer is not doing
>>> any Maintainer work?
>>>
>>> Andrew
>>
>> Hello Andrew, Krzysztof,
>> I will continue to maintain the listed drivers, so their status can
>> remain Supported.
>
> Please understand that being a Maintainer requires that you respond to
> patches and questions about this driver, give Reviewed-by:, ask for
> patches to be changed etc. If you don't respond, ideally with 2 to 3
> days, the driver will be set to Orphaned.
>
> If you want to maintain the Supported status, we can help you set up
> the needed CI system, and get it registered so it reports the results.
>
> Andrew
Thank you Andrew, Krzysztof, for the clarification on what "Supported"
status entails and for the offer to help with CI setup. I would very
much appreciate the community's help in getting the CI system set up
and registered for this driver. In the mean time we will also look at
resources internally within Qualcomm, to understand how to support
testing using kernelCI/netdevCI for IPQ SoC. This will help us test
the driver continuously as well.
I fully understand and accept the maintainer responsibilities for this
driver, and commit to the below:
- Responding to patches and questions in a timely manner.
- Providing review comments and requesting changes where appropriate,
and providing Reviewed-by tags when needed.
I would also like to take a moment to provide an update on our current
efforts for IPQ SoC, if it can be of help. We have already re-started
our efforts for the drivers and are currently actively working to extend
the IPQ drivers to support more functionality and for newer SoC support
for same family. We plan to post these updates to the current drivers
once the review window reopens.
We feel maintaining the "Supported" status is appropriate and reflects
our genuine long-term commitment to IPQ SoC networking drivers in Linux
kernel. We request you to retain the current status for this driver if
acceptable.
Regarding the email ID change, we had attempted to rectify the
MAINTAINERS file a few months ago based on recommendation given
internally (please see below thread), however agree that such an update
in documentation is also required.
https://lore.kernel.org/all/20250903-maintainer_update-v1-1-2183fd2a3c44@oss.qualcomm.com/
^ permalink raw reply
* [PATCH] arm64: dts: qcom: glymur: Add label properties to CoreSight devices
From: Jie Gan @ 2026-06-24 10:09 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
Add label properties to TPDM and CTI nodes in the hamoa device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 20b49af7298e..27cc30de940e 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -5770,6 +5770,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -5834,6 +5835,7 @@ tpdm@1102c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
@@ -5852,6 +5854,7 @@ tpdm@11180000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -5871,6 +5874,7 @@ tpdm@11185000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_dpm_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -5890,6 +5894,7 @@ tpdm@11186000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_dpm_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -6010,6 +6015,7 @@ cti@11193000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp";
};
cti_wpss: cti@111ab000 {
@@ -6018,6 +6024,7 @@ cti_wpss: cti@111ab000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_wpss";
};
tpdm@111d0000 {
@@ -6026,6 +6033,7 @@ tpdm@111d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-msrs-num = <32>;
@@ -6201,6 +6209,7 @@ tpdm@11207000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_dsb";
qcom,dsb-msrs-num = <32>;
@@ -6219,6 +6228,7 @@ tpdm@1120b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_east_dsb";
qcom,dsb-msrs-num = <32>;
@@ -6237,6 +6247,7 @@ tpdm@11213000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_west_dsb";
qcom,dsb-msrs-num = <32>;
@@ -6255,6 +6266,7 @@ tpdm@11219000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_center_dsb";
qcom,dsb-msrs-num = <32>;
@@ -6273,6 +6285,7 @@ tpdm@1121a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc";
qcom,cmb-msrs-num = <32>;
@@ -6291,6 +6304,7 @@ tpdm@1121b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qrng";
qcom,cmb-msrs-num = <32>;
@@ -6309,6 +6323,7 @@ tpdm@1121c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pmu";
qcom,dsb-msrs-num = <32>;
@@ -6327,6 +6342,7 @@ tpdm@1121d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cx";
qcom,cmb-msrs-num = <32>;
@@ -6345,6 +6361,7 @@ tpdm@1121e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mxc";
qcom,cmb-msrs-num = <32>;
@@ -6363,6 +6380,7 @@ tpdm@1121f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mxa";
qcom,cmb-msrs-num = <32>;
@@ -6381,6 +6399,7 @@ tpdm@11220000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_center_dsb_1";
qcom,dsb-msrs-num = <32>;
@@ -6399,6 +6418,7 @@ tpdm@11224000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_south2_dsb";
qcom,dsb-msrs-num = <32>;
@@ -6417,6 +6437,7 @@ tpdm@11228000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
@@ -6435,6 +6456,7 @@ tpdm@11470000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pcie_rscc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -6478,6 +6500,7 @@ tpdm@11c03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_4";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -6656,6 +6679,7 @@ tpdm@11c09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -6675,6 +6699,7 @@ tpdm@11c0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -6694,6 +6719,7 @@ tpdm@11c0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -6713,6 +6739,7 @@ tpdm@11c0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -6732,6 +6759,7 @@ tpdm@11c0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
---
base-commit: 4e5dfb7c84012007c3c7061126491bbc92d71bf1
change-id: 20260624-add-label-node-for-glymur-1ba59f479870
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH 0/4] input: misc: Add an initial driver for haptics inside Qcom PMIH010x PMIC
From: Krzysztof Kozlowski @ 2026-06-24 10:05 UTC (permalink / raw)
To: Fenglin Wu
Cc: linux-arm-msm, Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Stephen Boyd, Bjorn Andersson,
Konrad Dybcio, David Collins, Subbaraman Narayanamurthy,
Kamal Wadhwa, kernel, linux-input, devicetree, linux-kernel
In-Reply-To: <be2b54a5-ce9d-49a2-80e1-60da874350d9@oss.qualcomm.com>
On 24/06/2026 09:20, Fenglin Wu wrote:
>
> On 6/17/2026 6:42 PM, Krzysztof Kozlowski wrote:
>> On Tue, Jun 16, 2026 at 03:08:23AM -0700, Fenglin Wu wrote:
>>
>> Here - the first sentence - is where you mention merging
>> constraints/strategy/dependencies. Your MFD patch depends on ealier
>> ones.
>>
> Did you mean that these 2 MFD binding changes should be listed as the
> dependency of the MFD patch?
No. Act as maintainer. Clone Linus tree, apply the patch and see if
everything works. My claim is that nothing works and maintainer tree is
broken.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 14/14] video: leds: backlight: lm3533: Support getting LED sources from DT
From: Daniel Thompson @ 2026-06-24 10:04 UTC (permalink / raw)
To: Svyatoslav Ryhel
Cc: Lee Jones, Jingoo Han, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jonathan Cameron,
David Lechner, Nuno Sá, Andy Shevchenko, Helge Deller,
Johan Hovold, dri-devel, linux-leds, devicetree, linux-kernel,
linux-iio, linux-fbdev
In-Reply-To: <20260617080031.99156-15-clamor95@gmail.com>
On Wed, Jun 17, 2026 at 11:00:31AM +0300, Svyatoslav Ryhel wrote:
> Add Control Bank to HVLED/LVLED muxing support based on the led-sources
> defined in the device tree.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Daniel Thompson (RISCstar) <danielt@kernel.org>
Daniel.
^ permalink raw reply
* RE: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
From: Biju Das @ 2026-06-24 10:04 UTC (permalink / raw)
To: Krzysztof Kozlowski, biju.das.au
Cc: Geert Uytterhoeven, Alex Helms, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, magnus.damm,
Brian Masney, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad
In-Reply-To: <610f349f-b88a-440c-bae2-14199d047d12@kernel.org>
Hi Krzysztof Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 24 June 2026 11:01
> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
>
> On 24/06/2026 11:59, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 24 June 2026 10:52
> >> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update
> >> maintainer
> >>
> >> On 24/06/2026 11:46, Biju Das wrote:
> >>> Hi Krzysztof Kozlowski,
> >>>
> >>>> -----Original Message-----
> >>>> From: Krzysztof Kozlowski <krzk@kernel.org>
> >>>> Sent: 24 June 2026 10:42
> >>>> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7:
> >>>> Update maintainer
> >>>>
> >>>> On Tue, Jun 23, 2026 at 05:20:37PM +0100, Biju wrote:
> >>>>> From: Biju Das <biju.das.jz@bp.renesas.com>
> >>>>>
> >>>>> Alex's email is bouncing. Update the maintainers list with my
> >>>>> contact details to take over the schema maintenance.
> >>>>>
> >>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>>>> ---
> >>>>> Ref [1]
> >>>>> [1] https://lore.kernel.org/all/ajqWevofEJ3fv856@redhat.com/
> >>>>> ---
> >>>>> .../devicetree/bindings/clock/renesas,versaclock7.yaml | 2 +-
> >>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> Please also update MAINTAINERS file.
> >>>
> >>> It is taken care in [1]
> >>>
> >>> [1]
> >>> https://lore.kernel.org/all/CAMuHMdW0-WsZuuc7PoVNC5DBUoY9dP+ULmGTQ76
> >>> VW
> >>> MO_SjpbuQ@mail.gmail.com/
> >>
> >> Just squash them together.
> >>
> >> When you fix such issue like wrong email, fix it everywhere, not just
> >> one-by-one where the maintainers need to poke you to fix in other
> >> places as well. It is generic rule for bugs as well. The wrong email address is the most obvious
> example here, because it is also extremely easy. Just use git grep.
> >
> > Ok, but both patches were already queued by Geert for 7.3.
> >
> > The MAINTAINERS file patch is 9 months old patch.
>
>
> Hm? How or what exactly is 9 months old? I did `git grep` now and I still see old email entry in next-
> 20260619
Not sure, that patch is posted on Sep 05, 2025
and based on Brian's request Geert queued it.
See below
> On Fri, Sep 05, 2025 at 03:34:38PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add entries for Renesas versaclock 3 clock driver. While at it
> > add myself as maintainer for versaclock 7 clock driver as Alex's
> > email address bounces.
Cheers,
Biju
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: qcom: glymur-crd: Move common board nodes to shared DTSI
From: Pankaj Patil @ 2026-06-24 10:02 UTC (permalink / raw)
To: Gopikrishna Garmidi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, sibi.sankar,
rajendra.nayak
In-Reply-To: <b61ec109-92db-4dc1-ba7d-a5ce79fea08a@oss.qualcomm.com>
On 6/8/2026 3:33 PM, Gopikrishna Garmidi wrote:
>
>
> On 5/19/2026 7:55 PM, Gopikrishna Garmidi wrote:
>> The Glymur and Mahua CRDs use the same board-level hardware for the
>> eDP display panel, MDSS DP3 controller and PHY, USB-C ports (via
>> pmic-glink), USB 0/1/HS/MP controllers, QMP PHYs, eUSB2 repeaters,
>> HID peripherals (touchpad, keyboard, touchscreen) and their dependent
>> regulators and pin control states. This has been verified against
>> both CRD schematics.
>>
>> Move these nodes from glymur-crd.dts to glymur-crd.dtsi to enable code
>> reuse with the Mahua CRD.
>>
>> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
>> ---
>> Changes in v2:
>> - Rebased on top of next-20260518
>> - Updated subject to include glymur-crd scope prefix
>> - Rewrote commit message to describe the actual shared physical hardware
>> rather than the code-sharing intent; the commonality was verified
>> against Glymur CRD and Mahua CRD schematics
>> - Link to v1: https://lore.kernel.org/r/20260326-glymur-mahua-common-nodes-v1-1-12bb26920ea4@oss.qualcomm.com
>> ---
>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 399 -------------------------------
>> arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 396 ++++++++++++++++++++++++++++++
>> 2 files changed, 396 insertions(+), 399 deletions(-)
>
>
> Hi Krzysztof, Konrad,
>
> This has been waiting for a while now and already has a Reviewed-by from Dmitry. Could you take a look when you get a chance?
>
> Thanks,
> Gopikrishna Garmidi
Krzystof,
We've verified from the schematics the soc gpio and other lines do not change and are pin to pin compatible with glymur,
The only change are the external peripherals connected
Thanks,
Pankaj
Reviewed-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v5 2/2] backlight: Add SY7758 6-channel High Efficiency LED Driver support
From: Daniel Thompson @ 2026-06-24 10:00 UTC (permalink / raw)
To: Neil Armstrong
Cc: Lee Jones, Jingoo Han, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Helge Deller, dri-devel,
linux-leds, devicetree, linux-kernel, linux-fbdev, KancyJoe
In-Reply-To: <20260529-topic-sm8650-ayaneo-pocket-s2-sy7758-v5-2-03aacd49747c@linaro.org>
On Fri, May 29, 2026 at 09:23:09PM +0200, Neil Armstrong wrote:
> From: KancyJoe <kancy2333@outlook.com>
>
> Implement support for the Silergy SY7758 6-channel High Efficiency LED
> Driver used for backlight brightness control in the Ayaneo Pocket S2
> dual-DSI panel.
>
> Signed-off-by: KancyJoe <kancy2333@outlook.com>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Daniel Thompson (RISCstar) <danielt@kernel.org>
Daniel.
^ permalink raw reply
* Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
From: Krzysztof Kozlowski @ 2026-06-24 10:00 UTC (permalink / raw)
To: Biju Das, biju.das.au
Cc: Geert Uytterhoeven, Alex Helms, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, magnus.damm,
Brian Masney, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad
In-Reply-To: <TY3PR01MB11346A6077B4F7380078EA3B486ED2@TY3PR01MB11346.jpnprd01.prod.outlook.com>
On 24/06/2026 11:59, Biju Das wrote:
> Hi Krzysztof Kozlowski,
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 24 June 2026 10:52
>> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
>>
>> On 24/06/2026 11:46, Biju Das wrote:
>>> Hi Krzysztof Kozlowski,
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <krzk@kernel.org>
>>>> Sent: 24 June 2026 10:42
>>>> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update
>>>> maintainer
>>>>
>>>> On Tue, Jun 23, 2026 at 05:20:37PM +0100, Biju wrote:
>>>>> From: Biju Das <biju.das.jz@bp.renesas.com>
>>>>>
>>>>> Alex's email is bouncing. Update the maintainers list with my
>>>>> contact details to take over the schema maintenance.
>>>>>
>>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>>>> ---
>>>>> Ref [1]
>>>>> [1] https://lore.kernel.org/all/ajqWevofEJ3fv856@redhat.com/
>>>>> ---
>>>>> .../devicetree/bindings/clock/renesas,versaclock7.yaml | 2 +-
>>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> Please also update MAINTAINERS file.
>>>
>>> It is taken care in [1]
>>>
>>> [1]
>>> https://lore.kernel.org/all/CAMuHMdW0-WsZuuc7PoVNC5DBUoY9dP+ULmGTQ76VW
>>> MO_SjpbuQ@mail.gmail.com/
>>
>> Just squash them together.
>>
>> When you fix such issue like wrong email, fix it everywhere, not just one-by-one where the maintainers
>> need to poke you to fix in other places as well. It is generic rule for bugs as well. The wrong email
>> address is the most obvious example here, because it is also extremely easy. Just use git grep.
>
> Ok, but both patches were already queued by Geert for 7.3.
>
> The MAINTAINERS file patch is 9 months old patch.
Hm? How or what exactly is 9 months old? I did `git grep` now and I
still see old email entry in next-20260619
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 1/2] dt-bindings: leds: backlight: document the SY7758 6-channel High Efficiency LED Driver
From: Daniel Thompson @ 2026-06-24 10:00 UTC (permalink / raw)
To: Neil Armstrong
Cc: Lee Jones, Jingoo Han, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Helge Deller, dri-devel,
linux-leds, devicetree, linux-kernel, linux-fbdev, KancyJoe,
Krzysztof Kozlowski
In-Reply-To: <20260529-topic-sm8650-ayaneo-pocket-s2-sy7758-v5-1-03aacd49747c@linaro.org>
On Fri, May 29, 2026 at 09:23:08PM +0200, Neil Armstrong wrote:
> Document the Silergy SY7758 6-channel High Efficiency LED Driver
> used for backlight brightness control.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Daniel Thompson (RISCstar) <danielt@kernel.org>
Daniel.
^ permalink raw reply
* RE: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
From: Biju Das @ 2026-06-24 9:59 UTC (permalink / raw)
To: Krzysztof Kozlowski, biju.das.au
Cc: Geert Uytterhoeven, Alex Helms, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, magnus.damm,
Brian Masney, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad
In-Reply-To: <77976912-b0b0-4e08-ad9c-5080c4d8adcc@kernel.org>
Hi Krzysztof Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 24 June 2026 10:52
> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
>
> On 24/06/2026 11:46, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 24 June 2026 10:42
> >> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update
> >> maintainer
> >>
> >> On Tue, Jun 23, 2026 at 05:20:37PM +0100, Biju wrote:
> >>> From: Biju Das <biju.das.jz@bp.renesas.com>
> >>>
> >>> Alex's email is bouncing. Update the maintainers list with my
> >>> contact details to take over the schema maintenance.
> >>>
> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>> ---
> >>> Ref [1]
> >>> [1] https://lore.kernel.org/all/ajqWevofEJ3fv856@redhat.com/
> >>> ---
> >>> .../devicetree/bindings/clock/renesas,versaclock7.yaml | 2 +-
> >>> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> Please also update MAINTAINERS file.
> >
> > It is taken care in [1]
> >
> > [1]
> > https://lore.kernel.org/all/CAMuHMdW0-WsZuuc7PoVNC5DBUoY9dP+ULmGTQ76VW
> > MO_SjpbuQ@mail.gmail.com/
>
> Just squash them together.
>
> When you fix such issue like wrong email, fix it everywhere, not just one-by-one where the maintainers
> need to poke you to fix in other places as well. It is generic rule for bugs as well. The wrong email
> address is the most obvious example here, because it is also extremely easy. Just use git grep.
Ok, but both patches were already queued by Geert for 7.3.
The MAINTAINERS file patch is 9 months old patch.
Cheers,
Biju
^ permalink raw reply
* Re: [PATCH 07/12] rtc: rzn1: fix alarm range check truncation on 32-bit systems
From: Lad, Prabhakar @ 2026-06-24 9:53 UTC (permalink / raw)
To: Wolfram Sang
Cc: Miquel Raynal, Alexandre Belloni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
Magnus Damm, linux-rtc, linux-renesas-soc, devicetree,
linux-kernel, Biju Das, Fabrizio Castro, Lad Prabhakar
In-Reply-To: <ajr1wXCI2U23d1sY@shikoro>
Hi Wolfram,
On Tue, Jun 23, 2026 at 10:08 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
>
> > Can you please share the commands you tried, I'll try and replicate it
> > on my side.
>
> Sorry, can't give you the commands, just from my head: I tried to set an
> alarm more than a week in the future, and the alarm was set to the next
> day. But I was in a hurry, maybe I overlooked something, because that
> handling used to work in the past IIRC. I can return to this topic on
> Friday earliest, sadly. Maybe next week only...
>
I ran some tests for cases #1 and #2, and we see an out-of-range
error. By adding a 1-sec leeway when checking the ranges I don't get
the out-of-range error. Let me know what you think (I'll create a
seprate patch for it).
Case #1 reverting this patch:
root@rzn2h-evk:~# date -s "2026-06-24 10:34:00"; hwclock -w;
Wed Jun 24 10:34:00 UTC 2026
root@rzn2h-evk:~#
root@rzn2h-evk:~#
root@rzn2h-evk:~# rtcwake -m no -s 604800;cat /proc/driver/rtc
rtcwake: set rtc wake alarm failed: Numerical result out of range
rtc_time : 10:34:32
rtc_date : 2026-06-24
alrm_time : 10:34:33
alrm_date : 2026-07-01
alarm_IRQ : no
alrm_pending : no
update IRQ enabled : no
periodic IRQ enabled : no
periodic IRQ frequency : 1
max user IRQ frequency : 64
24hr : yes
root@rzn2h-evk:~#
Case #2 with this patch:
root@rzn2h-evk:~# date -s "2026-06-24 10:46:00"; hwclock -w;
Wed Jun 24 10:46:00 UTC 2026
root@rzn2h-evk:~# rtcwake -m no -s 604800;cat /proc/driver/rtc
rtcwake: set rtc wake alarm failed: Numerical result out of range
rtc_time : 10:46:30
rtc_date : 2026-06-24
alrm_time : 10:46:31
alrm_date : 2026-07-01
alarm_IRQ : no
alrm_pending : no
update IRQ enabled : no
periodic IRQ enabled : no
periodic IRQ frequency : 1
max user IRQ frequency : 64
24hr : yes
root@rzn2h-evk:~#
Case #3: Add 1-sec leeway:
root@rzn2h-evk:~# date -s "2026-06-24 10:48:00"; hwclock -w;
Wed Jun 24 10:48:00 UTC 2026
root@rzn2h-evk:~# rtcwake -m no -s 604800;cat /proc/driver/rtc
rtcwake: wakeup using /dev/rtc0 at Wed Jul 1 10:48:50 2026
rtc_time : 10:48:49
rtc_date : 2026-06-24
alrm_time : 10:48:50
alrm_date : 2026-07-01
alarm_IRQ : yes
alrm_pending : no
update IRQ enabled : no
periodic IRQ enabled : no
periodic IRQ frequency : 1
max user IRQ frequency : 64
24hr : yes
root@rzn2h-evk:~#
Changes for case #3:
diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
index 173526d50d41..8fdb5114a6d8 100644
--- a/drivers/rtc/rtc-rzn1.c
+++ b/drivers/rtc/rtc-rzn1.c
@@ -279,7 +279,9 @@ static int rzn1_rtc_set_alarm(struct device *dev,
struct rtc_wkalrm *alrm)
/* We cannot set alarms more than one week ahead */
farest = rtc_tm_to_time64(&tm_now) + rtc->rtcdev->alarm_offset_max;
alarm = rtc_tm_to_time64(tm);
- if (alarm > farest)
+
+ /* Add a 1-second leeway for processing delay */
+ if (alarm > (farest + 1))
return -ERANGE;
/* Convert alarm day into week day */
Cheers,
Prabhakar
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: arm: qcom,coresight-tnoc: allow arm,primecell-periphid
From: sashiko-bot @ 2026-06-24 9:54 UTC (permalink / raw)
To: Jie Gan; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260624-fix-tracenoc-probe-issue-v2-1-786520f62f21@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Setting `additionalProperties: true` completely disables strict schema validation for undefined properties, allowing misspelled or undocumented properties to silently pass.
--
commit 6e8606766f1fd41047be4a5d6a3178b5f3fd67e9
Author: Jie Gan <jie.gan@oss.qualcomm.com>
dt-bindings: arm: qcom,coresight-tnoc: allow arm,primecell-periphid
This commit updates the qcom,coresight-tnoc binding to reference
primecell.yaml. It changes additionalProperties to true to allow
the arm,primecell-periphid property along with other common properties.
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
[ ... ]
> @@ -78,7 +81,7 @@ required:
> - in-ports
> - out-ports
>
> -additionalProperties: false
> +additionalProperties: true
[Severity: Medium]
Does setting additionalProperties to true completely disable strict schema
validation for this node?
It looks like this change will cause misspelled properties to silently pass
during make dt_binding_check. When adding a $ref in an allOf block, should
unevaluatedProperties: false be used instead? That would allow the inherited
primecell.yaml properties to pass while still rejecting any undefined or
typoed properties.
>
> examples:
> - |
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260624-fix-tracenoc-probe-issue-v2-0-786520f62f21@oss.qualcomm.com?part=1
^ permalink raw reply
* Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
From: Krzysztof Kozlowski @ 2026-06-24 9:51 UTC (permalink / raw)
To: Biju Das, biju.das.au
Cc: Geert Uytterhoeven, Alex Helms, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, magnus.damm,
Brian Masney, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad
In-Reply-To: <TY3PR01MB11346659E1A238C232E29946686ED2@TY3PR01MB11346.jpnprd01.prod.outlook.com>
On 24/06/2026 11:46, Biju Das wrote:
> Hi Krzysztof Kozlowski,
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 24 June 2026 10:42
>> Subject: Re: [PATCH] dt-bindings: clock: renesas,versaclock7: Update maintainer
>>
>> On Tue, Jun 23, 2026 at 05:20:37PM +0100, Biju wrote:
>>> From: Biju Das <biju.das.jz@bp.renesas.com>
>>>
>>> Alex's email is bouncing. Update the maintainers list with my contact
>>> details to take over the schema maintenance.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> ---
>>> Ref [1]
>>> [1] https://lore.kernel.org/all/ajqWevofEJ3fv856@redhat.com/
>>> ---
>>> .../devicetree/bindings/clock/renesas,versaclock7.yaml | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> Please also update MAINTAINERS file.
>
> It is taken care in [1]
>
> [1] https://lore.kernel.org/all/CAMuHMdW0-WsZuuc7PoVNC5DBUoY9dP+ULmGTQ76VWMO_SjpbuQ@mail.gmail.com/
Just squash them together.
When you fix such issue like wrong email, fix it everywhere, not just
one-by-one where the maintainers need to poke you to fix in other places
as well. It is generic rule for bugs as well. The wrong email address is
the most obvious example here, because it is also extremely easy. Just
use git grep.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: qcom: kaanapali: fix traceNoC probe issue
From: Jie Gan @ 2026-06-24 9:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jingyi Wang, Jie Gan, Abel Vesa,
Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Yuanfang Zhang
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel, coresight,
linux-arm-kernel
In-Reply-To: <20260624-fix-tracenoc-probe-issue-v2-0-786520f62f21@oss.qualcomm.com>
The AMBA bus attempts to read the CID/PID of a device before invoking
its probe function if the arm,primecell-periphid property is absent.
This causes a deferred probe issue for the TraceNoC device, as the
CID/PID cannot be read from the periphid register.
Add the arm,primecell-periphid property to bypass the AMBA bus
check and resolve the probe issue.
Fixes: f73959d86c15 ("arm64: dts: qcom: kaanapali: add coresight nodes")
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7aa9653bd456..25820f7c04cd 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -5009,6 +5009,7 @@ tn@111b8000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ arm,primecell-periphid = <0x000f0c00>;
in-ports {
#address-cells = <1>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: arm: qcom,coresight-tnoc: allow arm,primecell-periphid
From: Jie Gan @ 2026-06-24 9:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jingyi Wang, Jie Gan, Abel Vesa,
Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Yuanfang Zhang
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel, coresight,
linux-arm-kernel
In-Reply-To: <20260624-fix-tracenoc-probe-issue-v2-0-786520f62f21@oss.qualcomm.com>
The TNOC device is an AMBA primecell and may carry the standard
arm,primecell-periphid property, which is used to supply the
peripheral ID when it cannot be read from the device registers.
Reference primecell.yaml and set additionalProperties to true so the
binding accepts arm,primecell-periphid along with the other common
primecell properties.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
index ef648a15b806..9624fc0adfdc 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
@@ -32,6 +32,9 @@ select:
required:
- compatible
+allOf:
+ - $ref: /schemas/arm/primecell.yaml#
+
properties:
$nodename:
pattern: "^tn(@[0-9a-f]+)$"
@@ -78,7 +81,7 @@ required:
- in-ports
- out-ports
-additionalProperties: false
+additionalProperties: true
examples:
- |
--
2.34.1
^ permalink raw reply related
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