Re: [PATCH v2 4/4] arm64: dts: qcom: sc8280xp: add Radxa Dragon Q8B

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] arm64: dts: qcom: swapped vdda-phy-supply and vdda-pll-supply in mdss0_dp2_phy
--

commit 1ed6dcf998cee616c10f9c98d191dd8e63e625e3
Author: Xilin Wu <sophon@radxa.com>

arm64: dts: qcom: sc8280xp: add Radxa Dragon Q8B

This commit adds initial device tree support for the Radxa Dragon Q8B
single-board computer. It describes various hardware components including
storage, PCIe, USB-C, HDMI output, audio, and multiple regulators.

> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts b/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts
> new file mode 100644
> index 0000000000000..322b66de6ef68
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts
> @@ -0,0 +1,2102 @@
[ ... ]
> +		vreg_l3b: ldo3 {
> +			regulator-name = "vreg_l3b";
> +			regulator-min-microvolt = <1200000>;
> +			regulator-max-microvolt = <1200000>;
> +			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +			regulator-boot-on;
> +			regulator-allow-set-load;
> +			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> +						   RPMH_REGULATOR_MODE_HPM>;
> +		};
[ ... ]
> +		vreg_l6b: ldo6 {
> +			regulator-name = "vreg_l6b";
> +			regulator-min-microvolt = <880000>;
> +			regulator-max-microvolt = <880000>;
> +			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +			regulator-boot-on;
> +			regulator-allow-set-load;
> +			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
> +						   RPMH_REGULATOR_MODE_HPM>;
> +		};
[ ... ]
> +&mdss0_dp2_phy {
> +	vdda-phy-supply = <&vreg_l3b>;
> +	vdda-pll-supply = <&vreg_l6b>;

[Severity: High]
Are the core analog PHY supply and PLL supply swapped here?

The vdda-phy-supply is connected to <&vreg_l3b> (which is configured as 1.2V
above), and vdda-pll-supply is connected to <&vreg_l6b> (configured as 0.88V).
For Qualcomm DisplayPort PHYs, the core analog PHY supply requires the lower
voltage rail (0.88V), and the PLL supply requires the higher voltage rail
(1.2V). 

Could this apply 1.2V to the 0.88V core domain, potentially preventing the PHY
from initializing or causing overvoltage damage? For comparison, usb_0_qmpphy
in this same file correctly uses the lower voltage for vdda-phy-supply and the
higher voltage for vdda-pll-supply.

> +
> +	status = "okay";
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261009-q8b-dts-v2-0-eda11e5dea8b@radxa.com?part=4