Re: [PATCH 4/5] arm64: dts: freescale: Add LVDS overlays for TQMa8Xx

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: unit address mismatch in dc0_pc channel@1 breaks LVDS1 hardware mapping
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commit 9e71d1e0ae4bcdbdae19947de71699d2eb47af70
Author: Alexander Stein <alexander.stein@ew.tq-group.com>

arm64: dts: freescale: Add LVDS overlays for TQMa8Xx

Add overlays for the supported LVDS display tianma tm070jvhg33 on both
LVDS0 and LVDS1 channels on connector X14 (+ control on X22).
The corresponding display controller PLL is configured with 10x the
pixelclock.

> diff --git a/arch/arm64/boot/dts/freescale/mba8xx-lvds1-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/mba8xx-lvds1-tm070jvhg33.dtso
> new file mode 100644
> index 0000000000000..4a8ba61962725
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/mba8xx-lvds1-tm070jvhg33.dtso

[ ... ]

> +&dc0_pc {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	channel@1 {
> +		reg = <0>;

[Severity: High]
Does this reg value incorrectly map channel@1 to hardware index 0 instead of 1?

It appears this overrides the channel@1 child node of &dc0_pc but explicitly
sets reg = <0>. This will incorrectly update hardware channel 0, overriding the
base device tree which expects channel 1, and will also trigger a DTC unit
address mismatch warning.

This can cause the LVDS1 display output to not function correctly because its
pixel combiner channel configuration is applied to channel 0 instead of
channel 1.

> +		status = "okay";
> +	};
> +};

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Sashiko AI review · https://sashiko.dev/#/patchset/20261013111737.998282-1-alexander.stein@ew.tq-group.com?part=4