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From: sashiko-bot@kernel.org
To: "Jason Yang" <jason98166@gmail.com>
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,
	neil.armstrong@linaro.org, olteanv@gmail.com
Subject: Re: [PATCH v5 3/8] phy: rockchip-samsung-dcphy: Move block-level setup to runtime resume
Date: Fri, 16 Oct 2026 09:09:46 +0000	[thread overview]
Message-ID: <sashiko-outbox-174059@kernel.org> (raw)
In-Reply-To: <20261016-dcphy-rx-v1-v5-3-e63b49eabe2d@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] phy: dcphy: PLL left enabled on lock failure, preventing recovery
--

commit 0436bfe5522a31ef65724b71dd2f683f01ebeaa1
Author: Jason Yang <jason98166@gmail.com>

phy: rockchip-samsung-dcphy: Move block-level setup to runtime resume

This commit moves the block-level APB reset and BIAS configuration
from the power-on path to runtime resume. This prevents resetting
the block underneath a PHY that is already running when multiple
consumers are present.

> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
> index 7382043e1f319..1471a1563d2a1 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

[ ... ]

> @@ -1362,10 +1361,6 @@ static int samsung_mipi_dcphy_power_on(struct phy *phy)
>  {
>  	struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
>  
> -	reset_control_assert(samsung->apb_rst);
> -	udelay(1);
> -	reset_control_deassert(samsung->apb_rst);
> -

[Severity: Medium]
If samsung_mipi_dcphy_pll_enable() fails to lock, it returns without clearing
the PLL_EN bit in PLL_CON0:

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c:samsung_mipi_dcphy_pll_enable() {
	regmap_update_bits(samsung->regmap, PLL_CON0, PLL_EN, PLL_EN);

	ret = regmap_read_poll_timeout(samsung->regmap, PLL_STAT0,
				       sts, (sts & PLL_LOCK), 1000, 20000);
	if (ret < 0)
		dev_err(samsung->dev, "DC-PHY pll failed to lock\n");

	return ret;
}

Because this patch removes the apb_rst sequence from the power_on path, the
stale PLL_EN bit is no longer cleared by the hardware reset on subsequent
retries.

Does this leave the hardware in an active but failed state, potentially
causing undefined behavior or preventing the PLL from locking during the
next power_on attempt?

>  	switch (samsung->type) {
>  	case PHY_TYPE_DPHY:
>  		return samsung_mipi_dphy_power_on(samsung);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261016-dcphy-rx-v1-v5-0-e63b49eabe2d@gmail.com?part=3

  reply	other threads:[~2026-10-16  9:09 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-16  8:56 [PATCH v5 0/8] phy: rockchip-samsung-dcphy: Add the MIPI D-PHY receiver Jason Yang
2026-10-16  8:56 ` [PATCH v5 1/8] dt-bindings: phy: Add PHY_DIRECTION_TX/RX definitions Jason Yang
2026-10-16  8:56 ` [PATCH v5 2/8] dt-bindings: phy: rockchip,rk3588-mipi-dcphy: Add a cell to select TX or RX Jason Yang
2026-10-16  8:56 ` [PATCH v5 3/8] phy: rockchip-samsung-dcphy: Move block-level setup to runtime resume Jason Yang
2026-10-16  9:09   ` sashiko-bot [this message]
2026-10-16  8:56 ` [PATCH v5 4/8] phy: rockchip-samsung-dcphy: Name the transmitter helpers and ops Jason Yang
2026-10-16  9:07   ` sashiko-bot
2026-10-16  8:56 ` [PATCH v5 5/8] phy: rockchip-samsung-dcphy: Add a second PHY for the receiver Jason Yang
2026-10-16  8:56 ` [PATCH v5 6/8] phy: rockchip-samsung-dcphy: Add MIPI D-PHY receiver support Jason Yang
2026-10-16  8:56 ` [PATCH v5 7/8] arm64: dts: rockchip: use two phy cells for the rk3588 mipi dcphys Jason Yang
2026-10-16  8:56 ` [PATCH v5 8/8] arm64: dts: rockchip: add mipi csi-2 receiver nodes for the dcphys on rk3588 Jason Yang

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