Re: [PATCH 08/10] ARM: dts: omap: dm816x: Correct speed for sysclk5

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] clk: ti: divider mask resolves to 0 preventing hardware update
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commit 010a738d1ba1df99c68c1c1fed6854e92365aa42
Author: Andrew Goodbody <andrew.goodbody@linaro.org>

ARM: dts: omap: dm816x: Correct speed for sysclk5

The commit forces sysclk5 to run at 813MHz by changing its divider
configuration from a maximum divider of 1 to a divider of 2.

> diff --git a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi
> index 76ebc6c3c3e5e..cb990773b0985 100644
> --- a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi
> +++ b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi
> @@ -144,7 +144,7 @@ sysclk5_ck: sysclk5_ck@310 {
>  		#clock-cells = <0>;
>  		compatible = "ti,divider-clock";
>  		clocks = <&sysclk4_ck>;
> -		ti,max-div = <1>;
> +		ti,dividers = <2>;

[Severity: High]
Does this actually change the clock rate in the hardware register?

By providing a single-element array ti,dividers = <2>;, the divider value 2
maps to the array index 0.

In drivers/clk/ti/divider.c:ti_clk_get_div_table():

	table[valid_div].div = val;
	table[valid_div].val = i;

Since there is only one element, the maximum valid index (and maximum register
value) is capped at 0.

When the mask is calculated in drivers/clk/ti/divider.c:_setup_mask():

	divider->mask = (1 << fls(mask)) - 1;

A maximum register value of 0 results in the mask evaluating to 0.

Consequently, any attempt to update the rate in ti_clk_divider_set_rate()
becomes a no-op:

	val &= ~(divider->mask << divider->shift);
	val |= value << divider->shift;

With a mask of 0, the physical hardware register is not modified, leaving the
clock running at 1.6GHz while the software incorrectly believes it has been
set to 813MHz.

>  		reg = <0x0310>;
>  	};

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Sashiko AI review · https://sashiko.dev/#/patchset/20261016-patch-ektor5-dm8168-dts-v1-0-b4ce30217028@linaro.org?part=8