Re: [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: samsung: exynos5515: CMU_PERI user muxes bypass CMU_TOP dout/gout clocks
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commit e9647c95dd003e1cc5e14508ac851bb3fa7a249e
Author: Aiden Isik <aidenisik@member.fsf.org>

arm64: dts: exynos: Add initial support for Exynos5515 SoC

This commit adds the initial device tree source for the Samsung Exynos 5515
SoC, including the Cortex-A55 CPUs, ChipID, generic timer, GIC, and the
CMU_TOP, CMU_PERI, and CMU_FSYS clock management units.

> diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> new file mode 100644
> index 0000000000000..ea70a45bfa50b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> @@ -0,0 +1,178 @@

[ ... ]

> +		sysreg_peri: syscon@10020000 {
> +			compatible = "samsung,exynos5515-peri-sysreg", "syscon";
> +			reg = <0x10020000 0x10000>;
> +			clocks = <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>;
> +		};
> +
> +		cmu_peri: clock-controller@10030000 {
> +			compatible = "samsung,exynos5515-cmu-peri";
> +			reg = <0x10030000 0x10000>;
> +			#clock-cells = <1>;
> +			clocks = <&oscclk>,
> +				 <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
> +				 <&cmu_top CLK_DOUT_CMU_PERI_IP>,
> +				 <&cmu_top CLK_DOUT_CMU_PERI_UART>;
> +			clock-names = "oscclk",
> +				      "bus",
> +				      "ip",
> +				      "uart";
> +			samsung,sysreg = <&sysreg_peri>;
> +		};

[Severity: Medium]
When cmu_peri is instantiated here with CLK_DOUT_CMU_PERI_BUS,
CLK_DOUT_CMU_PERI_IP, and CLK_DOUT_CMU_PERI_UART from cmu_top, will the
CMU_PERI user muxes in drivers/clk/samsung/clk-exynos5515.c bypass those
dividers and gates?

In drivers/clk/samsung/clk-exynos5515.c, CMU_TOP defines the clock chains
mout_cmu_peri_{bus,ip,uart} -> gout_cmu_peri_{bus,ip,uart} ->
dout_cmu_peri_{bus,ip,uart}, and CMU_FSYS connects its user muxes to
dout_cmu_fsys_*:

drivers/clk/samsung/clk-exynos5515.c:
    PNAME(mout_pll_fsys_bus_user_p)         = { "oscclk",
                                                "dout_cmu_fsys_bus" };

However, the CMU_PERI user mux parent arrays reference mout_cmu_peri_*
instead of dout_cmu_peri_*:

drivers/clk/samsung/clk-exynos5515.c:
    PNAME(mout_pll_peri_bus_user_p)         = { "oscclk",
                                                "mout_cmu_peri_bus" };

    PNAME(mout_pll_peri_ip_user_p)          = { "oscclk",
                                                "mout_cmu_peri_ip" };
    ...
    PNAME(mout_pll_peri_uart_user_p)        = { "oscclk",
                                                "mout_cmu_peri_uart" };

Because exynos5515_cmu_peri_init() -> exynos_arm64_register_cmu() ->
samsung_cmu_register_one() -> samsung_clk_register_mux() resolves parents by
these global clock name strings rather than the DT clocks property,
instantiating cmu_peri causes mout_pll_peri_{bus,ip,uart}_user and all
downstream CMU_PERI clocks (such as CLK_GOUT_PERI_SYSREG_PCLK) to attach
directly to mout_cmu_peri_*, bypassing gout_cmu_peri_* and dout_cmu_peri_*.

Should mout_pll_peri_{bus,ip,uart}_user_p in
drivers/clk/samsung/clk-exynos5515.c use dout_cmu_peri_{bus,ip,uart} to match
the clocks passed in the cmu_peri DT node?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-for-next-lucky7-v3-0-81e02272ce69@member.fsf.org?part=4