* [PATCH v3 1/5] dt-bindings: soc: samsung: exynos-sysreg: Add compatibles for Exynos5515
2026-10-30 20:33 [PATCH v3 0/5] arm64: dts: exynos: add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
@ 2026-10-30 20:33 ` Aiden Isik via B4 Relay
2026-10-30 20:33 ` [PATCH v3 2/5] dt-bindings: soc: samsung: exynos-pmu: Add Exynos5515 compatible Aiden Isik via B4 Relay
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-10-30 20:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
Add Exynos5515 compatibles for the following sysreg controllers:
- top
- peri
- fsys
Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
.../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index fcdb9ffd2644..9e698d065820 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -29,6 +29,9 @@ properties:
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
+ - samsung,exynos5515-fsys-sysreg
+ - samsung,exynos5515-peri-sysreg
+ - samsung,exynos5515-top-sysreg
- samsung,exynos7870-cam0-sysreg
- samsung,exynos7870-disp-sysreg
- samsung,exynos8895-fsys0-sysreg
@@ -100,6 +103,8 @@ allOf:
- google,gs101-misc-sysreg
- google,gs101-peric0-sysreg
- google,gs101-peric1-sysreg
+ - samsung,exynos5515-fsys-sysreg
+ - samsung,exynos5515-peri-sysreg
- samsung,exynos850-cmgp-sysreg
- samsung,exynos850-peri-sysreg
- samsung,exynos850-sysreg
--
2.54.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 2/5] dt-bindings: soc: samsung: exynos-pmu: Add Exynos5515 compatible
2026-10-30 20:33 [PATCH v3 0/5] arm64: dts: exynos: add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
2026-10-30 20:33 ` [PATCH v3 1/5] dt-bindings: soc: samsung: exynos-sysreg: Add compatibles for Exynos5515 Aiden Isik via B4 Relay
@ 2026-10-30 20:33 ` Aiden Isik via B4 Relay
2026-10-30 20:33 ` [PATCH v3 3/5] dt-bindings: arm: samsung: Add lucky7 board binding Aiden Isik via B4 Relay
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-10-30 20:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
Add exynos5515-pmu compatible to the device tree bindings documentation.
Use the samsung,exynos7-pmu compatible, as it works the same for Exynos7
and Exynos5515.
Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
index 5bd39876e3b3..1a0d9de79696 100644
--- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml
@@ -33,6 +33,7 @@ properties:
- enum:
- axis,artpec9-pmu
- samsung,exynos2200-pmu
+ - samsung,exynos5515-pmu
- samsung,exynos7870-pmu
- samsung,exynos7885-pmu
- samsung,exynos8890-pmu
--
2.54.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 3/5] dt-bindings: arm: samsung: Add lucky7 board binding
2026-10-30 20:33 [PATCH v3 0/5] arm64: dts: exynos: add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
2026-10-30 20:33 ` [PATCH v3 1/5] dt-bindings: soc: samsung: exynos-sysreg: Add compatibles for Exynos5515 Aiden Isik via B4 Relay
2026-10-30 20:33 ` [PATCH v3 2/5] dt-bindings: soc: samsung: exynos-pmu: Add Exynos5515 compatible Aiden Isik via B4 Relay
@ 2026-10-30 20:33 ` Aiden Isik via B4 Relay
2026-10-30 20:33 ` [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC Aiden Isik via B4 Relay
2026-10-30 20:34 ` [PATCH v3 5/5] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
4 siblings, 0 replies; 8+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-10-30 20:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
Add device tree binding for the Samsung Galaxy Watch FE (SM-R861/SM-R866)
board, based on the Exynos5515 SoC.
Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index db19a686f490..c80fac4fad7a 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -157,6 +157,12 @@ properties:
- const: samsung,exynos5420
- const: samsung,exynos5
+ - description: Exynos5515 based boards
+ items:
+ - enum:
+ - samsung,lucky7 # Samsung Galaxy Watch FE (SM-R861/SM-R866)
+ - const: samsung,exynos5515
+
- description: Google Peach Pit Boards (Rev 6+)
items:
- const: google,pit-rev16
--
2.54.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC
2026-10-30 20:33 [PATCH v3 0/5] arm64: dts: exynos: add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
` (2 preceding siblings ...)
2026-10-30 20:33 ` [PATCH v3 3/5] dt-bindings: arm: samsung: Add lucky7 board binding Aiden Isik via B4 Relay
@ 2026-10-30 20:33 ` Aiden Isik via B4 Relay
2026-10-30 20:49 ` sashiko-bot
2026-10-30 20:34 ` [PATCH v3 5/5] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
4 siblings, 1 reply; 8+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-10-30 20:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
The Exynos5515 is an ARMv8 wearable SoC, used in the following devices:
- Samsung Galaxy Watch 4 (SM-R860/SM-R865/SM-R870/SM-R875)
- Samsung Galaxy Watch 4 Classic (SM-R880/SM-R885/SM-R890/SM-R895)
- Samsung Galaxy Watch FE (SM-R861/SM-R866)
- Samsung Galaxy Watch 5 (SM-R900/SM-R905/SM-R910/SM-R915)
- Samsung Galaxy Watch 5 Pro (SM-R920/SM-R925)
- Samsung Galaxy Watch 6 (SM-R930/SM-R935/SM-R940/SM-R945)
- Samsung Galaxy Watch 6 Classic (SM-R950/SM-R955/SM-R960/SM-R965)
Add the following support for this SoC:
- Both Cortex-A55 cores
- ChipID
- Generic timer
- CMU_TOP, CMU_PERI, and CMU_FSYS clock management units
The devices using this SoC suffer from the same issue as many other
Samsung devices, where the stock bootloader does not configure CNTFRQ_EL0.
To mitigate this, the correct frequency is hardcoded in the timer node.
The VGIC maintenance interrupt on this SoC is also unavailable.
Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
arch/arm64/boot/dts/exynos/exynos5515.dtsi | 178 +++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
new file mode 100644
index 000000000000..ea70a45bfa50
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Exynos 5515 SoC device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ */
+
+#include <dt-bindings/clock/samsung,exynos5515-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos5515";
+ #address-cells = <2>;
+ interrupt-parent = <&gic>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ };
+
+ oscclk: osc-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos5515-chipid",
+ "samsung,exynos850-chipid";
+ reg = <0x10000000 0x100>;
+ };
+
+ sysreg_peri: syscon@10020000 {
+ compatible = "samsung,exynos5515-peri-sysreg", "syscon";
+ reg = <0x10020000 0x10000>;
+ clocks = <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>;
+ };
+
+ cmu_peri: clock-controller@10030000 {
+ compatible = "samsung,exynos5515-cmu-peri";
+ reg = <0x10030000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERI_IP>,
+ <&cmu_top CLK_DOUT_CMU_PERI_UART>;
+ clock-names = "oscclk",
+ "bus",
+ "ip",
+ "uart";
+ samsung,sysreg = <&sysreg_peri>;
+ };
+
+ cmu_fsys: clock-controller@10400000 {
+ compatible = "samsung,exynos5515-cmu-fsys";
+ reg = <0x10400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS_USB20DRD>;
+ clock-names = "oscclk",
+ "bus",
+ "mmc_card",
+ "mmc_embd",
+ "usb20drd";
+ samsung,sysreg = <&sysreg_fsys>;
+ };
+
+ sysreg_fsys: syscon@10420000 {
+ compatible = "samsung,exynos5515-fsys-sysreg", "syscon";
+ reg = <0x10420000 0x10000>;
+ clocks = <&cmu_fsys CLK_GOUT_FSYS_SYSREG_PCLK>;
+ };
+
+ pmu_system_controller: system-controller@12860000 {
+ compatible = "samsung,exynos5515-pmu",
+ "samsung,exynos7-pmu",
+ "syscon";
+ reg = <0x12860000 0x10000>;
+ };
+
+ cmu_top: clock-controller@15410000 {
+ compatible = "samsung,exynos5515-cmu-top";
+ reg = <0x15410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ samsung,sysreg = <&sysreg_top>;
+ };
+
+ sysreg_top: syscon@15430000 {
+ compatible = "samsung,exynos5515-top-sysreg", "syscon";
+ reg = <0x15430000 0x10000>;
+ };
+
+ gic: interrupt-controller@15601000 {
+ compatible = "arm,gic-400";
+ reg = <0x15601000 0x1000>,
+ <0x15602000 0x2000>,
+ <0x15604000 0x2000>,
+ <0x15606000 0x2000>;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ /* VGIC maintenance interrupt is not available */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /*
+ * Non-updatable, broken stock Samsung bootloader does not
+ * configure CNTFRQ_EL0
+ */
+ clock-frequency = <26000000>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+#include "arm/samsung/exynos-syscon-restart.dtsi"
--
2.54.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC
2026-10-30 20:33 ` [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC Aiden Isik via B4 Relay
@ 2026-10-30 20:49 ` sashiko-bot
2026-10-30 21:03 ` Aiden Isik
0 siblings, 1 reply; 8+ messages in thread
From: sashiko-bot @ 2026-10-30 20:49 UTC (permalink / raw)
To: Aiden Isik; +Cc: devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: samsung: exynos5515: CMU_PERI user muxes bypass CMU_TOP dout/gout clocks
--
commit e9647c95dd003e1cc5e14508ac851bb3fa7a249e
Author: Aiden Isik <aidenisik@member.fsf.org>
arm64: dts: exynos: Add initial support for Exynos5515 SoC
This commit adds the initial device tree source for the Samsung Exynos 5515
SoC, including the Cortex-A55 CPUs, ChipID, generic timer, GIC, and the
CMU_TOP, CMU_PERI, and CMU_FSYS clock management units.
> diff --git a/arch/arm64/boot/dts/exynos/exynos5515.dtsi b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> new file mode 100644
> index 0000000000000..ea70a45bfa50b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5515.dtsi
> @@ -0,0 +1,178 @@
[ ... ]
> + sysreg_peri: syscon@10020000 {
> + compatible = "samsung,exynos5515-peri-sysreg", "syscon";
> + reg = <0x10020000 0x10000>;
> + clocks = <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>;
> + };
> +
> + cmu_peri: clock-controller@10030000 {
> + compatible = "samsung,exynos5515-cmu-peri";
> + reg = <0x10030000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_CMU_PERI_BUS>,
> + <&cmu_top CLK_DOUT_CMU_PERI_IP>,
> + <&cmu_top CLK_DOUT_CMU_PERI_UART>;
> + clock-names = "oscclk",
> + "bus",
> + "ip",
> + "uart";
> + samsung,sysreg = <&sysreg_peri>;
> + };
[Severity: Medium]
When cmu_peri is instantiated here with CLK_DOUT_CMU_PERI_BUS,
CLK_DOUT_CMU_PERI_IP, and CLK_DOUT_CMU_PERI_UART from cmu_top, will the
CMU_PERI user muxes in drivers/clk/samsung/clk-exynos5515.c bypass those
dividers and gates?
In drivers/clk/samsung/clk-exynos5515.c, CMU_TOP defines the clock chains
mout_cmu_peri_{bus,ip,uart} -> gout_cmu_peri_{bus,ip,uart} ->
dout_cmu_peri_{bus,ip,uart}, and CMU_FSYS connects its user muxes to
dout_cmu_fsys_*:
drivers/clk/samsung/clk-exynos5515.c:
PNAME(mout_pll_fsys_bus_user_p) = { "oscclk",
"dout_cmu_fsys_bus" };
However, the CMU_PERI user mux parent arrays reference mout_cmu_peri_*
instead of dout_cmu_peri_*:
drivers/clk/samsung/clk-exynos5515.c:
PNAME(mout_pll_peri_bus_user_p) = { "oscclk",
"mout_cmu_peri_bus" };
PNAME(mout_pll_peri_ip_user_p) = { "oscclk",
"mout_cmu_peri_ip" };
...
PNAME(mout_pll_peri_uart_user_p) = { "oscclk",
"mout_cmu_peri_uart" };
Because exynos5515_cmu_peri_init() -> exynos_arm64_register_cmu() ->
samsung_cmu_register_one() -> samsung_clk_register_mux() resolves parents by
these global clock name strings rather than the DT clocks property,
instantiating cmu_peri causes mout_pll_peri_{bus,ip,uart}_user and all
downstream CMU_PERI clocks (such as CLK_GOUT_PERI_SYSREG_PCLK) to attach
directly to mout_cmu_peri_*, bypassing gout_cmu_peri_* and dout_cmu_peri_*.
Should mout_pll_peri_{bus,ip,uart}_user_p in
drivers/clk/samsung/clk-exynos5515.c use dout_cmu_peri_{bus,ip,uart} to match
the clocks passed in the cmu_peri DT node?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-for-next-lucky7-v3-0-81e02272ce69@member.fsf.org?part=4
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC
2026-10-30 20:49 ` sashiko-bot
@ 2026-10-30 21:03 ` Aiden Isik
0 siblings, 0 replies; 8+ messages in thread
From: Aiden Isik @ 2026-10-30 21:03 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Aiden Isik, devicetree, robh, conor+dt
> On Friday, 10/30/26 at 20:49 sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] clk: samsung: exynos5515: CMU_PERI user muxes bypass CMU_TOP dout/gout clocks
This is how those clocks are wired. I'm also not sure why the bot is suggesting
clock driver changes on a device tree patchset.
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 5/5] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
2026-10-30 20:33 [PATCH v3 0/5] arm64: dts: exynos: add initial support for Samsung Galaxy Watch FE Aiden Isik via B4 Relay
` (3 preceding siblings ...)
2026-10-30 20:33 ` [PATCH v3 4/5] arm64: dts: exynos: Add initial support for Exynos5515 SoC Aiden Isik via B4 Relay
@ 2026-10-30 20:34 ` Aiden Isik via B4 Relay
4 siblings, 0 replies; 8+ messages in thread
From: Aiden Isik via B4 Relay @ 2026-10-30 20:34 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Peter Griffin,
Alim Akhtar
Cc: Krzysztof Kozlowski, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel, Aiden Isik
From: Aiden Isik <aidenisik@member.fsf.org>
The Samsung Galaxy Watch FE (SM-R861/SM-R866), codenamed lucky7, is a
smartwatch developed by Samsung and released in 2024. It has 1.5GiB RAM,
16GiB of eMMC storage, an Exynos5515 (W920) SoC, and a 396x396 display.
Support for the following is added by this device tree:
- Bootloader framebuffer
- Memory
Signed-off-by: Aiden Isik <aidenisik@member.fsf.org>
---
arch/arm64/boot/dts/exynos/Makefile | 1 +
arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts | 215 +++++++++++++++++++++++
2 files changed, 216 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index 7534b773d28f..3ff3c643fc5c 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos2200-g0s.dtb \
exynos5433-tm2.dtb \
exynos5433-tm2e.dtb \
+ exynos5515-lucky7.dtb \
exynos7-espresso.dtb \
exynos7870-a2corelte.dtb \
exynos7870-j5y17lte.dtb \
diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
new file mode 100644
index 000000000000..0193a5d99f5c
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Galaxy Watch FE (lucky7/SM-R861/SM-R866) device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ */
+
+/dts-v1/;
+#include "exynos5515.dtsi"
+
+/ {
+ compatible = "samsung,lucky7", "samsung,exynos5515";
+ chassis-type = "watch";
+ model = "Samsung Galaxy Watch FE (SM-R861/SM-R866)";
+
+ chosen {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ format = "a8r8g8b8";
+ height = <396>;
+ stride = <(396 * 4)>;
+ width = <396>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x3ea00000>,
+ <0x0 0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ /*
+ * Some of these misc-rmem regions belong to memory-mapped
+ * devices, and will be assigned to drivers as support
+ * is added.
+ *
+ * Other regions belong to the TrustZone firmware and should
+ * never be touched.
+ */
+ misc-rmem@87000000 {
+ reg = <0x0 0x87000000 0x200000>;
+ no-map;
+ };
+
+ misc-rmem@87fff000 {
+ reg = <0x0 0x87fff000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@8a000000 {
+ reg = <0x0 0x8a000000 0x31000>;
+ no-map;
+ };
+
+ misc-rmem@8d800000 {
+ reg = <0x0 0x8d800000 0x180000>;
+ no-map;
+ };
+
+ misc-rmem@8ffff000 {
+ reg = <0x0 0x8ffff000 0x33000>;
+ no-map;
+ };
+
+ misc-rmem@90100000 {
+ reg = <0x0 0x90100000 0x200000>;
+ no-map;
+ };
+
+ misc-rmem@98a00000 {
+ reg = <0x0 0x98a00000 0x600000>;
+ no-map;
+ };
+
+ misc-rmem@9a000000 {
+ reg = <0x0 0x9a000000 0xc00000>;
+ no-map;
+ };
+
+ misc-rmem@9b000000 {
+ reg = <0x0 0x9b000000 0x400000>;
+ no-map;
+ };
+
+ misc-rmem@9bd00000 {
+ reg = <0x0 0x9bd00000 0x208000>;
+ no-map;
+ };
+
+ misc-rmem@9c000000 {
+ reg = <0x0 0x9c000000 0x20000>;
+ no-map;
+ };
+
+ framebuffer@9e0cf000 {
+ /*
+ * Reserve up to the end of the final page of the
+ * framebuffer region, to prevent memory aliasing.
+ *
+ * size: align((396 * 396 * 4), 0x1000)
+ */
+ reg = <0x0 0x9e0cf000 0x9a000>;
+ no-map;
+ };
+
+ misc-rmem@a0000000 {
+ reg = <0x0 0xa0000000 0x10000>;
+ no-map;
+ };
+
+ misc-rmem@a0010000 {
+ reg = <0x0 0xa0010000 0x400000>;
+ no-map;
+ };
+
+ misc-rmem@a0510000 {
+ reg = <0x0 0xa0510000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@a0900000 {
+ reg = <0x0 0xa0900000 0x2000>;
+ no-map;
+ };
+
+ misc-rmem@a0902000 {
+ reg = <0x0 0xa0902000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@a0910000 {
+ reg = <0x0 0xa0910000 0x3c000>;
+ no-map;
+ };
+
+ misc-rmem@b0000000 {
+ reg = <0x0 0xb0000000 0x200000>;
+ no-map;
+ };
+
+ misc-rmem@b1000000 {
+ reg = <0x0 0xb1000000 0x200000>;
+ no-map;
+ };
+
+ misc-rmem@bbfff000 {
+ reg = <0x0 0xbbfff000 0x1000000>;
+ no-map;
+ };
+
+ misc-rmem@bcfff000 {
+ reg = <0x0 0xbcfff000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@bd430000 {
+ reg = <0x0 0xbd430000 0x1250000>;
+ no-map;
+ };
+
+ misc-rmem@d0000000 {
+ reg = <0x0 0xd0000000 0x5d00000>;
+ no-map;
+ };
+
+ misc-rmem@dc444000 {
+ reg = <0x0 0xdc444000 0x2bbc000>;
+ no-map;
+ };
+
+ misc-rmem@df005000 {
+ reg = <0x0 0xdf005000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@df008000 {
+ reg = <0x0 0xdf008000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@df009000 {
+ reg = <0x0 0xdf009000 0x12000>;
+ no-map;
+ };
+
+ misc-rmem@df01b000 {
+ reg = <0x0 0xdf01b000 0x21000>;
+ no-map;
+ };
+
+ misc-rmem@df03c000 {
+ reg = <0x0 0xdf03c000 0x1000>;
+ no-map;
+ };
+
+ misc-rmem@df03d000 {
+ reg = <0x0 0xdf03d000 0xfc3000>;
+ no-map;
+ };
+ };
+};
+
+&oscclk {
+ clock-frequency = <26000000>;
+};
--
2.54.0
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