Re: [PATCH v1 RESEND 3/8] dt-bindings: pinctrl: Add starfive,jhb100-adc1-pinctrl

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: pinctrl: starfive,jhb100-adc1: reset order mismatch
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commit 4c932bf5e112630c79796db81f0b0cecf418f57b
Author: Changhuang Liang <changhuang.liang@starfivetech.com>

dt-bindings: pinctrl: Add starfive,jhb100-adc1-pinctrl

This commit adds the Device Tree binding schema for the StarFive JHB100
SoC ADC-1 pin controller.

> diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml
> new file mode 100644
> index 0000000000000..6f1486b4a8bdf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml

[ ... ]

> +  resets:
> +    items:
> +      - description: ADC1 IOMUX
> +      - description: ADC1 core

[ ... ]

> +examples:
> +  - |
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        pinctrl_adc1: pinctrl@11bc2c00 {
> +            compatible = "starfive,jhb100-adc1-pinctrl";
> +            reg = <0x0 0x11bc2c00 0x0 0x400>;
> +            clocks = <&per2crg 68>;
> +            resets = <&per2crg 12>,
> +                     <&per2crg 13>;

[Severity: Low]
In Documentation/devicetree/bindings/pinctrl/starfive,jhb100-adc1-pinctrl.yaml,
properties.resets defines the first entry as ADC1 IOMUX and the second entry
as ADC1 core, whereas the example lists <&per2crg 12> followed by
<&per2crg 13>.

In include/dt-bindings/reset/starfive,jhb100-crg.h, those reset indices are
defined in the opposite order:

    #define JHB100_PER2RST_ADC1_PRESETN			12
    #define JHB100_PER2RST_ADC1_IOMUX_PRESETN		13

Are the reset descriptions in properties.resets.items or the reset indices in
the example reversed?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261103102236.96872-1-changhuang.liang@starfivetech.com?part=3