From: sashiko-bot@kernel.org
To: "Demeter Barna" <me@fromdisposition.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-sound@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH 6/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS
Date: Wed, 04 Nov 2026 18:20:48 +0000 [thread overview]
Message-ID: <sashiko-outbox-197830@kernel.org> (raw)
In-Reply-To: <20261104-b4-sm8350-sound-v1-6-4c872df294fa@fromdisposition.org>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: sm8350: wrong PDC wakeup interrupt on swr2 node
--
commit e0bc0fd5876d3b09082c8770bf88a52e98e61a79
Author: Demeter Barna <me@fromdisposition.org>
arm64: dts: qcom: sm8350: Add SoundWire and LPASS
This commit adds the LPASS RX, TX, and VA macro nodes, the RX and TX
SoundWire controller nodes along with the LPASS audio clock controller,
and the LPI pin configuration states for SoundWire and DMICs on SM8350.
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 55b32050ce9c8..85476a04ea3fd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
[ ... ]
> @@ -2022,6 +2023,133 @@ compute-cb@5 {
[ ... ]
> + swr2: soundwire@3230000 {
> + compatible = "qcom,soundwire-v1.6.0";
> + reg = <0 0x03230000 0 0x2000>;
> + interrupts-extended = <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "core", "wakeup";
[Severity: Medium]
Should the wakeup interrupt on swr2 use PDC pin 70 instead of 130 on
SM8350?
When swr2 enters runtime suspend via swrm_runtime_suspend() in
drivers/soundwire/qcom.c, it stops the bus clock and enables
ctrl->wake_irq so that a peripheral pulling TX data lane 0
(WCD_SWR_TX_DATA0, LPI gpio1 / TLMM gpio169 on SM8350) high can wake the
controller.
In drivers/pinctrl/qcom/pinctrl-sm8350.c, sm8350_pdc_map routes TLMM
gpio169 to PDC pin 70 (which pdc maps to GIC_SPI 520 via
qcom,pdc-ranges), whereas PDC pin 130 is the SC7280 mapping and is not
mapped to any GPIO on SM8350:
drivers/pinctrl/qcom/pinctrl-sm8350.c:sm8350_pdc_map[] = {
...
{ 169, 70 }, { 172, 132 }, { 174, 87 }, { 175, 88 }, { 177, 89 },
...
};
With <&pdc 130 IRQ_TYPE_LEVEL_HIGH>, peripheral wakeup events on the TX
SoundWire bus will not fire during runtime suspend.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261104-b4-sm8350-sound-v1-0-4c872df294fa@fromdisposition.org?part=6
next prev parent reply other threads:[~2026-11-04 18:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 18:07 [PATCH 0/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS Demeter Barna via B4 Relay
2026-11-04 18:07 ` [PATCH 1/7] dt-bindings: clock: qcom,sc8280xp-lpasscc: Add SM8350 LPASS audio CSR Demeter Barna via B4 Relay
2026-11-04 18:22 ` sashiko-bot
2026-11-04 18:07 ` [PATCH 2/7] clk: qcom: lpassaudiocc-sc7280: Add SM8350 audio CSR resets Demeter Barna via B4 Relay
2026-11-04 18:07 ` [PATCH 3/7] ASoC: dt-bindings: qcom,lpass-rx-macro: Add SM8350 LPASS RX Demeter Barna via B4 Relay
2026-11-04 18:07 ` [PATCH 4/7] ASoC: dt-bindings: qcom,lpass-tx-macro: Add SM8350 LPASS TX Demeter Barna via B4 Relay
2026-11-04 18:07 ` [PATCH 5/7] ASoC: dt-bindings: qcom,lpass-va-macro: Add SM8350 LPASS VA Demeter Barna via B4 Relay
2026-11-04 18:07 ` [PATCH 6/7] arm64: dts: qcom: sm8350: Add SoundWire and LPASS Demeter Barna via B4 Relay
2026-11-04 18:20 ` sashiko-bot [this message]
2026-11-04 18:07 ` [PATCH 7/7] ASoC: dt-bindings: qcom,sm8250: Add SM8350 sound card Demeter Barna via B4 Relay
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