Re: [PATCH] arm64: dts: qcom: lemans: Enable the Inline Crypto Engine for SDHC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] arm64: dts: qcom: lemans: sdhc missing cqhci reg and
  supports-cqe for ICE
--

commit 62d5171c9cf52cc6dbe10886df2218e5f14f803c
Author: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>

arm64: dts: qcom: lemans: Enable the Inline Crypto Engine for SDHC

This commit adds the sdhc_ice node to lemans.dtsi and references it from
the sdhc node via qcom,ice.

> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa55184..dfd41b613523f 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -4327,6 +4327,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  			qcom,dll-config = <0x0007642c>;
>  			qcom,ddr-config = <0x80040868>;
>  
> +			qcom,ice = <&sdhc_ice>;

[Severity: High]
Does the sdhc node also need the cqhci register range, reg-names = "hc",
"cqhci", and supports-cqe for sdhc_ice to be used?

sdhci_msm_probe() only calls sdhci_msm_cqe_add_host() ->
sdhci_msm_ice_init() when supports-cqe is present, and
sdhci_msm_cqe_add_host() first calls cqhci_pltfm_init(), which requires a
"cqhci" memory resource:

drivers/mmc/host/sdhci-msm.c:sdhci_msm_probe() {
	...
	if (of_property_read_bool(node, "supports-cqe"))
		ret = sdhci_msm_cqe_add_host(host, pdev);
	else
		ret = sdhci_add_host(host);
	...
}

Because the sdhc node only defines reg = <0x0 0x087c4000 0x0 0x1000>
without supports-cqe or the cqhci region at 0x087c5000,
sdhci_msm_ice_init() is never called: inline crypto remains disabled,
and GCC_SDCC1_ICE_CORE_CLK and GCC_SDCC1_AHB_CLK enabled by
qcom_ice_probe() are never gated during runtime suspend.  Adding
supports-cqe on a board DT without the cqhci reg entry also causes
cqhci_pltfm_init() to fail sdhci_msm_probe() with -EINVAL.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-enable-ice-sdcc-for-lemans-v1-1-1f25debeea49@oss.qualcomm.com?part=1