[PATCH] arm64: dts: qcom: lemans: Enable the Inline Crypto Engine for SDHC

[PATCH] arm64: dts: qcom: lemans: Enable the Inline Crypto Engine for SDHC

[Abhinaba Rakshit]

Add an ICE node to LeMans SoC description and enable it by adding a
phandle to the SDHC node.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
This patchseries enables Inline Crypto Engine for LeMans platform
for SDHC storage.

Testing:
* dtbs_check.
* Validated on LeMans-evk with custom Mezzanine board for SDHC support.

Dependencies
============

[1] Enable ICE clock scaling
    https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-0-09271f583dc6@oss.qualcomm.com/
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 1fdb72fa5518446ba2ea582e8362e86bba75c379..dfd41b613523fb85eb122488e0562447f7228e61 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -4327,6 +4327,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			qcom,dll-config = <0x0007642c>;
 			qcom,ddr-config = <0x80040868>;
 
+			qcom,ice = <&sdhc_ice>;
+
 			status = "disabled";
 
 			sdhc_opp_table: opp-table {
@@ -4348,6 +4350,33 @@ opp-384000000 {
 			};
 		};
 
+		sdhc_ice: crypto@87c8000 {
+			compatible = "qcom,sa8775p-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x087c8000 0x0 0x18000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&rpmhpd SA8775P_CX>;
+
+			operating-points-v2 = <&ice_mmc_opp_table>;
+
+			ice_mmc_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-150000000 {
+					opp-hz = /bits/ 64 <150000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+
+				opp-300000000 {
+					opp-hz = /bits/ 64 <300000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
 		usb_0_hsphy: phy@88e4000 {
 			compatible = "qcom,sa8775p-usb-hs-phy",
 				     "qcom,usb-snps-hs-5nm-phy";

---
base-commit: ddfe51b0a0f5dc9e415cc2c8ad8db17532dd426b
change-id: 20261109-enable-ice-sdcc-for-lemans-9ee375987009

Best regards,
-- 
Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: lemans: Enable the Inline Crypto Engine for SDHC

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [High] arm64: dts: qcom: lemans: sdhc missing cqhci reg and
  supports-cqe for ICE
--

commit 62d5171c9cf52cc6dbe10886df2218e5f14f803c
Author: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>

arm64: dts: qcom: lemans: Enable the Inline Crypto Engine for SDHC

This commit adds the sdhc_ice node to lemans.dtsi and references it from
the sdhc node via qcom,ice.

> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa55184..dfd41b613523f 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -4327,6 +4327,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  			qcom,dll-config = <0x0007642c>;
>  			qcom,ddr-config = <0x80040868>;
>  
> +			qcom,ice = <&sdhc_ice>;

[Severity: High]
Does the sdhc node also need the cqhci register range, reg-names = "hc",
"cqhci", and supports-cqe for sdhc_ice to be used?

sdhci_msm_probe() only calls sdhci_msm_cqe_add_host() ->
sdhci_msm_ice_init() when supports-cqe is present, and
sdhci_msm_cqe_add_host() first calls cqhci_pltfm_init(), which requires a
"cqhci" memory resource:

drivers/mmc/host/sdhci-msm.c:sdhci_msm_probe() {
	...
	if (of_property_read_bool(node, "supports-cqe"))
		ret = sdhci_msm_cqe_add_host(host, pdev);
	else
		ret = sdhci_add_host(host);
	...
}

Because the sdhc node only defines reg = <0x0 0x087c4000 0x0 0x1000>
without supports-cqe or the cqhci region at 0x087c5000,
sdhci_msm_ice_init() is never called: inline crypto remains disabled,
and GCC_SDCC1_ICE_CORE_CLK and GCC_SDCC1_AHB_CLK enabled by
qcom_ice_probe() are never gated during runtime suspend.  Adding
supports-cqe on a board DT without the cqhci reg entry also causes
cqhci_pltfm_init() to fail sdhci_msm_probe() with -EINVAL.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-enable-ice-sdcc-for-lemans-v1-1-1f25debeea49@oss.qualcomm.com?part=1