Re: [PATCH v2 06/10] arm64: dts: qcom: lemans: Add support for TSCSS node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: lemans: missing CX power-domain and OPP in
  ptp@1c80000
--

commit 75dd9885f6f6ae470214655cb90edbd903d34847
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>

arm64: dts: qcom: lemans: Add support for TSCSS node

This commit adds the Timestamp Counter Subsystem node to the Qualcomm
Lemans SoC devicetree.

> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 1fdb72fa55184..4c76c820cacb1 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -3022,6 +3022,18 @@ pcie1_phy: phy@1c14000 {
>  			status = "disabled";
>  		};
>  
> +		ptp@1c80000 {
> +			compatible = "qcom,sa8775p-tscss";
> +			reg = <0x0 0x01c80000 0x0 0x2000>;
> +			reg-names = "tsc";
> +			clocks = <&gcc GCC_TSCSS_AHB_CLK>,
> +				 <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>,
> +				 <&gcc GCC_TSCSS_ETU_CLK>;
> +			clock-names = "ahb", "cntr", "etu";
> +			assigned-clocks = <&gcc GCC_TSCSS_GLOBAL_CNTR_CLK>;
> +			assigned-clock-rates = <15625000>;
> +		};

[Severity: Medium]
As reported by Konrad Dybcio on v1 [1], does ptp@1c80000 need
power-domains = <&rpmhpd SA8775P_CX> and
required-opps = <&rpmhpd_opp_svs_l1>?

Running the counter clock at 15.625 MHz requires the rpmhpd_opp_svs_l1
performance state, and rpmhpd_opp_table defines rpmhpd_opp_min_svs,
rpmhpd_opp_low_svs, and rpmhpd_opp_svs below it.  Once rpmhpd_sync_state()
completes, the CX power domain can drop to one of those lower corners when
other consumers vote lower levels or are idle, operating the counter clock
below its required voltage corner.

[1] https://lore.kernel.org/r/a93f11c5-d0cf-4acd-a959-53fecc996e5f@oss.qualcomm.com

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261108-tscss-v2-0-d5f575010427@oss.qualcomm.com?part=6