[PATCH] arm64: dts: qcom: mahua-crd: Enable DisplayPort

[PATCH] arm64: dts: qcom: mahua-crd: Enable DisplayPort

[Nabige Aala]

Mahua CRD uses the same DisplayPort configuration as Glymur CRD.
Enable the two DisplayPort controllers associated with the
Type-C ports and define the supported link frequencies for
their outputs.

Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
---
This patch enables the DisplayPort support in Mahua CRD.

Functional operation depends on following PHY PLL series:
https://lore.kernel.org/all/20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com
---
 arch/arm64/boot/dts/qcom/mahua-crd.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts
index 17e40f2a6259..2605c0e70c88 100644
--- a/arch/arm64/boot/dts/qcom/mahua-crd.dts
+++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts
@@ -20,6 +20,22 @@ / {
 	compatible = "qcom,mahua-crd", "qcom,mahua";
 };
 
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+};
+
 &pcie3b_phy {
 	vdda-phy-supply = <&vreg_l3c_e1_0p89>;
 	vdda-pll-supply = <&vreg_l2c_e1_1p14>;

---
base-commit: d6bcfc94eb4da6e089c5473970cd96727292fd97
change-id: 20261104-mahua-dp-df2541837127

Best regards,
--  
Nabige Aala <nabige.aala@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: mahua-crd: Enable DisplayPort

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: dts: qcom: mahua-crd: duplicate DisplayPort nodes instead
  of sharing
--

commit fbaa055483b5c2f8197fcdac2ccd42fd5ce8c9c7
Author: Nabige Aala <nabige.aala@oss.qualcomm.com>

arm64: dts: qcom: mahua-crd: Enable DisplayPort

This commit enables the mdss_dp0 and mdss_dp1 DisplayPort controllers and
defines the supported link frequencies on their output endpoints for the
Mahua CRD board.

> diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts
> index 17e40f2a6259f..2605c0e70c88e 100644
> --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts
> @@ -20,6 +20,22 @@ / {
>  	compatible = "qcom,mahua-crd", "qcom,mahua";
>  };
>  
> +&mdss_dp0 {
> +	status = "okay";
> +};
> +
> +&mdss_dp0_out {
> +	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
> +};
> +
> +&mdss_dp1 {
> +	status = "okay";
> +};
> +
> +&mdss_dp1_out {
> +	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
> +};

[Severity: Low]
Could these mdss_dp0, mdss_dp0_out, mdss_dp1, and mdss_dp1_out nodes be
moved from arch/arm64/boot/dts/qcom/glymur-crd.dts into the shared
arch/arm64/boot/dts/qcom/glymur-crd.dtsi instead of duplicating them in
mahua-crd.dts?

Both glymur-crd.dts and mahua-crd.dts include glymur-crd.dtsi (and no
other board file does), where the shared mdss, mdss_dp3, and Type-C QMP
PHY nodes were placed by 711e6f11640f ("arm64: dts: qcom: glymur-crd: Move
common board nodes to shared DTSI").

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261109-mahua-dp-v1-1-c1fdfb8eedb5@oss.qualcomm.com?part=1

Re: [PATCH] arm64: dts: qcom: mahua-crd: Enable DisplayPort

[Abel Vesa]

On 26-11-09 21:20:00, Nabige Aala wrote:
> Mahua CRD uses the same DisplayPort configuration as Glymur CRD.
> Enable the two DisplayPort controllers associated with the
> Type-C ports and define the supported link frequencies for
> their outputs.
> 
> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: mahua-crd: Enable DisplayPort

[Konrad Dybcio]

On 11/9/26 4:50 PM, Nabige Aala wrote:
> Mahua CRD uses the same DisplayPort configuration as Glymur CRD.
> Enable the two DisplayPort controllers associated with the
> Type-C ports and define the supported link frequencies for
> their outputs.
> 
> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
> ---
> This patch enables the DisplayPort support in Mahua CRD.
> 
> Functional operation depends on following PHY PLL series:
> https://lore.kernel.org/all/20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com
> ---

An alternative patch was part of the power grid commonization
series and has now been merged as

fee7cfb39608 ("arm64: dts: qcom: glymur-crd: Move DP0/DP1 to common dtsi")

Konrad