* [PATCH v2 1/2] dt-bindings: gpio: Add Siflower SF19A2890 GPIO controller
2026-11-09 20:09 [PATCH v2 0/2] gpio: Add the Siflower SF19A2890 GPIO controller Joseph Telaak via B4 Relay
@ 2026-11-09 20:09 ` Joseph Telaak via B4 Relay
2026-11-10 13:24 ` Krzysztof Kozlowski
2026-11-09 20:09 ` [PATCH v2 2/2] gpio: Add Siflower GPIO controller driver Joseph Telaak via B4 Relay
1 sibling, 1 reply; 5+ messages in thread
From: Joseph Telaak via B4 Relay @ 2026-11-09 20:09 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: Chuanhong Guo, Qingfang Deng, linux-mips, linux-gpio, devicetree,
linux-kernel, Joseph Telaak
From: Chuanhong Guo <gch981213@gmail.com>
Document the GPIO controller of the Siflower SF19A2890. Siflower's SF21
RISC-V SoCs have the same controller, and will get compatibles of their
own with their device trees.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[Joseph Telaak:
- take it from Chuanhong's siflower-7.1 branch
- list myself as the binding's maintainer
- use GPL-2.0-only instead of the deprecated GPL-2.0 SPDX
identifier
- indent the example by four spaces
- drop the ngpios property, which the compatible implies, take
exactly four interrupts, and order the properties as in required
- commit message and subject]
Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
.../bindings/gpio/siflower,sf19a2890-gpio.yaml | 76 ++++++++++++++++++++++
MAINTAINERS | 6 ++
2 files changed, 82 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/siflower,sf19a2890-gpio.yaml b/Documentation/devicetree/bindings/gpio/siflower,sf19a2890-gpio.yaml
new file mode 100644
index 000000000..830a049ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/siflower,sf19a2890-gpio.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/siflower,sf19a2890-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Siflower SF19A2890 GPIO controller
+
+maintainers:
+ - Joseph Telaak <joseph@telaak.dev>
+
+properties:
+ compatible:
+ const: siflower,sf19a2890-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: One interrupt per group of 16 GPIOs.
+ maxItems: 4
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+
+ gpio@19d00000 {
+ compatible = "siflower,sf19a2890-gpio";
+ reg = <0x19d00000 0x100000>;
+ interrupts = <GIC_SHARED 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 249 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpioclk 0>;
+ resets = <&gpiorst 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 49>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index b5a6dc379..4193b433c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25706,6 +25706,12 @@ N: sifive
K: fu[57]40
K: [^@]sifive
+SIFLOWER GPIO DRIVER
+M: Joseph Telaak <joseph@telaak.dev>
+L: linux-gpio@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/gpio/siflower,sf19a2890-gpio.yaml
+
SILEAD TOUCHSCREEN DRIVER
M: Hans de Goede <hansg@kernel.org>
L: linux-input@vger.kernel.org
--
Git-155)
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] gpio: Add Siflower GPIO controller driver
2026-11-09 20:09 [PATCH v2 0/2] gpio: Add the Siflower SF19A2890 GPIO controller Joseph Telaak via B4 Relay
2026-11-09 20:09 ` [PATCH v2 1/2] dt-bindings: gpio: Add " Joseph Telaak via B4 Relay
@ 2026-11-09 20:09 ` Joseph Telaak via B4 Relay
2026-11-09 20:21 ` sashiko-bot
1 sibling, 1 reply; 5+ messages in thread
From: Joseph Telaak via B4 Relay @ 2026-11-09 20:09 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel
Cc: Chuanhong Guo, Qingfang Deng, linux-mips, linux-gpio, devicetree,
linux-kernel, Qingfang Deng, Joseph Telaak
From: Qingfang Deng <qingfang.deng@siflower.com.cn>
Add a driver for the GPIO controller on Siflower SoCs.
This controller is found on all current Siflower MIPS and RISC-V
chips including SF19A2890, SF21A6826 and SF21H8898.
Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[Joseph Telaak:
- take it from Chuanhong's siflower-7.1 branch
- depend on MACH_SIFLOWER_MIPS instead of OF_GPIO, longer Kconfig help
- get the reset with devm_reset_control_get_exclusive_deasserted(),
so it is asserted again only after the GPIO chip is removed, not in
a .remove that ran first
- drop .owner and the unused drvdata, and get priv with
gpiochip_get_data()
- drop the irq_set_affinity callback, which reached the parent
through irq_to_desc(), not exported with SPARSE_IRQ
- call gpiochip_disable_irq() and gpiochip_enable_irq() from mask
and unmask, as an immutable irqchip must
- find the group by its parent IRQ instead of assuming consecutive
numbers
- return 0 or 1 from .get
- use readl() and writel() directly, without wrapper functions
- take the number of lines from the match data, not from an
ngpios property
- include linux/math64.h, drop the unused linux/pinctrl/consumer.h,
sort the includes, spell it "Siflower"
- subject]
Co-developed-by: Joseph Telaak <joseph@telaak.dev>
Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
MAINTAINERS | 1 +
drivers/gpio/Kconfig | 12 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-siflower.c | 310 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 324 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4193b433c..0a3f91844 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25711,6 +25711,7 @@ M: Joseph Telaak <joseph@telaak.dev>
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/gpio/siflower,sf19a2890-gpio.yaml
+F: drivers/gpio/gpio-siflower.c
SILEAD TOUCHSCREEN DRIVER
M: Hans de Goede <hansg@kernel.org>
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 55e428002..623c09832 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -721,6 +721,18 @@ config GPIO_SIFIVE
help
Say yes here to support the GPIO device on SiFive SoCs.
+config GPIO_SIFLOWER
+ tristate "Siflower GPIO support"
+ depends on MACH_SIFLOWER_MIPS || COMPILE_TEST
+ select GPIOLIB_IRQCHIP
+ help
+ GPIO controller driver for the Siflower SF19A2890. Each line can be
+ an input or an output and raise an interrupt on either edge or
+ level, and inputs can be debounced in hardware.
+
+ To compile this driver as a module, choose M here: the module will
+ be called gpio-siflower.
+
config GPIO_SIOX
tristate "SIOX GPIO support"
depends on SIOX
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 88f748846..bde618108 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -171,6 +171,7 @@ obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
obj-$(CONFIG_GPIO_SHARED_PROXY) += gpio-shared-proxy.o
obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o
+obj-$(CONFIG_GPIO_SIFLOWER) += gpio-siflower.o
obj-$(CONFIG_GPIO_SIM) += gpio-sim.o
obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o
obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o
diff --git a/drivers/gpio/gpio-siflower.c b/drivers/gpio/gpio-siflower.c
new file mode 100644
index 000000000..3fde9a287
--- /dev/null
+++ b/drivers/gpio/gpio-siflower.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * GPIO controller driver for Siflower MIPS and RISC-V SoCs including:
+ * Siflower SF19A2890
+ * Siflower SF21A6826
+ * Siflower SF21H8898
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/reset.h>
+
+#define GPIO_IR(n) (0x40 * (n) + 0x00)
+#define GPIO_OR(n) (0x40 * (n) + 0x04)
+#define GPIO_OEN(n) (0x40 * (n) + 0x08)
+#define GPIO_IMR(n) (0x40 * (n) + 0x0c)
+#define GPIO_GPIMR(n) (0x40 * (n) + 0x10)
+#define GPIO_PIR(n) (0x40 * (n) + 0x14)
+#define GPIO_ITR(n) (0x40 * (n) + 0x18)
+#define GPIO_IFR(n) (0x40 * (n) + 0x1c)
+#define GPIO_ICR(n) (0x40 * (n) + 0x20)
+#define GPIO_GPxIR(n) (0x4 * (n) + 0x4000)
+
+#define GPIOS_PER_GROUP 16
+
+struct sf_gpio_soc_data {
+ unsigned int ngpios;
+};
+
+struct sf_gpio_priv {
+ struct gpio_chip gc;
+ void __iomem *base;
+ struct clk *clk;
+ unsigned int irq[];
+};
+
+static int sf_gpio_get_value(struct gpio_chip *gc, unsigned int offset)
+{
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+
+ return !!readl(priv->base + GPIO_IR(offset));
+}
+
+static int sf_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+
+ writel(value, priv->base + GPIO_OR(offset));
+ return 0;
+}
+
+static int sf_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+
+ if (readl(priv->base + GPIO_OEN(offset)))
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int sf_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
+{
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+
+ writel(1, priv->base + GPIO_OEN(offset));
+ return 0;
+}
+
+static int sf_gpio_direction_output(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+
+ writel(value, priv->base + GPIO_OR(offset));
+ writel(0, priv->base + GPIO_OEN(offset));
+ return 0;
+}
+
+static int sf_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset,
+ u32 debounce)
+{
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+ unsigned long freq = clk_get_rate(priv->clk);
+ u64 mul;
+
+ /* (ICR + 1) * IFR = debounce_us * clkfreq_mhz / 4 */
+ mul = (u64)debounce * freq;
+ do_div(mul, 1000000 * 4);
+ if (mul > 0xff00)
+ return -EINVAL;
+
+ writel(0xff, priv->base + GPIO_ICR(offset));
+ writel(DIV_ROUND_UP(mul, 0x100), priv->base + GPIO_IFR(offset));
+
+ return 0;
+}
+
+static int sf_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
+ unsigned long config)
+{
+ switch (pinconf_to_config_param(config)) {
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ return sf_gpio_set_debounce(gc, offset,
+ pinconf_to_config_argument(config));
+ default:
+ return gpiochip_generic_config(gc, offset, config);
+ }
+}
+
+static void sf_gpio_irq_ack(struct irq_data *data)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+ unsigned long offset = irqd_to_hwirq(data);
+
+ writel(0, priv->base + GPIO_PIR(offset));
+}
+
+static void sf_gpio_irq_mask(struct irq_data *data)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+ unsigned long offset = irqd_to_hwirq(data);
+
+ writel(1, priv->base + GPIO_IMR(offset));
+ writel(1, priv->base + GPIO_GPIMR(offset));
+ gpiochip_disable_irq(gc, offset);
+}
+
+static void sf_gpio_irq_unmask(struct irq_data *data)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+ unsigned long offset = irqd_to_hwirq(data);
+
+ gpiochip_enable_irq(gc, offset);
+ writel(0, priv->base + GPIO_IMR(offset));
+ writel(0, priv->base + GPIO_GPIMR(offset));
+}
+
+static int sf_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+ unsigned long offset = irqd_to_hwirq(data);
+ u32 val;
+
+ switch (flow_type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val = 4;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ val = 2;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ val = 6;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ val = 1;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ writel(val, priv->base + GPIO_ITR(offset));
+
+ if (flow_type & IRQ_TYPE_LEVEL_MASK) {
+ irq_set_handler_locked(data, handle_level_irq);
+ return 0;
+ }
+
+ irq_set_handler_locked(data, handle_edge_irq);
+
+ return 0;
+}
+
+static const struct irq_chip sf_gpio_irqchip = {
+ .name = KBUILD_MODNAME,
+ .irq_ack = sf_gpio_irq_ack,
+ .irq_mask = sf_gpio_irq_mask,
+ .irq_unmask = sf_gpio_irq_unmask,
+ .irq_set_type = sf_gpio_irq_set_type,
+ .flags = IRQCHIP_IMMUTABLE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void sf_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *ic = irq_desc_get_chip(desc);
+ struct sf_gpio_priv *priv = gpiochip_get_data(gc);
+ unsigned int irq = irq_desc_get_irq(desc);
+ unsigned long pending;
+ unsigned int group, n;
+
+ for (group = 0; group < gc->irq.num_parents; group++)
+ if (priv->irq[group] == irq)
+ break;
+ if (WARN_ON_ONCE(group == gc->irq.num_parents))
+ return;
+
+ chained_irq_enter(ic, desc);
+
+ pending = readl(priv->base + GPIO_GPxIR(group));
+ for_each_set_bit(n, &pending, GPIOS_PER_GROUP) {
+ generic_handle_domain_irq(gc->irq.domain,
+ n + group * GPIOS_PER_GROUP);
+ }
+
+ chained_irq_exit(ic, desc);
+}
+
+static int sf_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct sf_gpio_soc_data *soc;
+ struct reset_control *rstc;
+ struct sf_gpio_priv *priv;
+ struct gpio_irq_chip *girq;
+ struct gpio_chip *gc;
+ u32 ngpios, ngroups;
+ int ret, i;
+
+ soc = device_get_match_data(dev);
+ if (!soc)
+ return -ENODEV;
+
+ ngpios = soc->ngpios;
+ ngroups = DIV_ROUND_UP(ngpios, GPIOS_PER_GROUP);
+ priv = devm_kzalloc(dev, struct_size(priv, irq, ngroups), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
+
+ for (i = 0; i < ngroups; i++) {
+ ret = platform_get_irq(pdev, i);
+ if (ret < 0)
+ return ret;
+
+ priv->irq[i] = ret;
+ }
+
+ gc = &priv->gc;
+ gc->label = KBUILD_MODNAME;
+ gc->parent = dev;
+ gc->owner = THIS_MODULE;
+ gc->request = gpiochip_generic_request;
+ gc->free = gpiochip_generic_free;
+ gc->get_direction = sf_gpio_get_direction;
+ gc->direction_input = sf_gpio_direction_input;
+ gc->direction_output = sf_gpio_direction_output;
+ gc->get = sf_gpio_get_value;
+ gc->set = sf_gpio_set_value;
+ gc->set_config = sf_gpio_set_config;
+ gc->base = -1;
+ gc->ngpio = ngpios;
+
+ girq = &gc->irq;
+ gpio_irq_chip_set_chip(girq, &sf_gpio_irqchip);
+ girq->num_parents = ngroups;
+ girq->parents = priv->irq;
+ girq->parent_handler = sf_gpio_irq_handler;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+
+ return devm_gpiochip_add_data(dev, gc, priv);
+}
+
+static const struct sf_gpio_soc_data sf19a2890_gpio_data = {
+ .ngpios = 49,
+};
+
+static const struct of_device_id sf_gpio_ids[] = {
+ { .compatible = "siflower,sf19a2890-gpio", .data = &sf19a2890_gpio_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sf_gpio_ids);
+
+static struct platform_driver sf_gpio_driver = {
+ .probe = sf_gpio_probe,
+ .driver = {
+ .name = "siflower_gpio",
+ .of_match_table = sf_gpio_ids,
+ },
+};
+module_platform_driver(sf_gpio_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Qingfang Deng <qingfang.deng@siflower.com.cn>");
+MODULE_DESCRIPTION("GPIO driver for Siflower SoCs");
--
Git-155)
^ permalink raw reply related [flat|nested] 5+ messages in thread