Re: [PATCH v3 2/8] ARM: dts: imx: Use minimum NAND ECC strength on BSH boards

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] ARM: dts: imx: unjustified incompatible NAND ECC layout
  change on BSH boards
--

commit 1e6153dffd8fb43d1ff6ef7ef9b632628cf01234
Author: Michael Trimarchi <michael@amarulasolutions.com>

ARM: dts: imx: Use minimum NAND ECC strength on BSH boards

This commit enables the fsl,use-minimum-ecc property on the GPMI NAND
controllers for the BSH SMM-M2 and SMM-S2 boards.

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
> index 2d9f495660c9a..aac211a9f9ebd 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts
> @@ -26,6 +26,7 @@ &gpmi {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_gpmi_nand>;
>  	nand-on-flash-bbt;
> +	fsl,use-minimum-ecc;
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
> index 11a1ba5bfdb7e..df11f81ac50c1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts
> @@ -21,6 +21,7 @@ memory@40000000 {
>  &gpmi {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_gpmi_nand>;
> +	fsl,use-minimum-ecc;
>  	status = "okay";
>  };

[Severity: Medium]
Does adding fsl,use-minimum-ecc to these existing boards break
compatibility with NAND flash already formatted using the mainline device
trees?

In common_nfc_set_geometry(), enabling fsl,use-minimum-ecc switches the
controller from legacy_set_geometry(), which maximizes ECC strength across
the OOB area, to set_geometry_by_ecc_info() using the chip's minimum ECC
requirements.  Because the GPMI BCH layout interleaves data and ECC parity
bits across the page and derives the bad-block marker offsets from the ECC
strength, this changes the physical on-flash layout and makes existing
NAND partitions, UBI volumes, and on-flash bad block tables unreadable
with -EBADMSG.

If this change is intentional (for example, to match the ECC geometry used
by the bootloader and flashing tools), could the commit message explain why
the incompatible layout change is needed and how existing devices are
affected?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111-add-bsh-smm-m2-v3-0-4abdf10e9a7f@cn.bosch.com?part=2