* [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210
@ 2026-11-12 4:36 Varadarajan Narayanan
2026-11-12 4:36 ` [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan
` (10 more replies)
0 siblings, 11 replies; 19+ messages in thread
From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Abel Vesa
Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan,
Konrad Dybcio
This set of patches enable mutliple peripherals like USB, PCIe etc.
Additionally, it enables CPUfreq and thermal tripping points.
Please refer to [1] for initial review comments on the PCIe related DT
changes.
1 - https://lore.kernel.org/linux-arm-msm/20260514-pci-ipq5210-v1-0-a09436200b35@oss.qualcomm.com/
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
---
Changes in v9:
- Rebase to next-20261110 and include merged changes from [1]
- Add qcom,ice = <&sdhc_ice>; to mmc@7804000 node
- Add qcom,ipq5210-inline-crypto-engine change to dependencies to avoid
dtb validation failure from sashiko
- Link to v8: https://lore.kernel.org/r/20261106-08-dts-v8-0-d91401955039@oss.qualcomm.com
1 - https://lore.kernel.org/all/20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com/
Changes in v8:
- Fix pcie0 & pcie1 nodes' ranges property
- s/wps/WPS/
- s/cpu-sleep-c3/cpu-sleep-0/
- Moved ICE out from sdhci to a separate node
- Keep pwm@1941010 enabled
- Combine i2c pin defines into one node
- Add opp tables fro spi and i2c
- Pick R-b
- Link to v7: https://lore.kernel.org/r/20261012-08-dts-v7-0-77bd3d68d850@oss.qualcomm.com
Changes in v7:
- In 'Add nodes for multiple peripherals' patch (it has R-B Konrad)
* Reduce critical temperature by about five degrees per recent
calibration updates
* Fix placement of 'efuse@a4000' node
- Move 'spi-{rx,tx}-bus-width = 4' to rdp504-common.dtsi instead of
rdp504-nand.dts
- Change 'reg' details in spi@1a80000 from 32 to 64 bit
- Add #address-cells = <1>; and #size-cells = <0>; to spi0 & spi1 nodes
- Fix incorrect placement of rng@4c3000 node
- Link to v6: https://lore.kernel.org/r/20261008-08-dts-v6-0-f9c4ec8664d8@oss.qualcomm.com
Changes in v6:
- Didn't touch the existing patch as it has R-b
- Add DT changes to enable more devices. Not sure if these can be squashed
into a single patch. Please let me know, will squash if that is
preferrable. Following were added
Random number generator
SPI node definitions
I2C definitions
PWM block
Download mode support
ICE support for sdhci
C3 CPU idle state
Support for WPS button
- New compatibles used are documented in
https://lore.kernel.org/linux-arm-msm/20261008-rng-v1-1-785580a8b48f@oss.qualcomm.com/
https://lore.kernel.org/linux-arm-msm/20261008-pwm-v1-1-0b8776398632@oss.qualcomm.com/
- Link to v5: https://lore.kernel.org/r/20260907-08-dts-v5-0-584e5ab50b40@oss.qualcomm.com
Changes in v5:
- Pick one R-b Konrad
- Do not remove ipq5210-rdp504.dtb from arch/arm64/boot/dts/qcom/Makefile
and add it in a subsequent patch. Instead, move the ipq5210-rdp504.dts
nodes to ipq5210-rdp504.dtb-common.dtsi and include common dtsi in rdp504
dts file and introduce rdp504-nand dts in the 3rd patch
- No code changes
- Link to v4: https://lore.kernel.org/r/20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com
Changes in v4:
- Fix following sashiko comments
- Add #include <dt-bindings/thermal/thermal.h> to dtsi file for
THERMAL_NO_LIMIT definition
- Change tsens interrupt from edge to level
- Remove ipq5210-rdp504.dtb from Makefile in the second patch to
avoid build break and add it back in the 3rd patch
- Dependency related sashiko comments ignored as they are addressed in the
prerequisite patch information
- Link to v3: https://lore.kernel.org/r/20260723-08-dts-v3-0-074eb131f382@oss.qualcomm.com
Changes in v3:
- Address v2 comments
- Introduce RDP504 common dtsi and two board specific dts files one
for NAND and one for eMMC
- Move 'dr_mode' to board file instead of SoC file
- Dropped 'polling-delay-passive = 0' and 'polling-delay = 0'
- Use THERMAL_NO_LIMIT in 'cooling-device'
- '\n' before status = okay
- Removed 'num-lanes' from pcie0 & pcie1 nodes
- Link to v2: https://lore.kernel.org/r/20260715-08-dts-v2-0-b060b68e0256@oss.qualcomm.com
Changes in v2:
- Change usb3@8a00000 -> usb@8a00000
- Ignore other comments as they are covered in the following prerequisite
prerequisite-message-id: <20260514-icc-ipq5210-v1-0-b5070dfbe460@oss.qualcomm.com>
- Link to v1: https://lore.kernel.org/r/20260707-08-dts-v1-0-fce82e14cd1d@oss.qualcomm.com
---
Varadarajan Narayanan (11):
arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals
arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file
arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant DT file
arm64: dts: qcom: ipq5210: Add support for WPS button
arm64: dts: qcom: ipq5210: Add C3 CPU idle state
arm64: dts: qcom: ipq5210: Add ICE support to SDHCI
arm64: dts: qcom: ipq5210: Enable download mode support
arm64: dts: qcom: ipq5210: Enable the PWM block
arm64: dts: qcom: ipq5210: Add I2C nodes
arm64: dts: qcom: ipq5210: Add SPI node definitions
arm64: dts: qcom: ipq5210: Add random number generator node
arch/arm64/boot/dts/qcom/Makefile | 2 +-
.../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 276 ++++++++
arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts | 17 +
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 77 +--
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 752 ++++++++++++++++++++-
5 files changed, 1043 insertions(+), 81 deletions(-)
---
base-commit: 827b0a511f329ad072f0f689407b3595a104cdf1
change-id: 20260706-08-dts-e830bb27c72b
prerequisite-message-id: <20261013-icc-v2-0-196b219e25c1@oss.qualcomm.com>
prerequisite-patch-id: 0b6145b6635b18fe79fbbff5815041b43778c5ed
prerequisite-patch-id: 924c6ff7baf4283ac7991ee94c803a00fc5cece4
prerequisite-patch-id: c2fe1800fe769dccd37f94c19860a07f979e3c4c
prerequisite-message-id: <20260615085218.1421347-1-varadarajan.narayanan@oss.qualcomm.com>
prerequisite-patch-id: 66aa95814074faffb61393faa30396c42af41126
prerequisite-patch-id: 0a03dc1c91a2f0c03af823aa43f59a9005eb8607
prerequisite-message-id: <20261008-rng-v1-1-785580a8b48f@oss.qualcomm.com>
prerequisite-patch-id: 08aa18faecd4f3588cfd01f3330eadb1a76dcd13
prerequisite-message-id: <20261105194606.772346-2-krzysztof.kozlowski@oss.qualcomm.com>
prerequisite-patch-id: 72e661bc72d8535e1dabc144e81978bc5161c3f5
prerequisite-message-id: <20261021-ice-v2-1-3dfa8f343ceb@oss.qualcomm.com>
prerequisite-patch-id: e6cdcf2043620e898c6dc3a5c266678a2b08137b
Best regards,
--
Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 5:00 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan ` (9 subsequent siblings) 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan, Konrad Dybcio Describe common IPQ5210 SoC peripherals in the base DTSI so board DTS files can enable the hardware they use. Add nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS and thermal zones. Also describe the CPU OPP table and CPU cooling cells needed for CPU frequency scaling and thermal throttling. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 606 +++++++++++++++++++++++++++++++++- 1 file changed, 600 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index c4a760c1ab23..504364ca031c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -6,7 +6,10 @@ #include <dt-bindings/clock/qcom,ipq5210-cmn-pll.h> #include <dt-bindings/clock/qcom,ipq5210-gcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,apss-ipq.h> +#include <dt-bindings/interconnect/qcom,ipq5210.h> #include <dt-bindings/reset/qcom,ipq5210-gcc.h> +#include <dt-bindings/thermal/thermal.h> / { #address-cells = <2>; @@ -41,36 +44,48 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; enable-method = "psci"; next-level-cache = <&l2_0>; + #cooling-cells = <2>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; l2_0: l2-cache { @@ -97,6 +112,40 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells = <&cpu_speed_bin>; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-supported-hw = <0x3>; + opp-microvolt = <850000>; + clock-latency-ns = <200000>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-supported-hw = <0x3>; + opp-microvolt = <850000>; + clock-latency-ns = <200000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x3>; + opp-microvolt = <850000>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-supported-hw = <0x1>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -143,6 +192,68 @@ soc@0 { dma-ranges = <0 0 0 0 0x10 0>; ranges = <0 0 0 0 0x10 0>; + qusb_phy_0: phy@7b000 { + compatible = "qcom,ipq5210-qusb2-phy", "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x0007b000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible = "qcom,ipq5210-qmp-usb3-phy", "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0 0x0007d000 0x0 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + + status = "disabled"; + }; + + pcie0_phy: phy@84000 { + compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x00084000 0x0 0x1000>; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + status = "disabled"; + }; + cmn_pll: clock-controller@9b000 { compatible = "qcom,ipq5210-cmn-pll"; reg = <0x0 0x0009b000 0x0 0x800>; @@ -155,6 +266,108 @@ cmn_pll: clock-controller@9b000 { assigned-clock-rates-u64 = /bits/ 64 <12000000000>; }; + efuse@a4000 { + compatible = "qcom,ipq5210-qfprom", "qcom,qfprom"; + reg = <0x0 0x000a4000 0x0 0x741>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_bin: cpu-speed-bin@28 { + reg = <0x28 0x1>; + bits = <0 8>; + }; + + tsens_sens11_off: s11@3dd { + reg = <0x3dd 0x1>; + bits = <4 4>; + }; + + tsens_sens12_off: s12@3de { + reg = <0x3de 0x1>; + bits = <0 4>; + }; + + tsens_sens13_off: s13@3de { + reg = <0x3de 0x1>; + bits = <4 4>; + }; + + tsens_sens14_off: s14@3e5 { + reg = <0x3e5 0x2>; + bits = <7 4>; + }; + + tsens_sens15_off: s15@3e6 { + reg = <0x3e6 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@419 { + reg = <0x419 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@419 { + reg = <0x419 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@41a { + reg = <0x41a 0x2>; + bits = <5 10>; + }; + }; + + pcie1_phy: phy@f4000 { + compatible = "qcom,ipq5210-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x000f4000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "pipe"; + + assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates = <20000000>; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk"; + + #phy-cells = <0>; + status = "disabled"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5210-tsens", "qcom,ipq5332-tsens"; + reg = <0x0 0x004a9000 0x0 0x1000>, + <0x0 0x004a8000 0x0 0x1000>; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names = "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <5>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5210-tlmm"; reg = <0x0 0x01000000 0x0 0x300000>; @@ -171,8 +384,8 @@ gcc: clock-controller@1800000 { reg = <0x0 0x01800000 0x0 0x40000>; clocks = <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>; #clock-cells = <1>; @@ -230,6 +443,88 @@ sdhc: mmc@7804000 { status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1c000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + + status = "okay"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq5210-snand", "qcom,ipq9574-snand"; + reg = <0x0 0x079b0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", + "aon", + "iom"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + + status = "disabled"; + }; + + usb3: usb@8a00000 { + compatible = "qcom,ipq5210-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x08a00000 0x0 0x200000>; + + clocks = <&gcc GCC_CNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "qusb2_phy", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + phys = <&qusb_phy_0>, + <&ssphy_0>; + phy-names = "usb2-phy", + "usb3-phy"; + + resets = <&gcc GCC_USB_BCR>; + + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -269,6 +564,24 @@ watchdog@b017000 { clocks = <&sleep_clk>; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5210-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0 0x0b111000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; + #mbox-cells = <1>; + }; + + a53pll: clock@b116000 { + compatible = "qcom,ipq5210-a53pll"; + reg = <0x0 0x0b116000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; @@ -332,6 +645,287 @@ frame@b128000 { status = "disabled"; }; }; + + pcie1: pcie@50000000 { + compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg = <0x0 0x50000000 0x0 0xf1c>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x0 0x0 0x50200000 0x0 0x00100000>, + <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects = <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>, + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie1_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie1_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible = "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg = <0x0 0x70000000 0x0 0xf1c>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names = "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x0 0x0 0x70200000 0x0 0x00100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names = "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names = "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects = <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>, + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + status = "disabled"; + + pcie0_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie0_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; + + thermal_zones: thermal-zones { + ethphy-thermal { + thermal-sensors = <&tsens 11>; + + trips { + ethphy-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + pon-uniphy-thermal { + thermal-sensors = <&tsens 12>; + + trips { + pon-uniphy-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + nss-top-thermal { + thermal-sensors = <&tsens 13>; + + trips { + nss-top-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors = <&tsens 14>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu0_thermal_alert: cpu-passive { + temperature = <100000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_thermal_alert>; + /* Set maximum frequency as 816 MHz */ + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + thermal-sensors = <&tsens 15>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu-passive { + temperature = <100000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + }; }; timer { -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals 2026-11-12 4:36 ` [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan @ 2026-11-12 5:00 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 5:00 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 5 potential issues to consider: - [Medium] arm64: dts: qcom: ipq5210: swapped pcie-mem and cpu-pcie interconnects in pcie0/1 - [Medium] arm64: dts: qcom: ipq5210: missing ssphy_0 pipe clock phandle in gcc clocks - [Medium] arm64: dts: qcom: ipq5210: incomplete passive cooling setup in CPU thermal zones - [Low] arm64: dts: qcom: ipq5210: qpic_bam enabled unconditionally in base SoC DTSI - [Low] arm64: dts: qcom: ipq5210: stale 816 MHz comment in cpu0-thermal cooling-maps -- commit d1ab8c6e1b0ebf5f28504c611ba26174cc9742a0 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals This commit adds IPQ5210 device tree nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS, thermal zones, and the CPU OPP table and cooling cells. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > index c4a760c1ab23e..504364ca031c4 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi [ ... ] > @@ -171,8 +384,8 @@ gcc: clock-controller@1800000 { > reg = <0x0 0x01800000 0x0 0x40000>; > clocks = <&xo_board>, > <&sleep_clk>, > - <0>, > - <0>, > + <&pcie0_phy>, > + <&pcie1_phy>, > <0>, > <0>; > #clock-cells = <1>; [Severity: Medium] Should the fifth entry in gcc's clocks property be <&ssphy_0> instead of <0>? In drivers/clk/qcom/gcc-ipq5210.c, gcc_usb0_pipe_clk_src resolves its sole parent via DT clock index DT_USB3_PHY0_CC_PIPE_CLK (4). Leaving that slot as <0> keeps gcc_usb0_pipe_clk_src and its child GCC_USB0_PIPE_CLK orphaned with a rate of 0 when USB3 is enabled. > @@ -230,6 +443,88 @@ sdhc: mmc@7804000 { > status = "disabled"; > }; > > + qpic_bam: dma-controller@7984000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x0 0x07984000 0x0 0x1c000>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QPIC_AHB_CLK>; > + clock-names = "bam_clk"; > + #dma-cells = <1>; > + qcom,ee = <0>; > + > + status = "okay"; > + }; [Severity: Low] Should qpic_bam have status = "disabled" here so boards only enable it alongside qpic_nand? Keeping it enabled in the base DTSI causes bam_dma_probe() to enable GCC_QPIC_AHB_CLK, reset the QPIC BAM block, and claim GIC_SPI 56 even on eMMC boards that do not use QPIC NAND. [ ... ] > @@ -332,6 +645,287 @@ frame@b128000 { > status = "disabled"; > }; > }; > + > + pcie1: pcie@50000000 { [ ... ] > + interconnects = <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>, > + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; > + interconnect-names = "pcie-mem", "cpu-pcie"; [ ... ] > + pcie0: pcie@70000000 { [ ... ] > + interconnects = <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>, > + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; > + interconnect-names = "pcie-mem", "cpu-pcie"; [Severity: Medium] Are the "pcie-mem" and "cpu-pcie" interconnect paths swapped in both pcie1 and pcie0? drivers/clk/qcom/gcc-ipq5210.c maps the CNOC pairs to the AXI slave clocks and the SNOC pairs to the AXI master clocks: drivers/clk/qcom/gcc-ipq5210.c: { MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_CNOC_PCIE0_1LANE_S_CLK }, { MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_CNOC_PCIE1_2LANE_S_CLK }, { MASTER_SNOC_PCIE0, SLAVE_SNOC_PCIE0, GCC_SNOC_PCIE0_AXI_M_CLK }, { MASTER_SNOC_PCIE1, SLAVE_SNOC_PCIE1, GCC_SNOC_PCIE1_AXI_M_CLK }, With CNOC bound to "pcie-mem" and SNOC bound to "cpu-pcie", pcie-qcom scales the CNOC AXI slave clock with PCIe link speed while clamping the SNOC AXI master DMA clock to 1 KBps, and disables the SNOC AXI master DMA clock via icc_disable(pcie->icc_cpu) during non-S2RAM suspend when the link stays active. [ ... ] > + cpu0-thermal { > + thermal-sensors = <&tsens 14>; > + > + trips { > + cpu-critical { > + temperature = <115000>; > + hysteresis = <9000>; > + type = "critical"; > + }; > + > + cpu0_thermal_alert: cpu-passive { > + temperature = <100000>; > + hysteresis = <9000>; > + type = "passive"; > + }; > + }; > + > + cooling-maps { > + map0 { > + trip = <&cpu0_thermal_alert>; > + /* Set maximum frequency as 816 MHz */ > + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > + }; [Severity: Low] As reported by Konrad Dybcio on v4 [1], the "Set maximum frequency as 816 MHz" comment is stale now that cooling-device uses THERMAL_NO_LIMIT instead of pinning state 3. > + > + cpu1-thermal { > + thermal-sensors = <&tsens 15>; > + > + trips { > + cpu-critical { > + temperature = <115000>; > + hysteresis = <9000>; > + type = "critical"; > + }; > + > + cpu-passive { > + temperature = <100000>; > + hysteresis = <9000>; > + type = "passive"; > + }; > + }; > + }; > }; [Severity: Medium] Is cpu1-thermal missing a cooling-maps node for its cpu-passive trip, and do both cpu0-thermal and cpu1-thermal need polling-delay-passive? Without cooling-maps in cpu1-thermal, crossing 100 C on TSENS sensor 15 binds no cooling devices and triggers no throttling. In addition, because neither zone sets polling-delay-passive, crossing the single 100 C passive trip in cpu0-thermal steps the CPU cooling state down by only one OPP (1416 MHz to 1200 MHz) while TSENS advances its upper interrupt threshold to 115 C, with no passive polling scheduled to step down further through 1008 MHz and 816 MHz. [1] https://lore.kernel.org/r/11f0df89-8bd5-41ed-85a3-b7164123f8f7@oss.qualcomm.com -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:58 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 03/11] arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant " Varadarajan Narayanan ` (8 subsequent siblings) 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND share the GPIOs. The board has to be reworked to change from EMMC to NAND variant. Rename ipq5210-rdp504.dts as ipq5210-rdp504-common.dtsi and include it in variant specific DTS file. Describe the fixed USB regulators, PCIe reset GPIOs, QPIC SPI NAND flash and required pinctrl states. Enable QPIC BAM, USB and PCIe for the board. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 225 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 79 +------- 2 files changed, 227 insertions(+), 77 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi new file mode 100644 index 000000000000..6fb8666ffbfd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "ipq5210.dtsi" + +/ { + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0"; + }; + + vreg_misc_3p3: regulator-usb-3p3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "usb_hs_vdda_3p3"; + }; + + vreg_misc_1p8: regulator-usb-1p8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vdda_1p8_usb"; + }; + + vreg_misc_0p925: regulator-usb-0p925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vdd_core_usb"; + }; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; +}; + +&qusb_phy_0 { + vdd-supply = <&vreg_misc_0p925>; + vdda-pll-supply = <&vreg_misc_1p8>; + vdda-phy-dpdm-supply = <&vreg_misc_3p3>; + + status = "okay"; +}; + +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHz, 96 MHz or 192 MHz. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHz. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + +&sdhc { + max-frequency = <192000000>; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 = <&sdhc_default_state>; + pinctrl-names = "default"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&ssphy_0 { + vdda-pll-supply = <&vreg_misc_1p8>; + vdda-phy-supply = <&vreg_misc_0p925>; + + status = "okay"; +}; + +&tlmm { + pcie1_default_state: pcie1-default-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + pcie0_default_state: pcie0-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + qpic_snand_default_state: qpic-snand-default-state { + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio4"; + function = "qspi_cs_n"; + drive-strength = <8>; + bias-disable; + }; + + clock-pins { + pins = "gpio5"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + }; + + qup_uart1_default_state: qup-uart1-default-state { + pins = "gpio38", "gpio39"; + function = "qup_se1"; + drive-strength = <6>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&qup_uart1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + + status = "okay"; +}; + +/* + * The frequency of xo_board is fixed to 24 MHz, which is routed + * from WiFi output clock 48 MHz divided by 2. + */ +&xo_board { + clock-div = <2>; + clock-mult = <1>; +}; + +&xo_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts index 519307c6b61e..43cdb981a4ba 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -5,30 +5,11 @@ /dts-v1/; -#include "ipq5210.dtsi" +#include "ipq5210-rdp504-common.dtsi" / { - model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504 (eMMC)"; compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -/* - * The bootstrap pins for the board select the XO clock frequency that - * supports 48 MHz, 96 MHz or 192 MHz. This setting automatically - * enables the right dividers, to ensure the reference clock output - * from WiFi to the CMN PLL is 48 MHz. - */ -&ref_48mhz_clk { - clock-div = <1>; - clock-mult = <1>; }; &sdhc { @@ -41,59 +22,3 @@ &sdhc { status = "okay"; }; - -&sleep_clk { - clock-frequency = <32000>; -}; - -&tlmm { - qup_uart1_default_state: qup-uart1-default-state { - pins = "gpio38", "gpio39"; - function = "qup_se1"; - drive-strength = <6>; - bias-pull-down; - }; - - sdhc_default_state: sdhc-default-state { - clk-pins { - pins = "gpio5"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio4"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; -}; - -&uart1 { - pinctrl-0 = <&qup_uart1_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - -/* - * The frequency of xo_board is fixed to 24 MHz, which is routed - * from WiFi output clock 48 MHz divided by 2. - */ -&xo_board { - clock-div = <2>; - clock-mult = <1>; -}; - -&xo_clk { - clock-frequency = <48000000>; -}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file 2026-11-12 4:36 ` [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan @ 2026-11-12 4:58 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 4:58 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 3 potential issues to consider: - [Medium] arm64: dts: qcom: ipq5210: missing ssphy_0 pipe clock phandle in gcc - [Low] arm64: dts: qcom: duplicated sdhc properties in ipq5210-rdp504.dts - [Low] arm64: dts: qcom: commit message mismatch on QPIC BAM and file rename -- commit feb4d109494ac58f48292db37ef205aa3dd5e3c3 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file This commit factors common board nodes out of ipq5210-rdp504.dts into ipq5210-rdp504-common.dtsi and adds USB, PCIe, and QPIC SPI NAND nodes for the RDP504 board. > RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND > share the GPIOs. The board has to be reworked to change from EMMC > to NAND variant. Rename ipq5210-rdp504.dts as ipq5210-rdp504-common.dtsi > and include it in variant specific DTS file. > > Describe the fixed USB regulators, PCIe reset GPIOs, QPIC SPI NAND flash > and required pinctrl states. Enable QPIC BAM, USB and PCIe for the board. [Severity: Low] Is the commit message accurate about enabling QPIC BAM and renaming ipq5210-rdp504.dts? Neither ipq5210-rdp504-common.dtsi nor ipq5210-rdp504.dts references or enables qpic_bam, which was already set to status = "okay" unconditionally in arch/arm64/boot/dts/qcom/ipq5210.dtsi. Also, ipq5210-rdp504.dts is not renamed; it is kept as the eMMC variant DTS while shared nodes are moved to ipq5210-rdp504-common.dtsi. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi > new file mode 100644 > index 0000000000000..6fb8666ffbfda > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi [ ... ] > +&sdhc { > + max-frequency = <192000000>; > + bus-width = <4>; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; > + pinctrl-0 = <&sdhc_default_state>; > + pinctrl-names = "default"; > +}; > + > +&sleep_clk { > + clock-frequency = <32000>; > +}; > + > +&ssphy_0 { > + vdda-pll-supply = <&vreg_misc_1p8>; > + vdda-phy-supply = <&vreg_misc_0p925>; > + > + status = "okay"; > +}; [Severity: Medium] Does enabling ssphy_0 leave gcc_usb0_pipe_clk_src and gcc_usb0_pipe_clk orphaned because gcc has <0> instead of <&ssphy_0> at clock index 4 in ipq5210.dtsi? When ssphy_0 probes, qmp_usb_probe() registers the 125 MHz usb0_pipe_clk provider and requests <&gcc GCC_USB0_PIPE_CLK>. In drivers/clk/qcom/gcc-ipq5210.c, gcc_usb0_pipe_clk_src resolves its parent solely through .parent_data = { .index = DT_USB3_PHY0_CC_PIPE_CLK } (index 4), but commit "arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals" left index 4 of gcc clocks as <0>: arch/arm64/boot/dts/qcom/ipq5210.dtsi: gcc: clock-controller@1800000 { ... clocks = <&xo_board>, <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy>, <0>, <0>; Because index 4 is <0>, of_parse_clkspec() returns -ENOENT when resolving gcc_usb0_pipe_clk_src's parent, leaving gcc_usb0_pipe_clk_src and gcc_usb0_pipe_clk permanently orphaned with a reported rate of 0 Hz and never preparing or enabling usb0_pipe_clk as their parent. [ ... ] > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > index 519307c6b61e5..43cdb981a4baa 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts > @@ -5,30 +5,11 @@ > > /dts-v1/; > > -#include "ipq5210.dtsi" > +#include "ipq5210-rdp504-common.dtsi" > > / { > - model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; > + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504 (eMMC)"; > compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; > - > - aliases { > - serial0 = &uart1; > - }; > - > - chosen { > - stdout-path = "serial0"; > - }; > -}; > - > -/* > - * The bootstrap pins for the board select the XO clock frequency that > - * supports 48 MHz, 96 MHz or 192 MHz. This setting automatically > - * enables the right dividers, to ensure the reference clock output > - * from WiFi to the CMN PLL is 48 MHz. > - */ > -&ref_48mhz_clk { > - clock-div = <1>; > - clock-mult = <1>; > }; > > &sdhc { > @@ -41,59 +22,3 @@ &sdhc { > > status = "okay"; > }; [Severity: Low] This isn't a bug, but &sdhc in ipq5210-rdp504.dts repeats max-frequency, bus-width, mmc-ddr-1_8v, mmc-hs200-1_8v, pinctrl-0, and pinctrl-names, which are already defined in &sdhc in ipq5210-rdp504-common.dtsi. Can ipq5210-rdp504.dts just set status = "okay" on &sdhc? -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=2 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 03/11] arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant DT file 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:49 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 04/11] arm64: dts: qcom: ipq5210: Add support for WPS button Varadarajan Narayanan ` (7 subsequent siblings) 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Add a DT file for the RDP504 NAND variant and include it in the Makefile. Enable QPIC NAND for the variant, and enable quad mode for it. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/Makefile | 2 +- arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 2 ++ arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts | 17 +++++++++++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8329c06b60a3..fcc94cbb3233 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -41,7 +41,7 @@ dtb-$(CONFIG_ARCH_QCOM) += hamoa-som-db5830.dtb dtb-$(CONFIG_ARCH_QCOM) += hawi-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb ipq5210-rdp504-nand.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index 6fb8666ffbfd..17daf277edbf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -87,6 +87,8 @@ flash@0 { nand-ecc-engine = <&qpic_nand>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts new file mode 100644 index 000000000000..1145fcf0a302 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210-rdp504-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504 (NAND)"; + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; +}; + +&qpic_nand { + status = "okay"; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 03/11] arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant DT file 2026-11-12 4:36 ` [PATCH v9 03/11] arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant " Varadarajan Narayanan @ 2026-11-12 4:49 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 4:49 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Medium] arm64: dts: qcom: ipq5210: identical root compatible on RDP504 NAND and eMMC -- commit 073c305d3df5613ad5b8c3e588379e6b62b9fe9c Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant DT file This commit adds a devicetree file for the IPQ5210 RDP504 NAND board variant, enables QPIC NAND in quad mode, and adds the new DTB to the Makefile. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts > new file mode 100644 > index 0000000000000..1145fcf0a3025 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts > @@ -0,0 +1,17 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +/dts-v1/; > + > +#include "ipq5210-rdp504-common.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504 (NAND)"; > + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; > +}; [Severity: Medium] Should ipq5210-rdp504-nand.dts use a distinct board compatible string instead of sharing "qcom,ipq5210-rdp504" with the eMMC variant in ipq5210-rdp504.dts? In ipq5210-rdp504-common.dtsi, qpic_snand_default_state and sdhc_default_state mux gpio0 through gpio5 to mutually exclusive functions for NAND and eMMC. When both DTBs are packaged in a multi-DTB image such as a FIT image, a bootloader matching on the root compatible property cannot distinguish between the two variants and may load the wrong DTB, causing storage initialization to fail. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=3 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 04/11] arm64: dts: qcom: ipq5210: Add support for WPS button 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (2 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 03/11] arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant " Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 05/11] arm64: dts: qcom: ipq5210: Add C3 CPU idle state Varadarajan Narayanan ` (6 subsequent siblings) 10 siblings, 0 replies; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan, Konrad Dybcio Add GPIO related nodes to enable WPS (Wi-Fi Protected Setup) in IPQ5210 based RDPs. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index 17daf277edbf..02fb76283f7f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include "ipq5210.dtsi" / { @@ -17,6 +18,19 @@ chosen { stdout-path = "serial0"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + vreg_misc_3p3: regulator-usb-3p3 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -132,6 +146,13 @@ &ssphy_0 { }; &tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + pcie1_default_state: pcie1-default-state { pins = "gpio29"; function = "gpio"; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 05/11] arm64: dts: qcom: ipq5210: Add C3 CPU idle state 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (3 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 04/11] arm64: dts: qcom: ipq5210: Add support for WPS button Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 06/11] arm64: dts: qcom: ipq5210: Add ICE support to SDHCI Varadarajan Narayanan ` (5 subsequent siblings) 10 siblings, 0 replies; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Add the PSCI-backed C3 idle state for the Cortex-A53 CPUs and wire it to all CPU nodes. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 504364ca031c..f3d688fded80 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -49,6 +49,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; + cpu-idle-states = <&cpu_sleep_0>; next-level-cache = <&l2_0>; #cooling-cells = <2>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; @@ -60,6 +61,7 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; + cpu-idle-states = <&cpu_sleep_0>; next-level-cache = <&l2_0>; #cooling-cells = <2>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; @@ -71,6 +73,7 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x2>; enable-method = "psci"; + cpu-idle-states = <&cpu_sleep_0>; next-level-cache = <&l2_0>; #cooling-cells = <2>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; @@ -82,6 +85,7 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x3>; enable-method = "psci"; + cpu-idle-states = <&cpu_sleep_0>; next-level-cache = <&l2_0>; #cooling-cells = <2>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; @@ -93,6 +97,20 @@ l2_0: l2-cache { cache-level = <2>; cache-unified; }; + + idle-states { + entry-method = "psci"; + + cpu_sleep_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <181>; + exit-latency-us = <149>; + min-residency-us = <703>; + local-timer-stop; + }; + }; }; firmware { -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 06/11] arm64: dts: qcom: ipq5210: Add ICE support to SDHCI 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (4 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 05/11] arm64: dts: qcom: ipq5210: Add C3 CPU idle state Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:57 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 07/11] arm64: dts: qcom: ipq5210: Enable download mode support Varadarajan Narayanan ` (4 subsequent siblings) 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Describe the SDHCI ICE register region and clock, and enable CQE support for the IPQ5210 SDHCI controller. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 4 ++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts index 43cdb981a4ba..aa8b37d837ec 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -22,3 +22,7 @@ &sdhc { status = "okay"; }; + +&sdhc_ice { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index f3d688fded80..267255d2980a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -164,6 +164,14 @@ opp-1416000000 { }; }; + sdhc_opp_table_300mhz: opp-table-300mhz { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -456,7 +464,25 @@ sdhc: mmc@7804000 { clock-names = "iface", "core", "xo"; + + qcom,ice = <&sdhc_ice>; + non-removable; + operating-points-v2 = <&sdhc_opp_table_300mhz>; + supports-cqe; + + status = "disabled"; + }; + + sdhc_ice: crypto@7808000 { + compatible = "qcom,ipq5210-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x07808000 0x0 0x2000>; + + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", + "iface"; status = "disabled"; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 06/11] arm64: dts: qcom: ipq5210: Add ICE support to SDHCI 2026-11-12 4:36 ` [PATCH v9 06/11] arm64: dts: qcom: ipq5210: Add ICE support to SDHCI Varadarajan Narayanan @ 2026-11-12 4:57 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 4:57 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Medium] arm64: dts: qcom: ipq5210: 300 MHz ICE OPP table attached to sdhc node -- commit 26d7894a0ee84572c70f5300978aa25be22d94a5 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Add ICE support to SDHCI This commit adds the SDHCI inline crypto engine (ICE) node, a 300 MHz OPP table, and CQE support for the IPQ5210 SDHCI controller, and enables ICE on RDP504. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > index f3d688fded802..267255d2980a3 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > @@ -164,6 +164,14 @@ opp-1416000000 { > }; > }; > > + sdhc_opp_table_300mhz: opp-table-300mhz { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + }; > + }; > + > pmu { > compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > @@ -456,7 +464,25 @@ sdhc: mmc@7804000 { > clock-names = "iface", > "core", > "xo"; > + > + qcom,ice = <&sdhc_ice>; > + > non-removable; > + operating-points-v2 = <&sdhc_opp_table_300mhz>; > + supports-cqe; > + > + status = "disabled"; > + }; > + > + sdhc_ice: crypto@7808000 { > + compatible = "qcom,ipq5210-inline-crypto-engine", > + "qcom,inline-crypto-engine"; > + reg = <0x0 0x07808000 0x0 0x2000>; > + > + clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, > + <&gcc GCC_SDCC1_AHB_CLK>; > + clock-names = "core", > + "iface"; > > status = "disabled"; > }; [Severity: Medium] Is sdhc_opp_table_300mhz attached to the wrong node here? sdhci_msm_probe() calls devm_pm_opp_set_clkname(&pdev->dev, "core") and devm_pm_opp_of_add_table(&pdev->dev), which binds operating-points-v2 on sdhc to sdhc's "core" clock (GCC_SDCC1_APPS_CLK). In drivers/clk/qcom/gcc-ipq5210.c, ftbl_gcc_sdcc1_apps_clk_src only supports rates up to 200 MHz, whereas 300 MHz is the rate in ftbl_gcc_sdcc1_ice_core_clk_src for GCC_SDCC1_ICE_CORE_CLK on sdhc_ice. Attaching the 300 MHz OPP table to sdhc gives GCC_SDCC1_APPS_CLK an unreachable 300 MHz OPP while leaving GCC_SDCC1_ICE_CORE_CLK on sdhc_ice with no rate configuration (qcom_ice_create() only enables its "core" clock and does not parse an OPP table). -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=6 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 07/11] arm64: dts: qcom: ipq5210: Enable download mode support 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (5 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 06/11] arm64: dts: qcom: ipq5210: Add ICE support to SDHCI Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block Varadarajan Narayanan ` (3 subsequent siblings) 10 siblings, 0 replies; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan, Konrad Dybcio Enable the support for download mode to collect the crashdumps if system crashes, to debug crashes extensively. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 267255d2980a..aa1045f20ed2 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -121,6 +121,7 @@ optee { scm { compatible = "qcom,scm-ipq5210", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x25100>; }; }; @@ -425,6 +426,11 @@ tcsr_mutex: hwlock@1905000 { #hwlock-cells = <1>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq5210", "syscon"; + reg = <0x0 0x01937000 0x0 0x2b000>; + }; + qupv3: geniqup@1ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x01ac0000 0x0 0x2000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (6 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 07/11] arm64: dts: qcom: ipq5210: Enable download mode support Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:48 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes Varadarajan Narayanan ` (2 subsequent siblings) 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Describe and enable the PWM block on IPQ5210. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index 02fb76283f7f..87a7e625a2a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -89,6 +89,11 @@ &pcie1_port0 { reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; }; +&pwm { + pinctrl-0 = <&pwm_default_state>; + pinctrl-names = "default"; +}; + &qpic_nand { pinctrl-0 = <&qpic_snand_default_state>; pinctrl-names = "default"; @@ -167,6 +172,13 @@ pcie0_default_state: pcie0-default-state { bias-pull-down; }; + pwm_default_state: pwm-default-state { + pins = "gpio11"; + function = "pwm0"; + drive-strength = <6>; + bias-pull-down; + }; + qpic_snand_default_state: qpic-snand-default-state { data-pins { pins = "gpio0", "gpio1", "gpio2", "gpio3"; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index aa1045f20ed2..4cb9f399d480 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -431,6 +431,16 @@ tcsr: syscon@1937000 { reg = <0x0 0x01937000 0x0 0x2b000>; }; + pwm: pwm@1941010 { + compatible = "qcom,ipq5210-pwm", "qcom,ipq6018-pwm"; + reg = <0x0 0x01941010 0x0 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + status = "okay"; + }; + qupv3: geniqup@1ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x01ac0000 0x0 0x2000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block 2026-11-12 4:36 ` [PATCH v9 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block Varadarajan Narayanan @ 2026-11-12 4:48 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 4:48 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Low] arm64: dts: qcom: ipq5210: pwm node enabled in SoC DTSI instead of board DTSI -- commit 2d83ac83097807a2fcd75eaf7c88a88dc70672e9 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Enable the PWM block This commit adds the PWM controller node to the IPQ5210 SoC device tree and configures its pinmux on the RDP504 common board file. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi > index 02fb76283f7fa..87a7e625a2a41 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi > @@ -89,6 +89,11 @@ &pcie1_port0 { > reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; > }; > > +&pwm { > + pinctrl-0 = <&pwm_default_state>; > + pinctrl-names = "default"; > +}; [ ... ] > diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > index aa1045f20ed20..4cb9f399d4808 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > @@ -431,6 +431,16 @@ tcsr: syscon@1937000 { > reg = <0x0 0x01937000 0x0 0x2b000>; > }; > > + pwm: pwm@1941010 { > + compatible = "qcom,ipq5210-pwm", "qcom,ipq6018-pwm"; > + reg = <0x0 0x01941010 0x0 0x20>; > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clock-rates = <100000000>; > + #pwm-cells = <3>; > + status = "okay"; > + }; [Severity: Low] Should pwm@1941010 have status = "disabled" here in ipq5210.dtsi, with status = "okay" moved to the &pwm node in ipq5210-rdp504-common.dtsi? The PWM pinmux is board-specific, and ipq_pwm_probe() calls devm_clk_get_enabled() and devm_clk_rate_exclusive_get(), so enabling the controller in the SoC DTSI keeps GCC_ADSS_PWM_CLK ungated and rate-locked at 100 MHz on every IPQ5210 board even when PWM is unused. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=8 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (7 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 4:56 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 11/11] arm64: dts: qcom: ipq5210: Add random number generator node Varadarajan Narayanan 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Add the QUPv3 I2C controller nodes for IPQ5210 and enable I2C0 with the required pin configuration on RDP504. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 16 ++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 47 ++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index 87a7e625a2a4..7cbdcf58d946 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -59,6 +59,13 @@ vreg_misc_0p925: regulator-usb-0p925 { }; }; +&i2c0 { + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -202,6 +209,15 @@ clock-pins { }; }; + qup_i2c0_default: qup-i2c0-default-state { + qup-i2c0-pins { + pins = "gpio20", "gpio21"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-up; + }; + }; + qup_uart1_default_state: qup-uart1-default-state { pins = "gpio38", "gpio39"; function = "qup_se1"; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 4cb9f399d480..36f874e57b42 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -173,6 +173,14 @@ opp-300000000 { }; }; + i2c_opp_table_32mhz: opp-table-qup32mhz { + compatible = "operating-points-v2"; + + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -460,6 +468,45 @@ uart1: serial@1a84000 { status = "disabled"; }; + + i2c0: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c1: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c2: i2c@1a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; }; sdhc: mmc@7804000 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes 2026-11-12 4:36 ` [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes Varadarajan Narayanan @ 2026-11-12 4:56 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 4:56 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [High] arm64: dts: qcom: ipq5210: unconfigured 32 MHz SE clock in geni_i2c_probe() -- commit 0886413b485197e28c9ca095b2bedf736adf3f28 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Add I2C nodes This commit adds the QUPv3 I2C controller nodes and 32 MHz OPP table for IPQ5210 and enables i2c0 on RDP504. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > index 4cb9f399d4808..36f874e57b425 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > @@ -173,6 +173,14 @@ opp-300000000 { > }; > }; > > + i2c_opp_table_32mhz: opp-table-qup32mhz { > + compatible = "operating-points-v2"; > + > + opp-32000000 { > + opp-hz = /bits/ 64 <32000000>; > + }; > + }; > + > pmu { > compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > @@ -460,6 +468,45 @@ uart1: serial@1a84000 { > > status = "disabled"; > }; > + > + i2c0: i2c@1a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x01a88000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; > + clock-names = "se"; > + clock-frequency = <400000>; > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > + operating-points-v2 = <&i2c_opp_table_32mhz>; > + status = "disabled"; > + }; > + > + i2c1: i2c@1a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x01a8c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; > + clock-names = "se"; > + clock-frequency = <400000>; > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > + operating-points-v2 = <&i2c_opp_table_32mhz>; > + status = "disabled"; > + }; > + > + i2c2: i2c@1a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x01a94000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; > + clock-names = "se"; > + clock-frequency = <400000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; > + operating-points-v2 = <&i2c_opp_table_32mhz>; > + status = "disabled"; > + }; [Severity: High] Will geni_i2c_probe() fail with -EINVAL on i2c0, i2c1, and i2c2 when the bootloader has not already set the SE clock to 32 MHz? geni_se_resources_init() registers operating-points-v2 via devm_pm_opp_of_add_table(), but the qcom,geni-i2c driver never calls dev_pm_opp_set_rate() or clk_set_rate() before geni_i2c_clk_map_idx() checks the current clock rate: drivers/i2c/busses/i2c-qcom-geni.c:geni_i2c_clk_map_idx() { ... if (clk_get_rate(gi2c->se.clk) == GENI_SE_CLK_32MHZ) { req_freq = GENI_SE_CLK_32MHZ; itr = geni_i2c_clk_map_32mhz; } else { req_freq = GENI_SE_CLK_19P2MHZ; itr = geni_i2c_clk_map_19p2mhz; } ret = geni_se_clk_freq_match(&gi2c->se, req_freq, &gi2c->clk_idx, &res_freq, true); ... } In drivers/clk/qcom/gcc-ipq5210.c, ftbl_gcc_qupv3_wrap_se0_clk_src has a 24 MHz XO rate and a 32 MHz rate, but no 19.2 MHz entry. If the SE clock is left at its default rate at boot, clk_get_rate() is not 32 MHz, and geni_se_clk_freq_match() fails looking for 19.2 MHz. Setting assigned-clocks and assigned-clock-rates = <32000000> on these nodes (or applying the OPP rate in the driver before geni_i2c_clk_map_idx()) would ensure the SE clock runs at 32 MHz before probe. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=9 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (8 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 2026-11-12 5:00 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 11/11] arm64: dts: qcom: ipq5210: Add random number generator node Varadarajan Narayanan 10 siblings, 1 reply; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan Add SPI node definition for the QUP SPI blocks present in IPQ5210. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 36f874e57b42..052c2f3df94d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -181,6 +181,14 @@ opp-32000000 { }; }; + spi_opp_table_50mhz: opp-table-spi50mhz { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -459,6 +467,18 @@ qupv3: geniqup@1ac0000 { #address-cells = <2>; #size-cells = <2>; + spi0: spi@1a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&spi_opp_table_50mhz>; + status = "disabled"; + }; + uart1: serial@1a84000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x01a84000 0x0 0x4000>; @@ -495,6 +515,18 @@ i2c1: i2c@1a8c000 { status = "disabled"; }; + spi1: spi@1a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + operating-points-v2 = <&spi_opp_table_50mhz>; + status = "disabled"; + }; + i2c2: i2c@1a94000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x01a94000 0x0 0x4000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions 2026-11-12 4:36 ` [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions Varadarajan Narayanan @ 2026-11-12 5:00 ` sashiko-bot 0 siblings, 0 replies; 19+ messages in thread From: sashiko-bot @ 2026-11-12 5:00 UTC (permalink / raw) To: Varadarajan Narayanan; +Cc: devicetree, robh, conor+dt Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Medium] arm64: dts: qcom: ipq5210: 50 MHz SPI OPP cap breaks get_spi_clk_cfg() -- commit 146df0b74de51d5a0fb5f5d16a2e1f1177beaca7 Author: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> arm64: dts: qcom: ipq5210: Add SPI node definitions This commit adds the spi0 and spi1 QUPv3 GENI SPI nodes and a 50 MHz OPP table to the IPQ5210 device tree. > diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > index 36f874e57b425..052c2f3df94db 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi > @@ -181,6 +181,14 @@ opp-32000000 { > }; > }; > > + spi_opp_table_50mhz: opp-table-spi50mhz { > + compatible = "operating-points-v2"; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000>; > + }; > + }; > + > pmu { > compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > @@ -459,6 +467,18 @@ qupv3: geniqup@1ac0000 { > #address-cells = <2>; > #size-cells = <2>; > > + spi0: spi@1a80000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x01a80000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QUPV3_WRAP_SE0_CLK>; > + clock-names = "se"; > + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > + operating-points-v2 = <&spi_opp_table_50mhz>; > + status = "disabled"; > + }; > + > uart1: serial@1a84000 { > compatible = "qcom,geni-debug-uart"; > reg = <0x0 0x01a84000 0x0 0x4000>; > @@ -495,6 +515,18 @@ i2c1: i2c@1a8c000 { > status = "disabled"; > }; > > + spi1: spi@1a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x01a90000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&gcc GCC_QUPV3_WRAP_SE4_CLK>; > + clock-names = "se"; > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; > + operating-points-v2 = <&spi_opp_table_50mhz>; > + status = "disabled"; > + }; > + > i2c2: i2c@1a94000 { > compatible = "qcom,geni-i2c"; > reg = <0x0 0x01a94000 0x0 0x4000>; [Severity: Medium] Will capping spi_opp_table_50mhz at 50 MHz cause get_spi_clk_cfg() -> dev_pm_opp_set_rate() to fail with -ERANGE when geni_se_clk_freq_match() picks a source clock rate above 50 MHz? Both GCC_QUPV3_WRAP_SE0_CLK and GCC_QUPV3_WRAP_SE4_CLK use ftbl_gcc_qupv3_wrap_se0_clk_src, which exposes five rates above 50 MHz: drivers/clk/qcom/gcc-ipq5210.c: F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125), F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100), F(58986175, P_GPLL0_OUT_MAIN, 1, 16, 217), F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40), F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), geni_se_clk_tbl_get() populates se->clk_perf_tbl via clk_round_rate() without consulting the device OPP table, so geni_se_clk_freq_match() will select 51.2..64 MHz source rates whenever an integer divider yields a better match for the requested SPI bus speed (for example, 30 MHz = 60 MHz / 2 or 15 MHz = 60 MHz / 4). When get_spi_clk_cfg() then calls dev_pm_opp_set_rate(mas->dev, sclk_freq), _find_freq_ceil() returns -ERANGE because the highest OPP in spi_opp_table_50mhz is 50 MHz, aborting the SPI transfer. Since spi_opp_table_50mhz carries no voltage, level, or bandwidth votes, operating-points-v2 can be dropped (as on ipq5424.dtsi) so dev_pm_opp_set_rate() falls back to clk_set_rate(), or the OPP ceiling can be raised to 64 MHz if the SPI controller supports those source rates. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261112-08-dts-v9-0-c34de4f78fbb@oss.qualcomm.com?part=10 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 11/11] arm64: dts: qcom: ipq5210: Add random number generator node 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan ` (9 preceding siblings ...) 2026-11-12 4:36 ` [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions Varadarajan Narayanan @ 2026-11-12 4:36 ` Varadarajan Narayanan 10 siblings, 0 replies; 19+ messages in thread From: Varadarajan Narayanan @ 2026-11-12 4:36 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Abel Vesa Cc: linux-arm-msm, devicetree, linux-kernel, Varadarajan Narayanan, Konrad Dybcio Add random generator node for the RNG block present in IPQ5210. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 052c2f3df94d..219b3f3696e5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -411,6 +411,13 @@ tsens: thermal-sensor@4a9000 { #qcom,sensors = <5>; }; + rng: rng@4c3000 { + compatible = "qcom,ipq5210-trng", "qcom,trng"; + reg = <0x0 0x004c3000 0x0 0x1000>; + clocks = <&gcc GCC_QRNG_AHB_CLK>; + clock-names = "core"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5210-tlmm"; reg = <0x0 0x01000000 0x0 0x300000>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
end of thread, other threads:[~2026-11-12 5:00 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-11-12 4:36 [PATCH v9 00/11] Enable mutliple peripherals in IPQ5210 Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 01/11] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Varadarajan Narayanan 2026-11-12 5:00 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 02/11] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Varadarajan Narayanan 2026-11-12 4:58 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 03/11] arm64: dts: qcom: ipq5210: Introduce RDP504 NAND variant " Varadarajan Narayanan 2026-11-12 4:49 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 04/11] arm64: dts: qcom: ipq5210: Add support for WPS button Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 05/11] arm64: dts: qcom: ipq5210: Add C3 CPU idle state Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 06/11] arm64: dts: qcom: ipq5210: Add ICE support to SDHCI Varadarajan Narayanan 2026-11-12 4:57 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 07/11] arm64: dts: qcom: ipq5210: Enable download mode support Varadarajan Narayanan 2026-11-12 4:36 ` [PATCH v9 08/11] arm64: dts: qcom: ipq5210: Enable the PWM block Varadarajan Narayanan 2026-11-12 4:48 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 09/11] arm64: dts: qcom: ipq5210: Add I2C nodes Varadarajan Narayanan 2026-11-12 4:56 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 10/11] arm64: dts: qcom: ipq5210: Add SPI node definitions Varadarajan Narayanan 2026-11-12 5:00 ` sashiko-bot 2026-11-12 4:36 ` [PATCH v9 11/11] arm64: dts: qcom: ipq5210: Add random number generator node Varadarajan Narayanan
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