[PATCH] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Disable ASPM for TC9563 switch

[PATCH] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Disable ASPM for TC9563 switch

[Sushrut Shree Trivedi]

In QCS6490 RB3gen2 Industrial Mezzanine platform, we have single TC9563
switch on PCIe0 and two TC9563 switches connected in cascade on PCIe1.
When ASPM L0s and L1 (excluding L1 sub-states) are enabled on this PCIe
hierarchy, data traffic may require coordinated recovery across more
than one link and switch. A failure or delay in one link’s transition
could therefore make the end-to-end path temporarily unavailable
resulting in software reporting a link-down or failed return to L0.

To avoid the same, disable ASPM L0s and L1 for this platform via DT for
every individual PCIe link.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 39 ++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts       |  4 +--
 2 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index e8780646ab19..b8d56a216e40 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -104,6 +104,9 @@ pcie@0,0 {
 		pinctrl-0 = <&pcie0_tc9563_resx_n>;
 		pinctrl-names = "default";
 
+		aspm-no-l0s;
+		aspm-no-l1;
+
 		pcie@1,0 {
 			reg = <0x20800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
@@ -112,6 +115,9 @@ pcie@1,0 {
 			device_type = "pci";
 			ranges;
 			bus-range = <0x3 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@2,0 {
@@ -122,6 +128,9 @@ pcie@2,0 {
 			device_type = "pci";
 			ranges;
 			bus-range = <0x4 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@3,0 {
@@ -132,6 +141,9 @@ pcie@3,0 {
 			ranges;
 			bus-range = <0x5 0xff>;
 
+			aspm-no-l0s;
+			aspm-no-l1;
+
 			dev@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
 			};
@@ -163,6 +175,11 @@ &pcie1 {
 		    <0x901 &apps_smmu 0x1c99 0x0 0x1>;
 };
 
+&pcie1_port0 {
+	aspm-no-l0s;
+	aspm-no-l1;
+};
+
 &pcie1_switch0_dsp1 {
 	#address-cells = <3>;
 	#size-cells = <2>;
@@ -191,6 +208,9 @@ pcie@0,0 {
 		pinctrl-0 = <&pcie1_tc9563_resx_n>;
 		pinctrl-names = "default";
 
+		aspm-no-l0s;
+		aspm-no-l1;
+
 		pcie@1,0 {
 			reg = <0x40800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
@@ -199,6 +219,9 @@ pcie@1,0 {
 			device_type = "pci";
 			ranges;
 			bus-range = <0x3 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@2,0 {
@@ -209,6 +232,9 @@ pcie@2,0 {
 			device_type = "pci";
 			ranges;
 			bus-range = <0x4 0xff>;
+
+			aspm-no-l0s;
+			aspm-no-l1;
 		};
 
 		pcie@3,0 {
@@ -219,6 +245,9 @@ pcie@3,0 {
 			ranges;
 			bus-range = <0x5 0xff>;
 
+			aspm-no-l0s;
+			aspm-no-l1;
+
 			dev@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
 			};
@@ -230,6 +259,16 @@ dev@0,1 {
 	};
 };
 
+&pcie1_switch0_dsp2 {
+	aspm-no-l0s;
+	aspm-no-l1;
+};
+
+&pcie1_switch0_dsp3 {
+	aspm-no-l0s;
+	aspm-no-l1;
+};
+
 &tlmm {
 	pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
 		pins = "gpio78";
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 909039816a21..afdcb03b070f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -901,7 +901,7 @@ pcie1_switch0_dsp1: pcie@1,0 {
 			bus-range = <0x3 0xff>;
 		};
 
-		pcie@2,0 {
+		pcie1_switch0_dsp2: pcie@2,0 {
 			reg = <0x21000 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -946,7 +946,7 @@ gl3590_3_0: hub@2 {
 			};
 		};
 
-		pcie@3,0 {
+		pcie1_switch0_dsp3: pcie@3,0 {
 			reg = <0x21800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;
 			#size-cells = <2>;

---
base-commit: 630059a5a632377b9b7b487baccde92b7ae1dd47
change-id: 20261112-ik_disable_aspm-426b41312323

Best regards,
-- 
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Disable ASPM for TC9563 switch

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found no new issues
in this patch, but noticed 1 related pre-existing issue it does not
introduce:
- [Medium] arm64: dts: qcom: qcs6490-rb3gen2: missing wake-gpios in
  &pcie1_port0 [1]
--

commit ba184a8d8b0523b067f0174cb5855f2bdeb4aa59
Author: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Disable ASPM for TC9563 switch

This commit disables ASPM L0s and L1 on the PCIe links for the TC9563
switches on the QCS6490 RB3gen2 Industrial Mezzanine platform.

> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> index e8780646ab19c..b8d56a216e409 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso

[ ... ]

> @@ -163,6 +175,11 @@ &pcie1 {
>  		    <0x901 &apps_smmu 0x1c99 0x0 0x1>;
>  };
>  
> +&pcie1_port0 {
> +	aspm-no-l0s;
> +	aspm-no-l1;
> +};

[Severity: Medium]
This problem wasn't introduced by this patch, but is &pcie1_port0 missing a
wake-gpios property in arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
[1]?

In qcs6490-rb3gen2.dts, &pcie1 configures pcie1_wake_n (gpio3) in pinctrl-0,
while &pcie1_port0 only specifies reset-gpios:

arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts:
&pcie1 {
	pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
	pinctrl-names = "default";
	...
};

&pcie1_port0 {
	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;

	pcie@0,0 {

Without wake-gpios on &pcie1_port0, the PCIe driver cannot register the
WAKE# interrupt, preventing connected PCIe devices from waking the system
from low-power states.

[1] https://sashiko.dev/#/bug/linux-83ecae7c-c21b-44fd-b7c0-3b2ef2ca245c

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-ik_disable_aspm-v1-1-f43d8ca7703b@oss.qualcomm.com?part=1