* [PATCH v13 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE
2026-11-12 22:38 [PATCH v13 0/6] Enable ICE clock scaling Abhinaba Rakshit
@ 2026-11-12 22:38 ` Abhinaba Rakshit
2026-11-12 23:09 ` sashiko-bot
2026-11-12 22:38 ` [PATCH v13 2/6] ufs: host: Add ICE clock scaling during UFS clock changes Abhinaba Rakshit
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Abhinaba Rakshit @ 2026-11-12 22:38 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-crypto, linux-kernel, linux-scsi, linux-mmc,
devicetree, Abhinaba Rakshit, Abel Vesa
Register optional operation-points-v2 table for ICE device
during device probe. Attach the OPP-table with only the ICE
core clock. Since, dtbinding is on a transition phase to include
iface clock and clock-names, attaching the opp-table to core clock
remains optional such that it does not cause probe failures.
Introduce clock scaling API qcom_ice_scale_clk which scale ICE
core clock based on the target frequency provided and if a valid
OPP-table is registered. Use round_ceil passed to decide on the
rounding of the clock freq against OPP-table. Clock scaling is
disabled when a valid OPP-table is not registered.
This ensures when an ICE-device specific OPP table is available,
use the PM OPP framework to manage frequency scaling and maintain
proper power-domain constraints.
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/soc/qcom/ice.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/soc/qcom/ice.h | 2 ++
2 files changed, 77 insertions(+)
diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index f9ac45505908fc175f87098e9807c4642c3df321..2259dbecb8b513ff9f2731a969e126118dfb9b1c 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -17,6 +17,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/xarray.h>
+#include <linux/pm_opp.h>
#include <linux/firmware/qcom/qcom_scm.h>
@@ -113,6 +114,7 @@ struct qcom_ice {
bool use_hwkm;
bool hwkm_init_complete;
u8 hwkm_version;
+ bool has_opp;
};
static DEFINE_XARRAY(ice_handles);
@@ -560,6 +562,50 @@ int qcom_ice_import_key(struct qcom_ice *ice,
}
EXPORT_SYMBOL_GPL(qcom_ice_import_key);
+/**
+ * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations
+ * @ice: ICE driver data
+ * @target_freq: requested frequency in Hz
+ * @round_ceil: when true, selects nearest freq >= @target_freq;
+ * otherwise, selects nearest freq <= @target_freq
+ *
+ * Selects an OPP frequency based on @target_freq and the rounding direction
+ * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(),
+ * including any voltage or power-domain transitions handled by the OPP
+ * framework.
+ *
+ * Return: 0 on success; -EOPNOTSUPP if no OPP table; or errno from
+ * dev_pm_opp_set_rate()/OPP lookup.
+ */
+int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
+ bool round_ceil)
+{
+ unsigned long ice_freq = target_freq;
+ struct dev_pm_opp *opp;
+ int ret;
+
+ if (!ice->has_opp)
+ return -EOPNOTSUPP;
+
+ if (round_ceil)
+ opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq);
+ else
+ opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq);
+
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+ dev_pm_opp_put(opp);
+
+ ret = dev_pm_opp_set_rate(ice->dev, ice_freq);
+ if (ret) {
+ dev_err(ice->dev, "Unable to scale ICE clock rate\n");
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(qcom_ice_scale_clk);
+
static struct qcom_ice *qcom_ice_create(struct device *dev,
void __iomem *base)
{
@@ -738,6 +784,7 @@ static int qcom_ice_probe(struct platform_device *pdev)
unsigned long phandle = pdev->dev.of_node->phandle;
struct qcom_ice *engine;
void __iomem *base;
+ int err;
guard(mutex)(&ice_mutex);
@@ -756,6 +803,34 @@ static int qcom_ice_probe(struct platform_device *pdev)
return PTR_ERR(engine);
}
+ err = devm_pm_opp_set_clkname(&pdev->dev, "core");
+ if (err && err != -ENOENT) {
+ dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n");
+ /* Store the error pointer for devm_of_qcom_ice_get() */
+ xa_store(&ice_handles, phandle, ERR_PTR(err), GFP_KERNEL);
+ return err;
+ }
+
+ /* OPP table is optional */
+ err = devm_pm_opp_of_add_table(&pdev->dev);
+ if (err && err != -ENODEV) {
+ dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
+ /* Store the error pointer for devm_of_qcom_ice_get() */
+ xa_store(&ice_handles, phandle, ERR_PTR(err), GFP_KERNEL);
+ return err;
+ }
+
+ /*
+ * The OPP table is optional. devm_pm_opp_of_add_table() returns
+ * -ENODEV when no OPP table is present in DT, which is not treated
+ * as an error. Therefore, track successful OPP registration only
+ * when err is not -ENODEV.
+ */
+ if (err == -ENODEV)
+ dev_dbg(&pdev->dev, "ICE OPP table is not registered, please update your DT\n");
+ else
+ engine->has_opp = true;
+
xa_store(&ice_handles, phandle, engine, GFP_KERNEL);
return 0;
diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h
index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..4eb58a264d416e71228ed4b13e7f53c549261fdc 100644
--- a/include/soc/qcom/ice.h
+++ b/include/soc/qcom/ice.h
@@ -30,5 +30,7 @@ int qcom_ice_import_key(struct qcom_ice *ice,
const u8 *raw_key, size_t raw_key_size,
u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
struct qcom_ice *devm_of_qcom_ice_get(struct device *dev);
+int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
+ bool round_ceil);
#endif /* __QCOM_ICE_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v13 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE
2026-11-12 22:38 ` [PATCH v13 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE Abhinaba Rakshit
@ 2026-11-12 23:09 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-11-12 23:09 UTC (permalink / raw)
To: Abhinaba Rakshit, Abel Vesa, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Adrian Hunter, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-crypto, linux-scsi, devicetree, Abel Vesa
Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] soc: qcom: ice: qcom_ice_probe() fails with -EOPNOTSUPP when
!CONFIG_PM_OPP
- [Medium] soc: qcom: ice: unreleased OPP power-domain vote in
qcom_ice_suspend()
--
commit 9800ed91573a2f35826acc3c3e7577fb8636aaef
Author: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
soc: qcom: ice: Add OPP-based clock scaling support for ICE
This commit registers an optional OPP table for the ICE device during
probe and introduces qcom_ice_scale_clk() to scale the ICE core clock via
the PM OPP framework.
> diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
> index f9ac45505908f..2259dbecb8b51 100644
> --- a/drivers/soc/qcom/ice.c
> +++ b/drivers/soc/qcom/ice.c
[ ... ]
> @@ -560,6 +562,50 @@ int qcom_ice_import_key(struct qcom_ice *ice,
> }
> EXPORT_SYMBOL_GPL(qcom_ice_import_key);
>
> +/**
> + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations
> + * @ice: ICE driver data
> + * @target_freq: requested frequency in Hz
> + * @round_ceil: when true, selects nearest freq >= @target_freq;
> + * otherwise, selects nearest freq <= @target_freq
> + *
> + * Selects an OPP frequency based on @target_freq and the rounding direction
> + * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(),
> + * including any voltage or power-domain transitions handled by the OPP
> + * framework.
> + *
> + * Return: 0 on success; -EOPNOTSUPP if no OPP table; or errno from
> + * dev_pm_opp_set_rate()/OPP lookup.
> + */
> +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
> + bool round_ceil)
> +{
> + unsigned long ice_freq = target_freq;
> + struct dev_pm_opp *opp;
> + int ret;
> +
> + if (!ice->has_opp)
> + return -EOPNOTSUPP;
> +
> + if (round_ceil)
> + opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq);
> + else
> + opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq);
> +
> + if (IS_ERR(opp))
> + return PTR_ERR(opp);
> + dev_pm_opp_put(opp);
> +
> + ret = dev_pm_opp_set_rate(ice->dev, ice_freq);
> + if (ret) {
> + dev_err(ice->dev, "Unable to scale ICE clock rate\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk);
[Severity: Medium]
Does the performance state vote set here by dev_pm_opp_set_rate() stay
asserted when ICE suspends?
When dev_pm_opp_set_rate() scales up the clock, it sets the required-opps
performance state on ice->dev's power domain (and its parent RPMHPD_CX).
genpd only drops a device's performance state in genpd_runtime_suspend(),
but runtime PM is never enabled on ice->dev, and qcom_ice_suspend() only
disables iface_clk and core_clk without calling
dev_pm_opp_set_rate(ice->dev, 0):
drivers/soc/qcom/ice.c:qcom_ice_suspend() {
clk_disable_unprepare(ice->iface_clk);
clk_disable_unprepare(ice->core_clk);
ice->hwkm_init_complete = false;
return 0;
}
Once a storage consumer scales the ICE clock, the CX rail vote remains
elevated across both runtime suspend and system suspend.
> static struct qcom_ice *qcom_ice_create(struct device *dev,
> void __iomem *base)
> {
> @@ -738,6 +784,7 @@ static int qcom_ice_probe(struct platform_device *pdev)
> unsigned long phandle = pdev->dev.of_node->phandle;
> struct qcom_ice *engine;
> void __iomem *base;
> + int err;
>
> guard(mutex)(&ice_mutex);
>
> @@ -756,6 +803,34 @@ static int qcom_ice_probe(struct platform_device *pdev)
> return PTR_ERR(engine);
> }
>
> + err = devm_pm_opp_set_clkname(&pdev->dev, "core");
> + if (err && err != -ENOENT) {
> + dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n");
> + /* Store the error pointer for devm_of_qcom_ice_get() */
> + xa_store(&ice_handles, phandle, ERR_PTR(err), GFP_KERNEL);
> + return err;
> + }
> +
> + /* OPP table is optional */
> + err = devm_pm_opp_of_add_table(&pdev->dev);
> + if (err && err != -ENODEV) {
> + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
> + /* Store the error pointer for devm_of_qcom_ice_get() */
> + xa_store(&ice_handles, phandle, ERR_PTR(err), GFP_KERNEL);
> + return err;
> + }
> +
> + /*
> + * The OPP table is optional. devm_pm_opp_of_add_table() returns
> + * -ENODEV when no OPP table is present in DT, which is not treated
> + * as an error. Therefore, track successful OPP registration only
> + * when err is not -ENODEV.
> + */
> + if (err == -ENODEV)
> + dev_dbg(&pdev->dev, "ICE OPP table is not registered, please update your DT\n");
> + else
> + engine->has_opp = true;
[Severity: Medium]
Does qcom_ice_probe() fail with -EOPNOTSUPP when CONFIG_PM_OPP is
disabled?
QCOM_INLINE_CRYPTO_ENGINE does not select or depend on PM_OPP. When
CONFIG_PM_OPP is disabled, the stubs for devm_pm_opp_set_clkname() and
devm_pm_opp_of_add_table() in include/linux/pm_opp.h both return
-EOPNOTSUPP. Because the error checks only allow -ENOENT and -ENODEV,
qcom_ice_probe() stores ERR_PTR(-EOPNOTSUPP) in ice_handles and fails,
preventing ufs-qcom and sdhci-msm from using inline crypto. Also, if
-EOPNOTSUPP is ignored above, the final check needs to test !err before
setting engine->has_opp = true so it is not set when CONFIG_PM_OPP is
disabled.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261113-enable-ice-clock-scaling-v13-0-258dc817bd63@oss.qualcomm.com?part=1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v13 2/6] ufs: host: Add ICE clock scaling during UFS clock changes
2026-11-12 22:38 [PATCH v13 0/6] Enable ICE clock scaling Abhinaba Rakshit
2026-11-12 22:38 ` [PATCH v13 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE Abhinaba Rakshit
@ 2026-11-12 22:38 ` Abhinaba Rakshit
2026-11-12 22:56 ` sashiko-bot
2026-11-12 22:38 ` [PATCH v13 3/6] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Abhinaba Rakshit
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Abhinaba Rakshit @ 2026-11-12 22:38 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-crypto, linux-kernel, linux-scsi, linux-mmc,
devicetree, Abhinaba Rakshit, Abel Vesa, Martin K. Petersen
Implement ICE (Inline Crypto Engine) clock scaling in sync with
UFS controller clock scaling. This ensures that the ICE operates at
an appropriate frequency when the UFS clocks are scaled up or down,
improving performance and maintaining stability for crypto operations.
For scale_up operation ensure to pass ~round_ceil (round_floor)
and vice-versa for scale_down operations.
In case of OPP scaling is not supported by ICE, ensure to not prevent
devfreq for UFS, as ICE OPP-table is optional.
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Acked-by: Martin K. Petersen <martin.petersen@oracle.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 6afb8498b8c267d0bbbdb1e14f37fd305c71fddc..5019803a6aba4f649972e2ecdafda1e9e38fe2ba 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -307,6 +307,15 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile,
return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key);
}
+static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
+ bool round_ceil)
+{
+ if (host->hba->caps & UFSHCD_CAP_CRYPTO)
+ return qcom_ice_scale_clk(host->ice, target_freq, round_ceil);
+
+ return 0;
+}
+
static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
.keyslot_program = ufs_qcom_ice_keyslot_program,
.keyslot_evict = ufs_qcom_ice_keyslot_evict,
@@ -341,6 +350,12 @@ static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
{
}
+static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
+ bool round_ceil)
+{
+ return 0;
+}
+
#endif
static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
@@ -1987,6 +2002,12 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
return err;
}
+ err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up);
+ if (err && err != -EOPNOTSUPP) {
+ ufshcd_uic_hibern8_exit(hba);
+ return err;
+ }
+
ufs_qcom_icc_update_bw(host);
ufshcd_uic_hibern8_exit(hba);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v13 2/6] ufs: host: Add ICE clock scaling during UFS clock changes
2026-11-12 22:38 ` [PATCH v13 2/6] ufs: host: Add ICE clock scaling during UFS clock changes Abhinaba Rakshit
@ 2026-11-12 22:56 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-11-12 22:56 UTC (permalink / raw)
To: Abhinaba Rakshit, Abel Vesa, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Adrian Hunter, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-crypto, linux-scsi, devicetree, Abel Vesa
Thank you for your contribution! Sashiko AI review found 3 potential
issues to consider:
- [High] ufs: ufs-qcom: inverted ICE clock rounding in
ufs_qcom_clk_scale_notify()
- [Medium] ufs: ufs-qcom: ICE clock scaling skipped when HBA is inactive
on reset
- [Medium] ufs: ufs-qcom: broken clock rollback on error in
ufs_qcom_clk_scale_notify()
--
commit 1e3a20c6222c6ad3d20e8e58d3a121e1fa7488c1
Author: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
ufs: host: Add ICE clock scaling during UFS clock changes
This commit adds Inline Crypto Engine (ICE) clock scaling to
ufs_qcom_clk_scale_notify() so the ICE clock scales alongside the UFS
controller clock.
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 6afb8498b8c26..5019803a6aba4 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
[ ... ]
> @@ -1987,6 +2002,12 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
> return err;
> }
>
> + err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up);
> + if (err && err != -EOPNOTSUPP) {
> + ufshcd_uic_hibern8_exit(hba);
> + return err;
> + }
> +
> ufs_qcom_icc_update_bw(host);
> ufshcd_uic_hibern8_exit(hba);
> }
[Severity: High]
Is the round_ceil argument (!scale_up) inverted in this
ufs_qcom_ice_scale_clk() call?
qcom_ice_scale_clk() calls dev_pm_opp_find_freq_ceil() when round_ceil
is true and dev_pm_opp_find_freq_floor() when round_ceil is false, while
target_freq is the concrete UFS core_clk frequency in Hz. On SoCs where
ICE OPP rates are higher than the corresponding UFS core_clk rates for
the same voltage corners (for example on QCS8300 or SM8550, where UFS
core_clk OPPs are 75/150/300 MHz and ICE OPPs are 100/201.5/403 MHz),
passing round_ceil = false during scale_up rounds 300 MHz down to
201.5 MHz, so the ICE clock never reaches its 403 MHz nominal OPP.
Scaling up to an intermediate OPP such as 150 MHz also picks 100 MHz
while scaling down to 150 MHz picks 201.5 MHz, and scaling up to a
frequency below the minimum ICE OPP (such as 75 MHz on SM8550) fails with
-ERANGE and aborts UFS clock scaling.
[Severity: Medium]
Does placing ufs_qcom_ice_scale_clk() after the !ufshcd_is_hba_active()
early return in ufs_qcom_clk_scale_notify() skip ICE clock scaling during
host reset and restore?
ufshcd_host_reset_and_restore() stops the HBA before scaling the clocks
back to maximum:
drivers/ufs/core/ufshcd.c:ufshcd_host_reset_and_restore() {
...
ufshcd_hba_stop(hba);
hba->silence_err_logs = true;
ufshcd_complete_requests(hba, true);
hba->silence_err_logs = false;
/* scale up clocks to max frequency before full reinitialization */
if (ufshcd_is_clkscaling_supported(hba))
ufshcd_scale_clks(hba, ULONG_MAX, true);
...
}
Because ufshcd_is_hba_active(hba) is false at that point,
ufs_qcom_clk_scale_notify() returns 0 immediately to avoid sending UIC
Hibern8 commands. Unlike the UFS timers, UniPro clock control and
interconnect bandwidth, the ICE clock is not reconfigured during the
subsequent ufshcd_hba_enable() and link startup, leaving the ICE clock at
its previous lower OPP while the UFS controller runs at maximum
frequency.
[Severity: Medium]
If ufs_qcom_ice_scale_clk() returns an error here, does the error path
leave the UFS timer and UniPro clock control registers out of sync with
the reverted clock rate?
By the time ufs_qcom_ice_scale_clk() runs in POST_CHANGE,
ufs_qcom_clk_scale_up_pre_change() or
ufs_qcom_clk_scale_down_post_change() has already programmed
REG_UFS_SYS1CLK_1US, DME_VS_CORE_CLK_CTRL and PA_VS_CORE_CLK_40NS_CYCLES
for target_freq. On error, ufs_qcom_clk_scale_notify() exits Hibern8 and
returns err, causing ufshcd_scale_clks() to roll the UFS clocks back to
previous_freq while the link is active and without restoring those
hardware registers to match previous_freq.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261113-enable-ice-clock-scaling-v13-0-258dc817bd63@oss.qualcomm.com?part=2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v13 3/6] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
2026-11-12 22:38 [PATCH v13 0/6] Enable ICE clock scaling Abhinaba Rakshit
2026-11-12 22:38 ` [PATCH v13 1/6] soc: qcom: ice: Add OPP-based clock scaling support for ICE Abhinaba Rakshit
2026-11-12 22:38 ` [PATCH v13 2/6] ufs: host: Add ICE clock scaling during UFS clock changes Abhinaba Rakshit
@ 2026-11-12 22:38 ` Abhinaba Rakshit
2026-11-12 23:04 ` sashiko-bot
2026-11-12 22:38 ` [PATCH v13 4/6] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE SDHC nodes Abhinaba Rakshit
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Abhinaba Rakshit @ 2026-11-12 22:38 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-crypto, linux-kernel, linux-scsi, linux-mmc,
devicetree, Abhinaba Rakshit, Konrad Dybcio, Abel Vesa
MMC controller lacks a clock scaling mechanism, unlike the UFS
controller. By default, the MMC controller is set to TURBO mode
during probe, but the ICE clock remains at XO frequency,
leading to read/write performance degradation on eMMC.
To address this, set the ICE clock to TURBO during sdhci_msm_ice_init
to align it with the controller clock. This ensures consistent
performance and avoids mismatches between the controller
and ICE clock frequencies.
For platforms where ICE is represented as a separate device,
use the OPP framework to vote for TURBO mode, maintaining
proper voltage and power domain constraints.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/mmc/host/sdhci-msm.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 32b1bcba47d6b75578f01d8de6ee9beea3b1e080..652c5cfc87bcc3c59b845b9e2fd785bcba197fa0 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1902,6 +1902,16 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
+static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host,
+ unsigned long target_freq,
+ bool round_ceil)
+{
+ if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
+ return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil);
+
+ return 0;
+}
+
static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
struct cqhci_host *cq_host)
{
@@ -1960,6 +1970,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
mmc->caps2 |= MMC_CAP2_CRYPTO;
mmc->caps2 |= MMC_CAP2_CRYPTO_NO_REPROG;
+
+ err = sdhci_msm_ice_scale_clk(msm_host, ULONG_MAX, false);
+ if (err && err != -EOPNOTSUPP)
+ dev_warn(dev, "Unable to boost ICE clock to TURBO\n");
+
return 0;
}
@@ -2160,6 +2175,13 @@ sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
static inline void sdhci_msm_ice_restore(struct sdhci_host *host)
{
}
+
+static inline int
+sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
+ bool round_ceil)
+{
+ return 0;
+}
#endif /* !CONFIG_MMC_CRYPTO */
/*****************************************************************************\
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v13 3/6] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
2026-11-12 22:38 ` [PATCH v13 3/6] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Abhinaba Rakshit
@ 2026-11-12 23:04 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-11-12 23:04 UTC (permalink / raw)
To: Abhinaba Rakshit, Abel Vesa, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, James E.J. Bottomley, Martin K. Petersen,
Adrian Hunter, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-crypto, linux-scsi, devicetree, Konrad Dybcio, Abel Vesa
Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [Medium] mmc: sdhci-msm: unreleased ICE OPP vote in
sdhci_msm_ice_init()
- [Low] mmc: sdhci-msm: unused !CONFIG_MMC_CRYPTO stub for
sdhci_msm_ice_scale_clk()
--
commit a5619e66f640a05fe76cc365285b6b0e44623197
Author: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
This commit scales the Inline Crypto Engine (ICE) clock to its maximum
frequency via qcom_ice_scale_clk() during sdhci_msm_ice_init() so that it
matches the MMC controller clock rate.
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 32b1bcba47d6b..652c5cfc87bcc 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -1902,6 +1902,16 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>
> static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
>
> +static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host,
> + unsigned long target_freq,
> + bool round_ceil)
> +{
> + if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
> + return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil);
> +
> + return 0;
> +}
> +
> static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
> struct cqhci_host *cq_host)
> {
> @@ -1960,6 +1970,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
>
> mmc->caps2 |= MMC_CAP2_CRYPTO;
> mmc->caps2 |= MMC_CAP2_CRYPTO_NO_REPROG;
> +
> + err = sdhci_msm_ice_scale_clk(msm_host, ULONG_MAX, false);
> + if (err && err != -EOPNOTSUPP)
> + dev_warn(dev, "Unable to boost ICE clock to TURBO\n");
> +
> return 0;
> }
[Severity: Medium]
As reported by Ulf Hansson on v12 [1], does this leave the OPP and
power-domain performance vote on msm_host->ice->dev permanently asserted?
On platforms with a standalone sdhc_ice device and an OPP table with
required-opps (such as sc7280 and qcs8300), qcom_ice_scale_clk() calls
dev_pm_opp_set_rate(ice->dev, ...), which votes on the shared CX power
domain. Because qcom_ice_probe() does not enable runtime PM on ice->dev,
genpd never drops this performance state automatically.
In sdhci_msm_runtime_suspend(), the driver drops the controller's own vote
with dev_pm_opp_set_rate(dev, 0), but sdhci_msm_ice_suspend() only calls
qcom_ice_suspend() to gate the ICE clocks. The vote on ice->dev is also
left active if cqhci_init() or __sdhci_add_host() fails after
sdhci_msm_ice_init(), or when sdhci_msm_remove() unbinds the driver,
keeping the shared CX rail elevated during idle and system suspend.
> @@ -2160,6 +2175,13 @@ sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
> static inline void sdhci_msm_ice_restore(struct sdhci_host *host)
> {
> }
> +
> +static inline int
> +sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
> + bool round_ceil)
> +{
> + return 0;
> +}
> #endif /* !CONFIG_MMC_CRYPTO */
[Severity: Low]
This isn't a bug, but sdhci_msm_ice_scale_clk() has no callers outside the
CONFIG_MMC_CRYPTO block. Its only caller is sdhci_msm_ice_init() right
after setting mmc->caps2 |= MMC_CAP2_CRYPTO, so this stub is unused and
sdhci_msm_ice_init() could call qcom_ice_scale_clk() directly.
[1] https://lore.kernel.org/r/CAPx+jO_Ltc6Q+VdUgOs81azTiM5Vx12GH1z+CXt6NW=M601THQ@mail.gmail.com
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261113-enable-ice-clock-scaling-v13-0-258dc817bd63@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v13 4/6] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE SDHC nodes
2026-11-12 22:38 [PATCH v13 0/6] Enable ICE clock scaling Abhinaba Rakshit
` (2 preceding siblings ...)
2026-11-12 22:38 ` [PATCH v13 3/6] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Abhinaba Rakshit
@ 2026-11-12 22:38 ` Abhinaba Rakshit
2026-11-12 22:38 ` [PATCH v13 5/6] arm64: dts: qcom: monaco: " Abhinaba Rakshit
2026-11-12 22:38 ` [PATCH v13 6/6] arm64: dts: qcom: lemans: Add OPP-table for ICE UFS device node Abhinaba Rakshit
5 siblings, 0 replies; 10+ messages in thread
From: Abhinaba Rakshit @ 2026-11-12 22:38 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-crypto, linux-kernel, linux-scsi, linux-mmc,
devicetree, Abhinaba Rakshit, Konrad Dybcio
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.
Add OPP-table for ICE UFS and ICE SDHC device nodes for Kodiak
platform.
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 42 ++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 10e9a5279ed60cea1514097354b8f0f59ffca2fc..397764d78dba579fe95654deb7b01ae3b1735f89 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1100,6 +1100,27 @@ sdhc_ice: crypto@7c8000 {
clock-names = "core",
"iface";
power-domains = <&rpmhpd SC7280_CX>;
+
+ operating-points-v2 = <&sdhc_ice_opp_table>;
+
+ sdhc_ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
};
gpi_dma0: dma-controller@900000 {
@@ -2608,6 +2629,27 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
cryptobam: dma-controller@1dc4000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v13 5/6] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE SDHC nodes
2026-11-12 22:38 [PATCH v13 0/6] Enable ICE clock scaling Abhinaba Rakshit
` (3 preceding siblings ...)
2026-11-12 22:38 ` [PATCH v13 4/6] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE SDHC nodes Abhinaba Rakshit
@ 2026-11-12 22:38 ` Abhinaba Rakshit
2026-11-12 22:38 ` [PATCH v13 6/6] arm64: dts: qcom: lemans: Add OPP-table for ICE UFS device node Abhinaba Rakshit
5 siblings, 0 replies; 10+ messages in thread
From: Abhinaba Rakshit @ 2026-11-12 22:38 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-crypto, linux-kernel, linux-scsi, linux-mmc,
devicetree, Abhinaba Rakshit, Abel Vesa
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.
Add OPP-table for ICE UFS and ICE SDHC device nodes for Monaco
platform.
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 3541313a79bf47fe27499f6dc370cb778d780a08..d7e2038854b0bdcc91d65d5712290c690e772258 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2725,6 +2725,27 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-201600000 {
+ opp-hz = /bits/ 64 <201600000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
crypto: crypto@1dfa000 {
@@ -4890,6 +4911,22 @@ sdhc_ice: crypto@87c8000 {
clock-names = "core",
"iface";
power-domains = <&rpmhpd RPMHPD_CX>;
+
+ operating-points-v2 = <&sdhc_ice_opp_table>;
+
+ sdhc_ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
usb_1_hsphy: phy@8904000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v13 6/6] arm64: dts: qcom: lemans: Add OPP-table for ICE UFS device node
2026-11-12 22:38 [PATCH v13 0/6] Enable ICE clock scaling Abhinaba Rakshit
` (4 preceding siblings ...)
2026-11-12 22:38 ` [PATCH v13 5/6] arm64: dts: qcom: monaco: " Abhinaba Rakshit
@ 2026-11-12 22:38 ` Abhinaba Rakshit
5 siblings, 0 replies; 10+ messages in thread
From: Abhinaba Rakshit @ 2026-11-12 22:38 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-crypto, linux-kernel, linux-scsi, linux-mmc,
devicetree, Abhinaba Rakshit, Abel Vesa
Qualcomm Inline Crypto Engine (ICE) platform driver now supports
an optional OPP-table.
Add OPP-table for ICE UFS device nodes for LeMans platform.
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-embedded.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
index 0be39bb9de1e1cdbb7d67a992172861a5a10a05a..a80fd8f96427488c20205c5ad798413aeb53964b 100644
--- a/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-embedded.dtsi
@@ -1840,6 +1840,32 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
lpass_ag_noc: interconnect@3c40000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread