Re: [PATCH 3/3] arm64: dts: qcom: sm8750: describe the second MDSS block reset

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: sm8750: unattached
  DISP_CC_MDSS_CORE_INT2_BCR reset on mdss
--

commit 048c5dc3c561337c4cf2b84db1d42eb1d5cdd378
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

arm64: dts: qcom: sm8750: describe the second MDSS block reset

This commit adds DISP_CC_MDSS_CORE_INT2_BCR as a second reset to the
SM8750 MDSS device tree node.

> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index cf947acc57602..0f3e649787315 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3359,7 +3359,8 @@ mdss: display-subsystem@ae00000 {
>  				 <&gcc GCC_DISP_HF_AXI_CLK>,
>  				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
>  
> -			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>,
> +				 <&dispcc DISP_CC_MDSS_CORE_INT2_BCR>;

[Severity: Medium]
Should the mdss node assert and deassert DISP_CC_MDSS_CORE_INT2_BCR when its
corresponding power domain and clocks are not attached to the device?

In drivers/clk/qcom/dispcc-sm8750.c, DISP_CC_MDSS_CORE_INT2_BCR at 0xa000 is
the block reset for a separate secondary domain with its own power domain
(MDSS_INT2_GDSC at 0xb000) and clock branches (disp_cc_mdss_mdp1_clk,
disp_cc_mdss_mdp_lut1_clk, disp_cc_mdss_vsync1_clk, and
disp_cc_mdss_ahb1_clk).  The mdss and mdss_mdp nodes in sm8750.dtsi only
attach MDSS_GDSC and the primary MDP0 clocks, so msm_mdss_reset() toggles a
reset for a domain whose GDSC and clocks are neither attached nor enabled.

In addition, while the commit message notes that DISP_CC_MDSS_CORE_INT2_BCR
belongs to the mdss_int2_gdsc domain and that this two-reset configuration
has not been tested on hardware, the companion binding in
Documentation/devicetree/bindings/display/msm/mdss-common.yaml still
describes the second reset as an MDSS core INT2 interrupt controller reset.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261113155606.1677313-1-xiaqinghuan@mail.ustc.edu.cn?part=3