Re: [PATCH 3/3] arm64: dts: qcom: sm8750: describe the second MDSS block reset

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: sm8750: unattached INT2 domain reset on
  mdss
--

commit b3b8b6c811f21fdd572edc7ec2e32709cdaa973b
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

arm64: dts: qcom: sm8750: describe the second MDSS block reset

This commit adds DISP_CC_MDSS_CORE_INT2_BCR to the resets property of the
mdss display-subsystem node in the SM8750 device tree.

> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index cf947acc57602..0f3e649787315 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3359,7 +3359,8 @@ mdss: display-subsystem@ae00000 {
>  				 <&gcc GCC_DISP_HF_AXI_CLK>,
>  				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
>  
> -			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>,
> +				 <&dispcc DISP_CC_MDSS_CORE_INT2_BCR>;

[Severity: Medium]
Should the mdss node assert DISP_CC_MDSS_CORE_INT2_BCR when it does not
attach the corresponding MDSS_INT2_GDSC power domain or clocks?

In drivers/clk/qcom/dispcc-sm8750.c, DISP_CC_MDSS_CORE_INT2_BCR (at 0xa000)
is the block reset for the secondary MDSS_CORE_INT2 domain governed by
mdss_int2_gdsc (at 0xb000) and the disp_cc_mdss_*1_clk branches.  Here,
mdss only attaches MDSS_GDSC and the primary MDSS_CORE clocks, so
mdss_probe() -> msm_mdss_init() -> msm_mdss_reset() will reset an
unattached power and clock domain.

In addition, commit "dt-bindings: display: msm: mdss-common: describe
additional block resets" in this series still documents this second reset
entry in Documentation/devicetree/bindings/display/msm/mdss-common.yaml as
"MDSS core INT2 interrupt controller reset", which contradicts the commit
message here describing it as a separate GDSC and clock domain.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261113155635.1677541-1-xiaqinghuan@mail.ustc.edu.cn?part=3