Re: [PATCH 2/2] pinctrl: qcom: Add Molokai TLMM driver

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential
issues to consider:
- [High] pinctrl: qcom: molokai uses MSM_PIN_FUNCTION() for egpio
- [High] pinctrl: qcom: molokai PINGROUP() omits intr_target_width = 4
--

commit e5d14e99015da685768f438aabdb5849901661b6
Author: Venkat Yadlapati <venkat.yadlapati@yahoo.com>

pinctrl: qcom: Add Molokai TLMM driver

This commit adds the pinctrl, pinmux, pinconf, and gpiolib driver for the
TLMM block on the Qualcomm Molokai (SM8845) SoC.

> diff --git a/drivers/pinctrl/qcom/pinctrl-molokai.c b/drivers/pinctrl/qcom/pinctrl-molokai.c
> new file mode 100644
> index 0000000000000..80763dce895be
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-molokai.c
> @@ -0,0 +1,1679 @@
[ ... ]
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)	\
> +	{					        \
> +		.grp = PINCTRL_PINGROUP("gpio" #id,	\
> +			gpio##id##_pins,		\
> +			ARRAY_SIZE(gpio##id##_pins)),	\
> +		.funcs = (int[]){			\
> +			msm_mux_gpio, /* gpio mode */	\
> +			msm_mux_##f1,			\
> +			msm_mux_##f2,			\
> +			msm_mux_##f3,			\
> +			msm_mux_##f4,			\
> +			msm_mux_##f5,			\
> +			msm_mux_##f6,			\
> +			msm_mux_##f7,			\
> +			msm_mux_##f8,			\
> +			msm_mux_##f9,			\
> +			msm_mux_##f10,			\
> +			msm_mux_##f11 /* egpio mode */	\
> +		},					\
> +		.nfuncs = 12,				\
> +		.ctl_reg = REG_SIZE * id,		\
> +		.io_reg = 0x4 + REG_SIZE * id,		\
> +		.intr_cfg_reg = 0x8 + REG_SIZE * id,	\
> +		.intr_status_reg = 0xc + REG_SIZE * id,	\
> +		.mux_bit = 2,			\
> +		.pull_bit = 0,			\
> +		.drv_bit = 6,			\
> +		.i2c_pull_bit = 13,		\
> +		.egpio_enable = 12,		\
> +		.egpio_present = 11,		\
> +		.oe_bit = 9,			\
> +		.in_bit = 0,			\
> +		.out_bit = 1,			\
> +		.intr_enable_bit = 0,		\
> +		.intr_status_bit = 0,		\
> +		.intr_wakeup_present_bit = 6,	\
> +		.intr_wakeup_enable_bit = 7,	\
> +		.intr_target_bit = 8,		\
> +		.intr_target_kpss_val = 3,	\
> +		.intr_raw_status_bit = 4,	\
> +		.intr_polarity_bit = 1,		\
> +		.intr_detection_bit = 2,	\
> +		.intr_detection_width = 2,	\
> +	}

[Severity: High]
Should PINGROUP() set .intr_target_width = 4?

Without intr_target_width, msm_gpio_irq_set_type() defaults to a 3-bit mask
(GENMASK(2, 0)).  In this TLMM register layout, TARGET_PROC occupies bits
11:8 and resets to 0xf (NONE), so clearing only bits 10:8 leaves bit 11 set
and writes 0xb instead of 0x3, misrouting all GPIO interrupts handled via
the TLMM summary interrupt path (the same issue fixed in commits
68ab4a6a84b9 ("pinctrl: qcom: nord: fix GPIO interrupt target width") and
1e7b04c12c07 ("pinctrl: qcom: shikra: Fix intr_target_width for summary
interrupt routing")).

[ ... ]

> +static const struct pinfunction molokai_functions[] = {
> +	MSM_GPIO_PIN_FUNCTION(gpio),
[ ... ]
> +	MSM_PIN_FUNCTION(dp_hot),
> +	MSM_PIN_FUNCTION(egpio),
> +	MSM_PIN_FUNCTION(gcc_gp1),

[Severity: High]
Should egpio in molokai_functions[] use MSM_GPIO_PIN_FUNCTION(egpio) instead
of MSM_PIN_FUNCTION(egpio)?

msm_pinmux_ops sets .strict = true and .function_is_gpio =
pinmux_generic_function_is_gpio.  Because MSM_PIN_FUNCTION() does not set
PINFUNCTION_FLAG_GPIO, pin_request() rejects any GPIO request on a pin muxed
to egpio with -EINVAL (as fixed across other Qualcomm TLMM drivers in
commits 480dc1952404 ("pinctrl: qcom: mark the `gpio` and `egpio` pins
function as non-strict functions") and e73fda2dcb0b ("pinctrl: qcom: glymur:
Fix the gpio and egpio pin functions")).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261116-molokai-tlmm-v1-0-3ba4840002cb@yahoo.com?part=2