* [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe @ 2023-04-28 19:06 Evan Green 2023-04-28 19:06 ` [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Evan Green 2023-04-29 12:34 ` [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Andrew Jones 0 siblings, 2 replies; 6+ messages in thread From: Evan Green @ 2023-04-28 19:06 UTC (permalink / raw) To: Palmer Dabbelt Cc: Evan Green, Albert Ou, Andrew Bresticker, Andrew Jones, Anup Patel, Celeste Liu, Conor Dooley, Dao Lu, Heiko Stuebner, Jisheng Zhang, Jonathan Corbet, Palmer Dabbelt, Paul Walmsley, Sunil V L, linux-doc, linux-kernel, linux-riscv This change detects the presence of Zba and Zbb extensions and exports them per-hart to userspace via the hwprobe mechanism. Glibc can then use these in setting up hwcaps-based library search paths. There's a little bit of extra housekeeping here: the first change adds Zba to the set of extensions the kernel recognizes, and the second change starts tracking ISA features per-hart (in addition to the ANDed mask of features across all harts which the kernel uses to make decisions). Now that we track the ISA information per-hart, we could even fix up /proc/cpuinfo to accurately report extension per-hart, though I've left that out of this series for now. Evan Green (3): RISC-V: Add Zba extension probing RISC-V: Track ISA extensions per hart RISC-V: hwprobe: Expose Zba and Zbb Documentation/riscv/hwprobe.rst | 7 +++++ arch/riscv/include/asm/cpufeature.h | 10 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 19 ++++++++---- arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- 7 files changed, 70 insertions(+), 13 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb 2023-04-28 19:06 [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Evan Green @ 2023-04-28 19:06 ` Evan Green 2023-04-29 13:40 ` Conor Dooley 2023-04-29 12:34 ` [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Andrew Jones 1 sibling, 1 reply; 6+ messages in thread From: Evan Green @ 2023-04-28 19:06 UTC (permalink / raw) To: Palmer Dabbelt Cc: Evan Green, Albert Ou, Andrew Bresticker, Andrew Jones, Celeste Liu, Conor Dooley, Heiko Stuebner, Jonathan Corbet, Palmer Dabbelt, Paul Walmsley, linux-doc, linux-kernel, linux-riscv Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These are accurately reported per CPU. Signed-off-by: Evan Green <evan@rivosinc.com> --- Documentation/riscv/hwprobe.rst | 7 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- 3 files changed, 45 insertions(+), 7 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f0dd62dcb5d..21f444a38359 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,13 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. + + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 8d745a4ad8a2..ef3b060d4e8d 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..adfcb6b64db7 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, pair->value = id; } +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + int cpu; + u64 missing = 0; + + pair->value = 0; + if (has_fpu()) + pair->value |= RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |= RISCV_HWPROBE_IMA_C; + + /* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + */ + for_each_cpu(cpu, cpus) { + struct riscv_isainfo *isainfo = &hart_isa[cpu]; + + if (riscv_isa_extension_available(isainfo->isa, ZBA)) + pair->value |= RISCV_HWPROBE_EXT_ZBA; + else + missing |= RISCV_HWPROBE_EXT_ZBA; + + if (riscv_isa_extension_available(isainfo->isa, ZBB)) + pair->value |= RISCV_HWPROBE_EXT_ZBB; + else + missing |= RISCV_HWPROBE_EXT_ZBB; + } + + /* Now turn off reporting features if any CPU is missing it. */ + pair->value &= ~missing; +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, break; case RISCV_HWPROBE_KEY_IMA_EXT_0: - pair->value = 0; - if (has_fpu()) - pair->value |= RISCV_HWPROBE_IMA_FD; - - if (riscv_isa_extension_available(NULL, c)) - pair->value |= RISCV_HWPROBE_IMA_C; - + hwprobe_isa_ext0(pair, cpus); break; case RISCV_HWPROBE_KEY_CPUPERF_0: -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb 2023-04-28 19:06 ` [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Evan Green @ 2023-04-29 13:40 ` Conor Dooley 2023-04-29 20:07 ` Palmer Dabbelt 0 siblings, 1 reply; 6+ messages in thread From: Conor Dooley @ 2023-04-29 13:40 UTC (permalink / raw) To: Evan Green Cc: Palmer Dabbelt, Albert Ou, Andrew Bresticker, Andrew Jones, Celeste Liu, Conor Dooley, Heiko Stuebner, Jonathan Corbet, Palmer Dabbelt, Paul Walmsley, linux-doc, linux-kernel, linux-riscv [-- Attachment #1: Type: text/plain, Size: 4015 bytes --] On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote: > Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These > are accurately reported per CPU. > > Signed-off-by: Evan Green <evan@rivosinc.com> > > --- > > Documentation/riscv/hwprobe.rst | 7 +++++ > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- > 3 files changed, 45 insertions(+), 7 deletions(-) > > diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > index 9f0dd62dcb5d..21f444a38359 100644 > --- a/Documentation/riscv/hwprobe.rst > +++ b/Documentation/riscv/hwprobe.rst > @@ -64,6 +64,13 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > by version 2.2 of the RISC-V ISA manual. > > + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is > + supported, as defined in version 1.0 of the Bit-Manipulation ISA > + extensions. > + > + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below, so I assume this is a copy-paste mistake. Also, s/supporte/supported. Otherwise, looks fine. Cheers, Conor. > + in version 1.0 of the Bit-Manipulation ISA extensions. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 8d745a4ad8a2..ef3b060d4e8d 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -25,6 +25,8 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > #define RISCV_HWPROBE_IMA_FD (1 << 0) > #define RISCV_HWPROBE_IMA_C (1 << 1) > +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) > +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 5db29683ebee..adfcb6b64db7 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, > pair->value = id; > } > > +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > + const struct cpumask *cpus) > +{ > + int cpu; > + u64 missing = 0; > + > + pair->value = 0; > + if (has_fpu()) > + pair->value |= RISCV_HWPROBE_IMA_FD; > + > + if (riscv_isa_extension_available(NULL, c)) > + pair->value |= RISCV_HWPROBE_IMA_C; > + > + /* > + * Loop through and record extensions that 1) anyone has, and 2) anyone > + * doesn't have. > + */ > + for_each_cpu(cpu, cpus) { > + struct riscv_isainfo *isainfo = &hart_isa[cpu]; > + > + if (riscv_isa_extension_available(isainfo->isa, ZBA)) > + pair->value |= RISCV_HWPROBE_EXT_ZBA; > + else > + missing |= RISCV_HWPROBE_EXT_ZBA; > + > + if (riscv_isa_extension_available(isainfo->isa, ZBB)) > + pair->value |= RISCV_HWPROBE_EXT_ZBB; > + else > + missing |= RISCV_HWPROBE_EXT_ZBB; > + } > + > + /* Now turn off reporting features if any CPU is missing it. */ > + pair->value &= ~missing; > +} > + > static u64 hwprobe_misaligned(const struct cpumask *cpus) > { > int cpu; > @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > break; > > case RISCV_HWPROBE_KEY_IMA_EXT_0: > - pair->value = 0; > - if (has_fpu()) > - pair->value |= RISCV_HWPROBE_IMA_FD; > - > - if (riscv_isa_extension_available(NULL, c)) > - pair->value |= RISCV_HWPROBE_IMA_C; > - > + hwprobe_isa_ext0(pair, cpus); > break; > > case RISCV_HWPROBE_KEY_CPUPERF_0: > -- > 2.25.1 > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb 2023-04-29 13:40 ` Conor Dooley @ 2023-04-29 20:07 ` Palmer Dabbelt 2023-05-01 15:33 ` Evan Green 0 siblings, 1 reply; 6+ messages in thread From: Palmer Dabbelt @ 2023-04-29 20:07 UTC (permalink / raw) To: Conor Dooley Cc: Evan Green, aou, abrestic, ajones, coelacanthus, Conor Dooley, heiko.stuebner, corbet, Paul Walmsley, linux-doc, linux-kernel, linux-riscv On Sat, 29 Apr 2023 06:40:51 PDT (-0700), Conor Dooley wrote: > On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote: >> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These >> are accurately reported per CPU. >> >> Signed-off-by: Evan Green <evan@rivosinc.com> >> >> --- >> >> Documentation/riscv/hwprobe.rst | 7 +++++ >> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ >> arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- >> 3 files changed, 45 insertions(+), 7 deletions(-) >> >> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst >> index 9f0dd62dcb5d..21f444a38359 100644 >> --- a/Documentation/riscv/hwprobe.rst >> +++ b/Documentation/riscv/hwprobe.rst >> @@ -64,6 +64,13 @@ The following keys are defined: >> * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined >> by version 2.2 of the RISC-V ISA manual. >> >> + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is >> + supported, as defined in version 1.0 of the Bit-Manipulation ISA >> + extensions. >> + >> + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined > > Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below, > so I assume this is a copy-paste mistake. Looks like it. Either way this was too late for the current merge window, so no big deal. > > Also, s/supporte/supported. > > Otherwise, looks fine. > Cheers, > Conor. > >> + in version 1.0 of the Bit-Manipulation ISA extensions. >> + >> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance >> information about the selected set of processors. >> >> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h >> index 8d745a4ad8a2..ef3b060d4e8d 100644 >> --- a/arch/riscv/include/uapi/asm/hwprobe.h >> +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> @@ -25,6 +25,8 @@ struct riscv_hwprobe { >> #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 >> #define RISCV_HWPROBE_IMA_FD (1 << 0) >> #define RISCV_HWPROBE_IMA_C (1 << 1) >> +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) >> +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) >> #define RISCV_HWPROBE_KEY_CPUPERF_0 5 >> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) >> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) >> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c >> index 5db29683ebee..adfcb6b64db7 100644 >> --- a/arch/riscv/kernel/sys_riscv.c >> +++ b/arch/riscv/kernel/sys_riscv.c >> @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, >> pair->value = id; >> } >> >> +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, >> + const struct cpumask *cpus) >> +{ >> + int cpu; >> + u64 missing = 0; >> + >> + pair->value = 0; >> + if (has_fpu()) >> + pair->value |= RISCV_HWPROBE_IMA_FD; >> + >> + if (riscv_isa_extension_available(NULL, c)) >> + pair->value |= RISCV_HWPROBE_IMA_C; >> + >> + /* >> + * Loop through and record extensions that 1) anyone has, and 2) anyone >> + * doesn't have. >> + */ >> + for_each_cpu(cpu, cpus) { >> + struct riscv_isainfo *isainfo = &hart_isa[cpu]; >> + >> + if (riscv_isa_extension_available(isainfo->isa, ZBA)) >> + pair->value |= RISCV_HWPROBE_EXT_ZBA; >> + else >> + missing |= RISCV_HWPROBE_EXT_ZBA; >> + >> + if (riscv_isa_extension_available(isainfo->isa, ZBB)) >> + pair->value |= RISCV_HWPROBE_EXT_ZBB; >> + else >> + missing |= RISCV_HWPROBE_EXT_ZBB; >> + } >> + >> + /* Now turn off reporting features if any CPU is missing it. */ >> + pair->value &= ~missing; >> +} >> + >> static u64 hwprobe_misaligned(const struct cpumask *cpus) >> { >> int cpu; >> @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, >> break; >> >> case RISCV_HWPROBE_KEY_IMA_EXT_0: >> - pair->value = 0; >> - if (has_fpu()) >> - pair->value |= RISCV_HWPROBE_IMA_FD; >> - >> - if (riscv_isa_extension_available(NULL, c)) >> - pair->value |= RISCV_HWPROBE_IMA_C; >> - >> + hwprobe_isa_ext0(pair, cpus); >> break; >> >> case RISCV_HWPROBE_KEY_CPUPERF_0: >> -- >> 2.25.1 >> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb 2023-04-29 20:07 ` Palmer Dabbelt @ 2023-05-01 15:33 ` Evan Green 0 siblings, 0 replies; 6+ messages in thread From: Evan Green @ 2023-05-01 15:33 UTC (permalink / raw) To: Palmer Dabbelt Cc: Conor Dooley, aou, abrestic, ajones, coelacanthus, Conor Dooley, heiko.stuebner, corbet, Paul Walmsley, linux-doc, linux-kernel, linux-riscv On Sat, Apr 29, 2023 at 1:07 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Sat, 29 Apr 2023 06:40:51 PDT (-0700), Conor Dooley wrote: > > On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote: > >> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These > >> are accurately reported per CPU. > >> > >> Signed-off-by: Evan Green <evan@rivosinc.com> > >> > >> --- > >> > >> Documentation/riscv/hwprobe.rst | 7 +++++ > >> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > >> arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- > >> 3 files changed, 45 insertions(+), 7 deletions(-) > >> > >> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst > >> index 9f0dd62dcb5d..21f444a38359 100644 > >> --- a/Documentation/riscv/hwprobe.rst > >> +++ b/Documentation/riscv/hwprobe.rst > >> @@ -64,6 +64,13 @@ The following keys are defined: > >> * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined > >> by version 2.2 of the RISC-V ISA manual. > >> > >> + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is > >> + supported, as defined in version 1.0 of the Bit-Manipulation ISA > >> + extensions. > >> + > >> + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined > > > > Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below, > > so I assume this is a copy-paste mistake. > > Looks like it. Either way this was too late for the current merge > window, so no big deal. Copypasta! I'll fix it. -Evan ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe 2023-04-28 19:06 [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Evan Green 2023-04-28 19:06 ` [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Evan Green @ 2023-04-29 12:34 ` Andrew Jones 1 sibling, 0 replies; 6+ messages in thread From: Andrew Jones @ 2023-04-29 12:34 UTC (permalink / raw) To: Evan Green Cc: Palmer Dabbelt, Albert Ou, Andrew Bresticker, Anup Patel, Celeste Liu, Conor Dooley, Dao Lu, Heiko Stuebner, Jisheng Zhang, Jonathan Corbet, Palmer Dabbelt, Paul Walmsley, Sunil V L, linux-doc, linux-kernel, linux-riscv On Fri, Apr 28, 2023 at 12:06:05PM -0700, Evan Green wrote: > > This change detects the presence of Zba and Zbb extensions and exports > them per-hart to userspace via the hwprobe mechanism. Glibc can then use > these in setting up hwcaps-based library search paths. > > There's a little bit of extra housekeeping here: the first change adds > Zba to the set of extensions the kernel recognizes, and the second > change starts tracking ISA features per-hart (in addition to the ANDed > mask of features across all harts which the kernel uses to make > decisions). Now that we track the ISA information per-hart, we could > even fix up /proc/cpuinfo to accurately report extension per-hart, > though I've left that out of this series for now. > > > Evan Green (3): > RISC-V: Add Zba extension probing > RISC-V: Track ISA extensions per hart > RISC-V: hwprobe: Expose Zba and Zbb > > Documentation/riscv/hwprobe.rst | 7 +++++ > arch/riscv/include/asm/cpufeature.h | 10 +++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 19 ++++++++---- > arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- > 7 files changed, 70 insertions(+), 13 deletions(-) > > -- > 2.25.1 > For the series Reviewed-by: Andrew Jones <ajones@ventanamicro.com> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-01 15:34 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-04-28 19:06 [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Evan Green 2023-04-28 19:06 ` [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Evan Green 2023-04-29 13:40 ` Conor Dooley 2023-04-29 20:07 ` Palmer Dabbelt 2023-05-01 15:33 ` Evan Green 2023-04-29 12:34 ` [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Andrew Jones
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