From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Deepak Gupta" <debug@rivosinc.com>
Subject: [PATCH v5 13/13] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Thu, 17 Apr 2025 14:20:00 +0200 [thread overview]
Message-ID: <20250417122337.547969-14-cleger@rivosinc.com> (raw)
In-Reply-To: <20250417122337.547969-1-cleger@rivosinc.com>
SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
misaligned load/store exceptions. Save and restore it during CPU
load/put.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/kvm/vcpu.c | 3 +++
arch/riscv/kvm/vcpu_sbi_fwft.c | 36 ++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 542747e2c7f5..d98e379945c3 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -646,6 +646,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
{
void *nsh;
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
+ struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
vcpu->cpu = -1;
@@ -671,6 +672,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
csr->vstval = nacl_csr_read(nsh, CSR_VSTVAL);
csr->hvip = nacl_csr_read(nsh, CSR_HVIP);
csr->vsatp = nacl_csr_read(nsh, CSR_VSATP);
+ cfg->hedeleg = nacl_csr_read(nsh, CSR_HEDELEG);
} else {
csr->vsstatus = csr_read(CSR_VSSTATUS);
csr->vsie = csr_read(CSR_VSIE);
@@ -681,6 +683,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
csr->vstval = csr_read(CSR_VSTVAL);
csr->hvip = csr_read(CSR_HVIP);
csr->vsatp = csr_read(CSR_VSATP);
+ cfg->hedeleg = csr_read(CSR_HEDELEG);
}
}
diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c
index b0f66c7bf010..237edaefa267 100644
--- a/arch/riscv/kvm/vcpu_sbi_fwft.c
+++ b/arch/riscv/kvm/vcpu_sbi_fwft.c
@@ -14,6 +14,8 @@
#include <asm/kvm_vcpu_sbi.h>
#include <asm/kvm_vcpu_sbi_fwft.h>
+#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALIGNED))
+
struct kvm_sbi_fwft_feature {
/**
* @id: Feature ID
@@ -68,7 +70,41 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature)
return false;
}
+static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *vcpu)
+{
+ return misaligned_traps_can_delegate();
+}
+
+static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ unsigned long value)
+{
+ if (value == 1)
+ csr_set(CSR_HEDELEG, MIS_DELEG);
+ else if (value == 0)
+ csr_clear(CSR_HEDELEG, MIS_DELEG);
+ else
+ return SBI_ERR_INVALID_PARAM;
+
+ return SBI_SUCCESS;
+}
+
+static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu,
+ struct kvm_sbi_fwft_config *conf,
+ unsigned long *value)
+{
+ *value = (csr_read(CSR_HEDELEG) & MIS_DELEG) != 0;
+
+ return SBI_SUCCESS;
+}
+
static const struct kvm_sbi_fwft_feature features[] = {
+ {
+ .id = SBI_FWFT_MISALIGNED_EXC_DELEG,
+ .supported = kvm_sbi_fwft_misaligned_delegation_supported,
+ .set = kvm_sbi_fwft_set_misaligned_delegation,
+ .get = kvm_sbi_fwft_get_misaligned_delegation,
+ },
};
static struct kvm_sbi_fwft_config *
--
2.49.0
next prev parent reply other threads:[~2025-04-17 12:25 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-17 12:19 [PATCH v5 00/13] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-04-17 12:19 ` [PATCH v5 01/13] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-04-17 12:19 ` [PATCH v5 02/13] riscv: sbi: add new SBI error mappings Clément Léger
2025-04-17 12:19 ` [PATCH v5 03/13] riscv: sbi: add FWFT extension interface Clément Léger
2025-04-24 11:00 ` Andrew Jones
2025-04-24 12:32 ` Clément Léger
2025-04-24 12:57 ` Andrew Jones
2025-04-17 12:19 ` [PATCH v5 04/13] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-04-24 11:06 ` Andrew Jones
2025-04-24 12:35 ` Clément Léger
2025-04-24 12:59 ` Andrew Jones
2025-04-24 13:04 ` Clément Léger
2025-04-17 12:19 ` [PATCH v5 05/13] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-04-24 11:14 ` Andrew Jones
2025-04-17 12:19 ` [PATCH v5 06/13] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-04-17 12:19 ` [PATCH v5 07/13] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-04-17 12:19 ` [PATCH v5 08/13] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-04-17 12:19 ` [PATCH v5 09/13] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-04-17 12:19 ` [PATCH v5 10/13] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-04-17 12:19 ` [PATCH v5 11/13] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-04-17 12:19 ` [PATCH v5 12/13] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-04-17 12:20 ` Clément Léger [this message]
2025-04-24 11:34 ` [PATCH v5 13/13] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Andrew Jones
2025-04-24 12:37 ` Clément Léger
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