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From: Leo Yan <leo.yan@arm.com>
To: James Clark <james.clark@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jonathan Corbet <corbet@lwn.net>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Subject: Re: [PATCH v4 09/13] coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD()
Date: Fri, 14 Nov 2025 16:09:54 +0000	[thread overview]
Message-ID: <20251114160954.GJ3568724@e132581.arm.com> (raw)
In-Reply-To: <20251112-james-cs-syncfreq-v4-9-165ba21401dc@linaro.org>

On Wed, Nov 12, 2025 at 03:22:15PM +0000, James Clark wrote:
> Remove hard coded bitfield extractions and shifts and replace with
> ATTR_CFG_GET_FLD().
> 
> ETM4_CFG_BIT_BB was defined to give the register bit positions to
> userspace, TRCCONFIGR_BB should be used in the kernel so replace it.
> 
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 44 ++++++++++------------
>  1 file changed, 19 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 380a7840adb8..1aa0357a5ce7 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -29,6 +29,7 @@
>  #include <linux/seq_file.h>
>  #include <linux/uaccess.h>
>  #include <linux/perf_event.h>
> +#include <linux/perf/arm_pmu.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/property.h>
> @@ -789,17 +790,17 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>  		goto out;
>  
>  	/* Go from generic option to ETMv4 specifics */
> -	if (attr->config & BIT(ETM_OPT_CYCACC)) {
> +	if (ATTR_CFG_GET_FLD(attr, cycacc)) {
>  		config->cfg |= TRCCONFIGR_CCI;
>  		/* TRM: Must program this for cycacc to work */
> -		cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
> +		cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold);
>  		if (!cc_threshold)
>  			cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
>  		if (cc_threshold < drvdata->ccitmin)
>  			cc_threshold = drvdata->ccitmin;
>  		config->ccctlr = cc_threshold;
>  	}
> -	if (attr->config & BIT(ETM_OPT_TS)) {
> +	if (ATTR_CFG_GET_FLD(attr, timestamp)) {
>  		/*
>  		 * Configure timestamps to be emitted at regular intervals in
>  		 * order to correlate instructions executed on different CPUs
> @@ -819,17 +820,17 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>  	}
>  
>  	/* Only trace contextID when runs in root PID namespace */
> -	if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
> +	if (ATTR_CFG_GET_FLD(attr, contextid1) &&
>  	    task_is_in_init_pid_ns(current))
>  		/* bit[6], Context ID tracing bit */
>  		config->cfg |= TRCCONFIGR_CID;
>  
>  	/*
> -	 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
> -	 * for recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the
> -	 * kernel is not running in EL2.
> +	 * If set bit contextid2 in perf config, this asks to trace VMID for
> +	 * recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the kernel
> +	 * is not running in EL2.
>  	 */
> -	if (attr->config & BIT(ETM_OPT_CTXTID2)) {
> +	if (ATTR_CFG_GET_FLD(attr, contextid2)) {
>  		if (!is_kernel_in_hyp_mode()) {
>  			ret = -EINVAL;
>  			goto out;
> @@ -840,26 +841,22 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>  	}
>  
>  	/* return stack - enable if selected and supported */
> -	if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
> +	if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack)
>  		/* bit[12], Return stack enable bit */
>  		config->cfg |= TRCCONFIGR_RS;
>  
>  	/*
> -	 * Set any selected configuration and preset.
> -	 *
> -	 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
> -	 * in the perf attributes defined in coresight-etm-perf.c.
> -	 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
> -	 * A zero configid means no configuration active, preset = 0 means no preset selected.
> +	 * Set any selected configuration and preset. A zero configid means no
> +	 * configuration active, preset = 0 means no preset selected.
>  	 */
> -	if (attr->config2 & GENMASK_ULL(63, 32)) {
> -		cfg_hash = (u32)(attr->config2 >> 32);
> -		preset = attr->config & 0xF;
> +	if (ATTR_CFG_GET_FLD(attr, configid)) {
> +		cfg_hash = ATTR_CFG_GET_FLD(attr, configid);

Nitpick:


    cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
    if (cfg_hash) {

Then we can avoid a redundant ATTR_CFG_GET_FLD().

Otherwise:

Reviewed-by: Leo Yan <leo.yan@arm.com>

> +		preset = ATTR_CFG_GET_FLD(attr, preset);
>  		ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
>  	}
>  
>  	/* branch broadcast - enable if selected and supported */
> -	if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
> +	if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
>  		if (!drvdata->trcbb) {
>  			/*
>  			 * Missing BB support could cause silent decode errors
> @@ -868,7 +865,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
>  			ret = -EINVAL;
>  			goto out;
>  		} else {
> -			config->cfg |= BIT(ETM4_CFG_BIT_BB);
> +			config->cfg |= TRCCONFIGR_BB;
>  		}
>  	}
>  
> @@ -1104,11 +1101,8 @@ static int etm4_disable_perf(struct coresight_device *csdev,
>  		return -EINVAL;
>  
>  	etm4_disable_hw(drvdata);
> -	/*
> -	 * The config_id occupies bits 63:32 of the config2 perf event attr
> -	 * field. If this is non-zero then we will have enabled a config.
> -	 */
> -	if (attr->config2 & GENMASK_ULL(63, 32))
> +	/* If configid is non-zero then we will have enabled a config. */
> +	if (ATTR_CFG_GET_FLD(attr, configid))
>  		cscfg_csdev_disable_active_config(csdev);
>  
>  	/*
> 
> -- 
> 2.34.1
> 

  reply	other threads:[~2025-11-14 16:09 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-12 15:22 [PATCH v4 00/13] coresight: Update timestamp attribute to be an interval instead of bool James Clark
2025-11-12 15:22 ` [PATCH v4 01/13] coresight: Change syncfreq to be a u8 James Clark
2025-11-14 12:20   ` Leo Yan
2025-11-12 15:22 ` [PATCH v4 02/13] coresight: Repack struct etmv4_drvdata James Clark
2025-11-12 15:22 ` [PATCH v4 03/13] coresight: Refactor etm4_config_timestamp_event() James Clark
2025-11-12 15:22 ` [PATCH v4 04/13] coresight: Hide unused ETMv3 format attributes James Clark
2025-11-14 14:55   ` Leo Yan
2025-11-18 14:56     ` James Clark
2025-11-12 15:22 ` [PATCH v4 05/13] coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() James Clark
2025-11-14 15:03   ` Leo Yan
2025-11-12 15:22 ` [PATCH v4 06/13] coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() James Clark
2025-11-14 15:07   ` Leo Yan
2025-11-12 15:22 ` [PATCH v4 07/13] coresight: Don't reject unrecognized ETMv3 format attributes James Clark
2025-11-14 15:18   ` Leo Yan
2025-11-14 15:21     ` James Clark
2025-11-12 15:22 ` [PATCH v4 08/13] coresight: Interpret perf config with ATTR_CFG_GET_FLD() James Clark
2025-11-14 15:30   ` Leo Yan
2025-11-14 15:34     ` James Clark
2025-11-14 15:41       ` Leo Yan
2025-11-12 15:22 ` [PATCH v4 09/13] coresight: Interpret ETMv4 " James Clark
2025-11-14 16:09   ` Leo Yan [this message]
2025-11-12 15:22 ` [PATCH v4 10/13] coresight: Remove misleading definitions James Clark
2025-11-14 16:23   ` Leo Yan
2025-11-12 15:22 ` [PATCH v4 11/13] coresight: Extend width of timestamp format attribute James Clark
2025-11-14 17:10   ` Leo Yan
2025-11-12 15:22 ` [PATCH v4 12/13] coresight: Allow setting the timestamp interval James Clark
2025-11-12 15:22 ` [PATCH v4 13/13] coresight: docs: Document etm4x timestamp interval option James Clark
2025-11-14  5:02   ` Randy Dunlap
2025-11-14  9:59     ` James Clark
2025-11-14 18:05   ` Leo Yan
2025-11-18 16:15     ` James Clark

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