From: Jonathan Cameron <jic23@kernel.org>
To: Rodrigo Alencar via B4 Relay
<devnull+rodrigo.alencar.analog.com@kernel.org>
Cc: rodrigo.alencar@analog.com, linux-iio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, linux-hardening@vger.kernel.org,
Lars-Peter Clausen <lars@metafoo.de>,
Michael Hennerich <Michael.Hennerich@analog.com>,
David Lechner <dlechner@baylibre.com>,
Andy Shevchenko <andy@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Kees Cook <kees@kernel.org>,
"Gustavo A. R. Silva" <gustavoars@kernel.org>
Subject: Re: [PATCH RFC v4 06/10] iio: frequency: ad9910: add RAM mode support
Date: Sun, 17 May 2026 16:06:27 +0100 [thread overview]
Message-ID: <20260517160627.5c98ec03@jic23-huawei> (raw)
In-Reply-To: <20260508-ad9910-iio-driver-v4-6-d26bfd20ee3d@analog.com>
On Fri, 08 May 2026 18:00:22 +0100
Rodrigo Alencar via B4 Relay <devnull+rodrigo.alencar.analog.com@kernel.org> wrote:
> From: Rodrigo Alencar <rodrigo.alencar@analog.com>
>
> Add RAM control channel, which includes:
> - RAM data loading via firmware upload interface;
> - Per-profile configuration and DDS core parameter destination as firmware
> metadata;
> - Profile switching relying on profile channels;
> - Sampling frequency control of the active profile;
> - ram-enable-aware read/write paths that redirect single tone
> frequency/phase/amplitude access through reg_profile cache when RAM is
> active;
>
> When RAM is enabled, the DDS profile parameters (frequency, phase,
> amplitude) for the single tone mode are sourced from a shadow register
> cache (reg_profile[]) since the profile registers are repurposed for RAM
> control.
>
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
Minor stuff inline.
> +
> +static enum fw_upload_err ad9910_ram_fwu_write(struct fw_upload *fw_upload,
> + const u8 *data, u32 offset,
> + u32 size, u32 *written)
> +{
> + const struct ad9910_ram_fw *fw_data = (const struct ad9910_ram_fw *)data;
> + struct ad9910_state *st = fw_upload->dd_handle;
> + int ret, ret2, idx, wcount;
> + u64 tmp64, backup;
> +
> + if (offset != 0)
> + return FW_UPLOAD_ERR_INVALID_SIZE;
> +
> + guard(mutex)(&st->lock);
> +
> + if (st->ram_fwu_cancel)
> + return FW_UPLOAD_ERR_CANCELED;
> +
> + if (AD9910_RAM_ENABLED(st))
> + return FW_UPLOAD_ERR_HW_ERROR;
> +
> + /* copy ram profiles */
> + for (idx = 0; idx < AD9910_NUM_PROFILES; idx++)
> + st->reg_profile[idx] = get_unaligned_be64(&fw_data->profiles[idx]) |
> + AD9910_PROFILE_RAM_OPEN_MSK;
> +
> + /* update CFR1 */
Comment is kind of obvious. Maybe say more or drop it.
> + ret = ad9910_reg32_update(st, AD9910_REG_CFR1,
> + AD9910_CFR1_RAM_PLAYBACK_DEST_MSK |
> + AD9910_CFR1_INT_PROFILE_CTL_MSK,
> + get_unaligned_be32(&fw_data->cfr1), true);
> + if (ret)
> + return FW_UPLOAD_ERR_RW_ERROR;
> +
> + wcount = get_unaligned_be32(&fw_data->wcount);
> + if (!wcount) {
> + *written = size;
> + return FW_UPLOAD_ERR_NONE; /* nothing else to write */
> + }
> +
> + /* ensure profile is selected */
Comment is not adding value unless there is more to say.
> + ret = ad9910_profile_set(st, st->profile);
> + if (ret)
> + return FW_UPLOAD_ERR_HW_ERROR;
> +
> + /* backup profile register and update it with required address range */
> + backup = st->reg[AD9910_REG_PROFILE(st->profile)].val64;
> + tmp64 = AD9910_PROFILE_RAM_STEP_RATE_MSK |
> + FIELD_PREP(AD9910_PROFILE_RAM_START_ADDR_MSK, 0) |
> + FIELD_PREP(AD9910_PROFILE_RAM_END_ADDR_MSK, wcount - 1);
> + ret = ad9910_reg64_write(st, AD9910_REG_PROFILE(st->profile), tmp64, true);
> + if (ret)
> + return FW_UPLOAD_ERR_RW_ERROR;
> +
> + /* populate words into tx_buf[1:] */
Another comment that doesn't add value given the code is obviously doing that.
If nothing else to say remove it.
> + memcpy(&st->tx_buf[1], fw_data->words, wcount * AD9910_RAM_WORD_SIZE);
> +
> + /* write ram data and restore profile register */
> + ret = ad9910_spi_write(st, AD9910_REG_RAM,
> + wcount * AD9910_RAM_WORD_SIZE, false);
> + ret2 = ad9910_reg64_write(st, AD9910_REG_PROFILE(st->profile), backup, true);
> + if (ret || ret2)
> + return FW_UPLOAD_ERR_RW_ERROR;
> +
> + *written = size;
> + return FW_UPLOAD_ERR_NONE;
> +}
> static int ad9910_probe(struct spi_device *spi)
> {
> static const char * const supplies[] = {
> @@ -1688,7 +1991,21 @@ static int ad9910_probe(struct spi_device *spi)
> if (ret)
> return dev_err_probe(dev, ret, "device setup failed\n");
>
> - return devm_iio_device_register(dev, indio_dev);
> + ret = devm_iio_device_register(dev, indio_dev);
> + if (ret)
> + return ret;
> +
> + snprintf(st->ram_fwu_name, sizeof(st->ram_fwu_name), "%s:ram",
> + dev_name(&indio_dev->dev));
> + st->ram_fwu = firmware_upload_register(THIS_MODULE, dev, st->ram_fwu_name,
> + &ad9910_ram_fwu_ops, st);
> + if (IS_ERR(st->ram_fwu))
> + return dev_err_probe(dev, PTR_ERR(st->ram_fwu),
> + "failed to register ram upload ops\n");
> +
> + ad9910_debugfs_init(st, indio_dev);
> +
> + return devm_add_action_or_reset(dev, ad9910_ram_fwu_unregister, st->ram_fwu);
Why is this only after we've registered the device? At that point userspace
stuff is exposed, so any risk of a race with this bit not having finished yet?
Perhaps a comment would be useful.
> }
>
> static const struct spi_device_id ad9910_id[] = {
>
next prev parent reply other threads:[~2026-05-17 15:06 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 17:00 [PATCH RFC v4 00/10] AD9910 Direct Digital Synthesizer Rodrigo Alencar via B4 Relay
2026-05-08 17:00 ` [PATCH RFC v4 01/10] dt-bindings: iio: frequency: add ad9910 Rodrigo Alencar via B4 Relay
2026-05-12 18:31 ` Jonathan Cameron
2026-05-13 15:09 ` Rodrigo Alencar
2026-05-16 10:40 ` Jonathan Cameron
2026-05-17 10:12 ` Rodrigo Alencar
2026-05-17 11:28 ` Jonathan Cameron
2026-05-08 17:00 ` [PATCH RFC v4 02/10] iio: core: support 64-bit register through debugfs Rodrigo Alencar via B4 Relay
2026-05-10 10:07 ` Andy Shevchenko
2026-05-11 10:47 ` Rodrigo Alencar
2026-05-08 17:00 ` [PATCH RFC v4 03/10] iio: frequency: ad9910: initial driver implementation Rodrigo Alencar via B4 Relay
2026-05-17 14:47 ` Jonathan Cameron
2026-05-17 18:07 ` Rodrigo Alencar
2026-05-18 13:42 ` Jonathan Cameron
2026-05-08 17:00 ` [PATCH RFC v4 04/10] iio: frequency: ad9910: add basic parallel port support Rodrigo Alencar via B4 Relay
2026-05-08 17:00 ` [PATCH RFC v4 05/10] iio: frequency: ad9910: add digital ramp generator support Rodrigo Alencar via B4 Relay
2026-05-17 15:01 ` Jonathan Cameron
2026-05-08 17:00 ` [PATCH RFC v4 06/10] iio: frequency: ad9910: add RAM mode support Rodrigo Alencar via B4 Relay
2026-05-17 15:06 ` Jonathan Cameron [this message]
2026-05-08 17:00 ` [PATCH RFC v4 07/10] iio: frequency: ad9910: add output shift keying support Rodrigo Alencar via B4 Relay
2026-05-17 15:08 ` Jonathan Cameron
2026-05-08 17:00 ` [PATCH RFC v4 08/10] iio: frequency: ad9910: show channel priority in debugfs Rodrigo Alencar via B4 Relay
2026-05-08 17:00 ` [PATCH RFC v4 09/10] Documentation: ABI: testing: add docs for ad9910 sysfs entries Rodrigo Alencar via B4 Relay
2026-05-17 14:58 ` Jonathan Cameron
2026-05-17 15:45 ` Jonathan Cameron
2026-05-17 17:30 ` Rodrigo Alencar
2026-05-18 13:45 ` Jonathan Cameron
2026-05-18 15:27 ` Rodrigo Alencar
2026-05-20 9:54 ` Jonathan Cameron
2026-05-08 17:00 ` [PATCH RFC v4 10/10] docs: iio: add documentation for ad9910 driver Rodrigo Alencar via B4 Relay
2026-05-09 23:42 ` David Lechner
2026-05-10 9:30 ` Rodrigo Alencar
2026-05-11 14:46 ` David Lechner
2026-05-11 15:02 ` Rodrigo Alencar
2026-05-11 15:23 ` David Lechner
2026-05-11 16:01 ` Rodrigo Alencar
2026-05-15 15:47 ` Rodrigo Alencar
2026-05-17 15:44 ` Jonathan Cameron
2026-05-17 17:54 ` Rodrigo Alencar
2026-05-09 22:31 ` [PATCH RFC v4 00/10] AD9910 Direct Digital Synthesizer David Lechner
2026-05-10 8:50 ` Rodrigo Alencar
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