From: Jason Gunthorpe <jgg@nvidia.com>
To: Mostafa Saleh <smostafa@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Jonathan Corbet <corbet@lwn.net>,
iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
Mark Rutland <mark.rutland@arm.com>,
Randy Dunlap <rdunlap@infradead.org>,
Robin Murphy <robin.murphy@arm.com>,
Shuah Khan <skhan@linuxfoundation.org>,
Will Deacon <will@kernel.org>,
David Matlack <dmatlack@google.com>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Nicolin Chen <nicolinc@nvidia.com>,
Pasha Tatashin <pasha.tatashin@soleen.com>,
patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
Samiullah Khawaja <skhawaja@google.com>,
stable@vger.kernel.org,
Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>
Subject: Re: [PATCH v5 6/9] iommu/arm-smmu-v3: Precompute the invalidation commands
Date: Mon, 7 Sep 2026 12:19:53 -0300 [thread overview]
Message-ID: <20260907151953.GZ4157646@nvidia.com> (raw)
In-Reply-To: <ap7J6NKXgWhiwXgL@google.com>
On Mon, Sep 07, 2026 at 02:27:52PM +0000, Mostafa Saleh wrote:
> On Tue, Sep 01, 2026 at 02:49:55PM -0300, Jason Gunthorpe wrote:
> > Store the required cmd data in the tlbi and just copy it out when
> > processing each item in the invs list. The cmd form only depends on
> > if the instance supports RIL or not, otherwise it is always the same.
> >
> > This avoids redundant calculations for each invs entry.
>
> As I mentioned on v2, I don’t see a value for this without smmu
> sharing over the same domain, as this just adds extra complexity IMHO,
> but that's up to Robin and Will.
Nicolin already has a series that does exactly this, waiting for stuff
already on the list to get merged before posting it. I'd rather have
things organized in the way we know we need them..
Otherwise we need to go around and change this stuff again..
Jason
next prev parent reply other threads:[~2026-09-07 15:19 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 17:49 [PATCH v5 0/9] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 1/9] iommu/arm-smmu-v3: Handle ARM erratum for CONT under invalidation with SVA Jason Gunthorpe
2026-09-07 14:21 ` Mostafa Saleh
2026-09-07 15:11 ` Jason Gunthorpe
2026-09-07 15:17 ` Mostafa Saleh
2026-09-07 15:18 ` Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 2/9] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 3/9] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-09-07 14:22 ` Mostafa Saleh
2026-09-01 17:49 ` [PATCH v5 4/9] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-09-07 14:26 ` Mostafa Saleh
2026-09-07 15:23 ` Jason Gunthorpe
2026-09-07 19:34 ` Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 5/9] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 6/9] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-09-07 14:27 ` Mostafa Saleh
2026-09-07 15:19 ` Jason Gunthorpe [this message]
2026-09-01 17:49 ` [PATCH v5 7/9] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 8/9] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-09-07 14:42 ` Mostafa Saleh
2026-09-07 15:34 ` Jason Gunthorpe
2026-09-09 15:57 ` Jason Gunthorpe
2026-09-01 17:49 ` [PATCH v5 9/9] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-09-07 14:44 ` Mostafa Saleh
2026-09-07 19:39 ` Jason Gunthorpe
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