[PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT

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* [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
       [not found] <20241001043602.1116991-1-anshuman.khandual@arm.com>
@ 2024-10-01  4:36 ` Anshuman Khandual
  2024-10-02 23:25   ` kernel test robot
                     ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-10-01  4:36 UTC (permalink / raw)
  To: linux-kernel, linux-arm-kernel
  Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
	James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
	Mark Brown, Mark Rutland, kvmarm, linux-doc

Fine grained trap control for MDSELR_EL1 register needs to be configured in
HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
is also present. This adds a new helper __init_el2_fgt2() initializing this
new FEAT_FGT2 based fine grained registers.

MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
This updates __init_el2_debug() as required for FEAT_Debugv8p9.

While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: kvmarm@lists.linux.dev
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 Documentation/arch/arm64/booting.rst | 19 +++++++++++++++++++
 arch/arm64/include/asm/el2_setup.h   | 27 +++++++++++++++++++++++++++
 arch/arm64/include/asm/kvm_arm.h     |  1 +
 3 files changed, 47 insertions(+)

diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index b57776a68f15..e69d972018cf 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -285,6 +285,12 @@ Before jumping into the kernel, the following conditions must be met:
 
     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
 
+  For CPUs with the Fine Grained Traps (FEAT_FGT2) extension present:
+
+  - If EL3 is present and the kernel is entered at EL2:
+
+    - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
+
   For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
 
   - If EL3 is present and the kernel is entered at EL2:
@@ -319,6 +325,19 @@ Before jumping into the kernel, the following conditions must be met:
     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
       kernel will execute on.
 
+  For CPUs with FEAT_Debugv8p9 extension present:
+
+  - If the kernel is entered at EL1 and EL2 is present:
+
+    - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
+    - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
+    - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
+
+  - If EL3 is present:
+
+    - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
+    - MDCR_EL3.EBWE (bit 43) must be initialized to 0b1
+
   For CPUs with the Scalable Matrix Extension (FEAT_SME):
 
   - If EL3 is present:
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index e0ffdf13a18b..2e6a8de5e4e4 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -97,6 +97,14 @@
 						// to own it.
 
 .Lskip_trace_\@:
+	mrs	x1, id_aa64dfr0_el1
+	ubfx	x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
+	cmp	x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
+	b.lt	.Lskip_dbg_v8p9_\@
+
+	mov	x0, #MDCR_EL2_EBWE
+	orr	x2, x2, x0
+.Lskip_dbg_v8p9_\@:
 	msr	mdcr_el2, x2			// Configure debug traps
 .endm
 
@@ -215,6 +223,24 @@
 .Lskip_fgt_\@:
 .endm
 
+.macro __init_el2_fgt2
+	mrs	x1, id_aa64mmfr0_el1
+	ubfx	x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
+	cmp	x1, #ID_AA64MMFR0_EL1_FGT_FGT2
+	b.lt	.Lskip_fgt2_\@
+
+	mrs	x1, id_aa64dfr0_el1
+	ubfx	x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
+	cmp	x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
+	b.lt	.Lskip_dbg_v8p9_\@
+
+	mov_q   x0, HDFGWTR2_EL2_nMDSELR_EL1
+	msr_s	SYS_HDFGWTR2_EL2, x0
+	msr_s	SYS_HDFGRTR2_EL2, x0
+.Lskip_dbg_v8p9_\@:
+.Lskip_fgt2_\@:
+.endm
+
 .macro __init_el2_nvhe_prepare_eret
 	mov	x0, #INIT_PSTATE_EL1
 	msr	spsr_el2, x0
@@ -240,6 +266,7 @@
 	__init_el2_nvhe_idregs
 	__init_el2_cptr
 	__init_el2_fgt
+	__init_el2_fgt2
 .endm
 
 #ifndef __KVM_NVHE_HYPERVISOR__
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 850fac9a7840..18aeec43efc2 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -312,6 +312,7 @@
 				 GENMASK(15, 0))
 
 /* Hyp Debug Configuration Register bits */
+#define MDCR_EL2_EBWE		(UL(1) << 43)
 #define MDCR_EL2_E2TB_MASK	(UL(0x3))
 #define MDCR_EL2_E2TB_SHIFT	(UL(24))
 #define MDCR_EL2_HPMFZS		(UL(1) << 36)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
  2024-10-01  4:36 ` [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Anshuman Khandual
@ 2024-10-02 23:25   ` kernel test robot
  2024-10-02 23:25   ` kernel test robot
  2024-10-22 16:10   ` Mark Rutland
  2 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2024-10-02 23:25 UTC (permalink / raw)
  To: Anshuman Khandual, linux-kernel, linux-arm-kernel
  Cc: llvm, oe-kbuild-all, Anshuman Khandual, Jonathan Corbet,
	Marc Zyngier, Oliver Upton, James Morse, Suzuki K Poulose,
	Catalin Marinas, Will Deacon, Mark Brown, Mark Rutland, kvmarm,
	linux-doc

Hi Anshuman,

kernel test robot noticed the following build errors:

[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on kvmarm/next soc/for-next arm/for-next arm/fixes linus/master v6.12-rc1 next-20241002]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Anshuman-Khandual/arm64-cpufeature-Add-field-details-for-ID_AA64DFR1_EL1-register/20241001-123752
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
patch link:    https://lore.kernel.org/r/20241001043602.1116991-3-anshuman.khandual%40arm.com
patch subject: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
config: arm64-randconfig-002-20241003 (https://download.01.org/0day-ci/archive/20241003/202410030702.9xBCVi6s-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241003/202410030702.9xBCVi6s-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410030702.9xBCVi6s-lkp@intel.com/

All errors (new ones prefixed by >>):

>> <instantiation>:3:10: error: expected compatible register, symbol or integer in range [0, 4095]
    cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2
            ^
   <instantiation>:12:2: note: while in macro instantiation
    __init_el2_fgt2
    ^
   arch/arm64/kernel/head.S:317:2: note: while in macro instantiation
    init_el2_state
    ^
>> <instantiation>:1:5: error: expected absolute expression
   .if (((HDFGWTR2_EL2_nMDSELR_EL1) >> 31) == 0 || ((HDFGWTR2_EL2_nMDSELR_EL1) >> 31) == 0x1ffffffff)
       ^
   <instantiation>:11:2: note: while in macro instantiation
    mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1
    ^
   <instantiation>:12:2: note: while in macro instantiation
    __init_el2_fgt2
    ^
   arch/arm64/kernel/head.S:317:2: note: while in macro instantiation
    init_el2_state
    ^
   <instantiation>:4:6: error: expected absolute expression
    .if (((HDFGWTR2_EL2_nMDSELR_EL1) >> 47) == 0 || ((HDFGWTR2_EL2_nMDSELR_EL1) >> 47) == 0x1ffff)
        ^
   <instantiation>:11:2: note: while in macro instantiation
    mov_q x0, HDFGWTR2_EL2_nMDSELR_EL1
    ^
   <instantiation>:12:2: note: while in macro instantiation
    __init_el2_fgt2
    ^
   arch/arm64/kernel/head.S:317:2: note: while in macro instantiation
    init_el2_state
    ^
>> <instantiation>:1:6: error: expected constant expression
   .inst(0xd5000000|(SYS_HDFGWTR2_EL2)|(.L__gpr_num_x0))
        ^
   <instantiation>:12:2: note: while in macro instantiation
    msr_s SYS_HDFGWTR2_EL2, x0
    ^
   <instantiation>:12:2: note: while in macro instantiation
    __init_el2_fgt2
    ^
   arch/arm64/kernel/head.S:317:2: note: while in macro instantiation
    init_el2_state
    ^
>> <instantiation>:1:6: error: expected constant expression
   .inst(0xd5000000|(SYS_HDFGRTR2_EL2)|(.L__gpr_num_x0))
        ^
   <instantiation>:13:2: note: while in macro instantiation
    msr_s SYS_HDFGRTR2_EL2, x0
    ^
   <instantiation>:12:2: note: while in macro instantiation
    __init_el2_fgt2
    ^
   arch/arm64/kernel/head.S:317:2: note: while in macro instantiation
    init_el2_state
    ^

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
  2024-10-01  4:36 ` [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Anshuman Khandual
  2024-10-02 23:25   ` kernel test robot
@ 2024-10-02 23:25   ` kernel test robot
  2024-10-22 16:10   ` Mark Rutland
  2 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2024-10-02 23:25 UTC (permalink / raw)
  To: Anshuman Khandual, linux-kernel, linux-arm-kernel
  Cc: oe-kbuild-all, Anshuman Khandual, Jonathan Corbet, Marc Zyngier,
	Oliver Upton, James Morse, Suzuki K Poulose, Catalin Marinas,
	Will Deacon, Mark Brown, Mark Rutland, kvmarm, linux-doc

Hi Anshuman,

kernel test robot noticed the following build errors:

[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on kvmarm/next soc/for-next arm/for-next arm/fixes linus/master v6.12-rc1 next-20241002]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Anshuman-Khandual/arm64-cpufeature-Add-field-details-for-ID_AA64DFR1_EL1-register/20241001-123752
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
patch link:    https://lore.kernel.org/r/20241001043602.1116991-3-anshuman.khandual%40arm.com
patch subject: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
config: arm64-allnoconfig (https://download.01.org/0day-ci/archive/20241003/202410030737.Mxx9Cvge-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241003/202410030737.Mxx9Cvge-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410030737.Mxx9Cvge-lkp@intel.com/

All errors (new ones prefixed by >>):

   arch/arm64/kernel/head.S: Assembler messages:
>> arch/arm64/kernel/head.S:550: Error: non-constant expression in ".if" statement
   arch/arm64/kernel/head.S:237:  Info: macro invoked from here
   arch/arm64/kernel/head.S:269:   Info: macro invoked from here
   arch/arm64/kernel/head.S:317:    Info: macro invoked from here
   arch/arm64/kernel/head.S:553: Error: non-constant expression in ".if" statement
   arch/arm64/kernel/head.S:237:  Info: macro invoked from here
   arch/arm64/kernel/head.S:269:   Info: macro invoked from here
   arch/arm64/kernel/head.S:317:    Info: macro invoked from here
>> arch/arm64/kernel/head.S:1094: Error: constant expression required
   arch/arm64/kernel/head.S:238:  Info: macro invoked from here
   arch/arm64/kernel/head.S:269:   Info: macro invoked from here
   arch/arm64/kernel/head.S:317:    Info: macro invoked from here
>> arch/arm64/kernel/head.S:1094: Error: constant expression required
   arch/arm64/kernel/head.S:239:  Info: macro invoked from here
   arch/arm64/kernel/head.S:269:   Info: macro invoked from here
   arch/arm64/kernel/head.S:317:    Info: macro invoked from here
>> arch/arm64/kernel/head.S:317: Error: undefined symbol ID_AA64MMFR0_EL1_FGT_FGT2 used as an immediate value


vim +317 arch/arm64/kernel/head.S

034edabe6cf1d0d Laura Abbott    2014-11-21  246  
034edabe6cf1d0d Laura Abbott    2014-11-21  247  /*
034edabe6cf1d0d Laura Abbott    2014-11-21  248   * end early head section, begin head code that is also used for
034edabe6cf1d0d Laura Abbott    2014-11-21  249   * hotplug and needs to have the same protections as the text region
034edabe6cf1d0d Laura Abbott    2014-11-21  250   */
d54170812ef1c80 Mark Rutland    2023-02-20  251  	.section ".idmap.text","a"
f80fb3a3d50843a Ard Biesheuvel  2016-01-26  252  
9703d9d7f77ce12 Catalin Marinas 2012-03-05  253  /*
ecbb11ab3ebc027 Mark Rutland    2020-11-13  254   * Starting from EL2 or EL1, configure the CPU to execute at the highest
ecbb11ab3ebc027 Mark Rutland    2020-11-13  255   * reachable EL supported by the kernel in a chosen default state. If dropping
ecbb11ab3ebc027 Mark Rutland    2020-11-13  256   * from EL2 to EL1, configure EL2 before configuring EL1.
828e9834e9a5b7e Matthew Leach   2013-10-11  257   *
d87a8e65b510112 Mark Rutland    2020-11-13  258   * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
d87a8e65b510112 Mark Rutland    2020-11-13  259   * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
828e9834e9a5b7e Matthew Leach   2013-10-11  260   *
b65e411d6cc2f12 Marc Zyngier    2022-06-30  261   * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if
b65e411d6cc2f12 Marc Zyngier    2022-06-30  262   * booted in EL1 or EL2 respectively, with the top 32 bits containing
b65e411d6cc2f12 Marc Zyngier    2022-06-30  263   * potential context flags. These flags are *not* stored in __boot_cpu_mode.
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  264   *
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  265   * x0: whether we are being called from the primary boot path with the MMU on
9703d9d7f77ce12 Catalin Marinas 2012-03-05  266   */
ecbb11ab3ebc027 Mark Rutland    2020-11-13  267  SYM_FUNC_START(init_kernel_el)
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  268  	mrs	x1, CurrentEL
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  269  	cmp	x1, #CurrentEL_EL2
d87a8e65b510112 Mark Rutland    2020-11-13  270  	b.eq	init_el2
d87a8e65b510112 Mark Rutland    2020-11-13  271  
d87a8e65b510112 Mark Rutland    2020-11-13  272  SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
31a32b49b80f79c Marc Zyngier    2021-04-08  273  	mov_q	x0, INIT_SCTLR_EL1_MMU_OFF
9d7c13e5dde3127 Ard Biesheuvel  2023-01-11  274  	pre_disable_mmu_workaround
31a32b49b80f79c Marc Zyngier    2021-04-08  275  	msr	sctlr_el1, x0
9cf71728931a407 Matthew Leach   2013-10-11  276  	isb
d87a8e65b510112 Mark Rutland    2020-11-13  277  	mov_q	x0, INIT_PSTATE_EL1
d87a8e65b510112 Mark Rutland    2020-11-13  278  	msr	spsr_el1, x0
d87a8e65b510112 Mark Rutland    2020-11-13  279  	msr	elr_el1, lr
d87a8e65b510112 Mark Rutland    2020-11-13  280  	mov	w0, #BOOT_CPU_MODE_EL1
d87a8e65b510112 Mark Rutland    2020-11-13  281  	eret
9703d9d7f77ce12 Catalin Marinas 2012-03-05  282  
d87a8e65b510112 Mark Rutland    2020-11-13  283  SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  284  	msr	elr_el2, lr
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  285  
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  286  	// clean all HYP code to the PoC if we booted at EL2 with the MMU on
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  287  	cbz	x0, 0f
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  288  	adrp	x0, __hyp_idmap_text_start
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  289  	adr_l	x1, __hyp_text_end
d54170812ef1c80 Mark Rutland    2023-02-20  290  	adr_l	x2, dcache_clean_poc
d54170812ef1c80 Mark Rutland    2023-02-20  291  	blr	x2
34e526cb7d46726 Ard Biesheuvel  2024-04-15  292  
34e526cb7d46726 Ard Biesheuvel  2024-04-15  293  	mov_q	x0, INIT_SCTLR_EL2_MMU_OFF
34e526cb7d46726 Ard Biesheuvel  2024-04-15  294  	pre_disable_mmu_workaround
34e526cb7d46726 Ard Biesheuvel  2024-04-15  295  	msr	sctlr_el2, x0
34e526cb7d46726 Ard Biesheuvel  2024-04-15  296  	isb
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  297  0:
78869f0f0552d03 David Brazdil   2020-12-02  298  	mov_q	x0, HCR_HOST_NVHE_FLAGS
b3320142f3db9b3 Marc Zyngier    2024-03-21  299  
b3320142f3db9b3 Marc Zyngier    2024-03-21  300  	/*
b3320142f3db9b3 Marc Zyngier    2024-03-21  301  	 * Compliant CPUs advertise their VHE-onlyness with
b3320142f3db9b3 Marc Zyngier    2024-03-21  302  	 * ID_AA64MMFR4_EL1.E2H0 < 0. HCR_EL2.E2H can be
b3320142f3db9b3 Marc Zyngier    2024-03-21  303  	 * RES1 in that case. Publish the E2H bit early so that
b3320142f3db9b3 Marc Zyngier    2024-03-21  304  	 * it can be picked up by the init_el2_state macro.
b3320142f3db9b3 Marc Zyngier    2024-03-21  305  	 *
b3320142f3db9b3 Marc Zyngier    2024-03-21  306  	 * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but
b3320142f3db9b3 Marc Zyngier    2024-03-21  307  	 * don't advertise it (they predate this relaxation).
b3320142f3db9b3 Marc Zyngier    2024-03-21  308  	 */
b3320142f3db9b3 Marc Zyngier    2024-03-21  309  	mrs_s	x1, SYS_ID_AA64MMFR4_EL1
b3320142f3db9b3 Marc Zyngier    2024-03-21  310  	tbz	x1, #(ID_AA64MMFR4_EL1_E2H0_SHIFT + ID_AA64MMFR4_EL1_E2H0_WIDTH - 1), 1f
b3320142f3db9b3 Marc Zyngier    2024-03-21  311  
b3320142f3db9b3 Marc Zyngier    2024-03-21  312  	orr	x0, x0, #HCR_E2H
b3320142f3db9b3 Marc Zyngier    2024-03-21  313  1:
78869f0f0552d03 David Brazdil   2020-12-02  314  	msr	hcr_el2, x0
22043a3c082a584 Dave Martin     2017-10-31  315  	isb
78869f0f0552d03 David Brazdil   2020-12-02  316  
e2df464173f0b58 Marc Zyngier    2021-02-08 @317  	init_el2_state
22043a3c082a584 Dave Martin     2017-10-31  318  
712c6ff4dba4917 Marc Zyngier    2012-10-19  319  	/* Hypervisor stub */
78869f0f0552d03 David Brazdil   2020-12-02  320  	adr_l	x0, __hyp_stub_vectors
712c6ff4dba4917 Marc Zyngier    2012-10-19  321  	msr	vbar_el2, x0
d87a8e65b510112 Mark Rutland    2020-11-13  322  	isb
78869f0f0552d03 David Brazdil   2020-12-02  323  
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  324  	mov_q	x1, INIT_SCTLR_EL1_MMU_OFF
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  325  
31a32b49b80f79c Marc Zyngier    2021-04-08  326  	mrs	x0, hcr_el2
31a32b49b80f79c Marc Zyngier    2021-04-08  327  	and	x0, x0, #HCR_E2H
3944382fa6f22b5 Marc Zyngier    2024-01-22  328  	cbz	x0, 2f
b3320142f3db9b3 Marc Zyngier    2024-03-21  329  
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  330  	/* Set a sane SCTLR_EL1, the VHE way */
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  331  	msr_s	SYS_SCTLR_EL12, x1
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  332  	mov	x2, #BOOT_CPU_FLAG_E2H
3944382fa6f22b5 Marc Zyngier    2024-01-22  333  	b	3f
31a32b49b80f79c Marc Zyngier    2021-04-08  334  
3944382fa6f22b5 Marc Zyngier    2024-01-22  335  2:
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  336  	msr	sctlr_el1, x1
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  337  	mov	x2, xzr
3944382fa6f22b5 Marc Zyngier    2024-01-22  338  3:
1700f89cb99aae1 Marc Zyngier    2023-06-14  339  	__init_el2_nvhe_prepare_eret
1700f89cb99aae1 Marc Zyngier    2023-06-14  340  
d87a8e65b510112 Mark Rutland    2020-11-13  341  	mov	w0, #BOOT_CPU_MODE_EL2
ae4b7e38e9a9479 Marc Zyngier    2022-06-30  342  	orr	x0, x0, x2
9703d9d7f77ce12 Catalin Marinas 2012-03-05  343  	eret
ecbb11ab3ebc027 Mark Rutland    2020-11-13  344  SYM_FUNC_END(init_kernel_el)
9703d9d7f77ce12 Catalin Marinas 2012-03-05  345  
9703d9d7f77ce12 Catalin Marinas 2012-03-05  346  	/*
9703d9d7f77ce12 Catalin Marinas 2012-03-05  347  	 * This provides a "holding pen" for platforms to hold all secondary
9703d9d7f77ce12 Catalin Marinas 2012-03-05  348  	 * cores are held until we're ready for them to initialise.
9703d9d7f77ce12 Catalin Marinas 2012-03-05  349  	 */
c63d9f82db94399 Mark Brown      2020-02-18  350  SYM_FUNC_START(secondary_holding_pen)
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  351  	mov	x0, xzr
ecbb11ab3ebc027 Mark Rutland    2020-11-13  352  	bl	init_kernel_el			// w0=cpu_boot_mode
005e12676af09a3 Ard Biesheuvel  2022-06-24  353  	mrs	x2, mpidr_el1
b03cc885328e3c0 Ard Biesheuvel  2016-04-18  354  	mov_q	x1, MPIDR_HWID_BITMASK
005e12676af09a3 Ard Biesheuvel  2022-06-24  355  	and	x2, x2, x1
b1c98297fe0c6e2 Ard Biesheuvel  2015-03-10  356  	adr_l	x3, secondary_holding_pen_release
9703d9d7f77ce12 Catalin Marinas 2012-03-05  357  pen:	ldr	x4, [x3]
005e12676af09a3 Ard Biesheuvel  2022-06-24  358  	cmp	x4, x2
9703d9d7f77ce12 Catalin Marinas 2012-03-05  359  	b.eq	secondary_startup
9703d9d7f77ce12 Catalin Marinas 2012-03-05  360  	wfe
9703d9d7f77ce12 Catalin Marinas 2012-03-05  361  	b	pen
c63d9f82db94399 Mark Brown      2020-02-18  362  SYM_FUNC_END(secondary_holding_pen)
652af8997993540 Mark Rutland    2013-10-24  363  
652af8997993540 Mark Rutland    2013-10-24  364  	/*
652af8997993540 Mark Rutland    2013-10-24  365  	 * Secondary entry point that jumps straight into the kernel. Only to
652af8997993540 Mark Rutland    2013-10-24  366  	 * be used where CPUs are brought online dynamically by the kernel.
652af8997993540 Mark Rutland    2013-10-24  367  	 */
c63d9f82db94399 Mark Brown      2020-02-18  368  SYM_FUNC_START(secondary_entry)
3dcf60bbfd284e5 Ard Biesheuvel  2023-01-11  369  	mov	x0, xzr
ecbb11ab3ebc027 Mark Rutland    2020-11-13  370  	bl	init_kernel_el			// w0=cpu_boot_mode
652af8997993540 Mark Rutland    2013-10-24  371  	b	secondary_startup
c63d9f82db94399 Mark Brown      2020-02-18  372  SYM_FUNC_END(secondary_entry)
9703d9d7f77ce12 Catalin Marinas 2012-03-05  373  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
  2024-10-01  4:36 ` [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Anshuman Khandual
  2024-10-02 23:25   ` kernel test robot
  2024-10-02 23:25   ` kernel test robot
@ 2024-10-22 16:10   ` Mark Rutland
  2024-10-23  6:12     ` Anshuman Khandual
  2 siblings, 1 reply; 7+ messages in thread
From: Mark Rutland @ 2024-10-22 16:10 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-kernel, linux-arm-kernel, Jonathan Corbet, Marc Zyngier,
	Oliver Upton, James Morse, Suzuki K Poulose, Catalin Marinas,
	Will Deacon, Mark Brown, kvmarm, linux-doc

On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote:
> Fine grained trap control for MDSELR_EL1 register needs to be configured in
> HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
> is also present. This adds a new helper __init_el2_fgt2() initializing this
> new FEAT_FGT2 based fine grained registers.
> 
> MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
> watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
> This updates __init_el2_debug() as required for FEAT_Debugv8p9.
> 
> While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.

[...]

> +  For CPUs with FEAT_Debugv8p9 extension present:
> +
> +  - If the kernel is entered at EL1 and EL2 is present:
> +
> +    - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
> +    - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
> +    - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
> +
> +  - If EL3 is present:
> +
> +    - MDCR_EL3.TDA (bit 9) must be initialized to 0b0

AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need
MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably
check if there's anything else we haven't yet documented in MDCR_EL3.

[...]

>  .Lskip_trace_\@:
> +	mrs	x1, id_aa64dfr0_el1
> +	ubfx	x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
> +	cmp	x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
> +	b.lt	.Lskip_dbg_v8p9_\@
> +
> +	mov	x0, #MDCR_EL2_EBWE
> +	orr	x2, x2, x0

That can be:

	orr	x2, x2, #MDCR_EL2_EBWE

Mark.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
  2024-10-22 16:10   ` Mark Rutland
@ 2024-10-23  6:12     ` Anshuman Khandual
  2024-10-28 12:35       ` Mark Rutland
  0 siblings, 1 reply; 7+ messages in thread
From: Anshuman Khandual @ 2024-10-23  6:12 UTC (permalink / raw)
  To: Mark Rutland
  Cc: linux-kernel, linux-arm-kernel, Jonathan Corbet, Marc Zyngier,
	Oliver Upton, James Morse, Suzuki K Poulose, Catalin Marinas,
	Will Deacon, Mark Brown, kvmarm, linux-doc



On 10/22/24 21:40, Mark Rutland wrote:
> On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote:
>> Fine grained trap control for MDSELR_EL1 register needs to be configured in
>> HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
>> is also present. This adds a new helper __init_el2_fgt2() initializing this
>> new FEAT_FGT2 based fine grained registers.
>>
>> MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
>> watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
>> This updates __init_el2_debug() as required for FEAT_Debugv8p9.
>>
>> While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.
> 
> [...]
> 
>> +  For CPUs with FEAT_Debugv8p9 extension present:
>> +
>> +  - If the kernel is entered at EL1 and EL2 is present:
>> +
>> +    - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
>> +    - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
>> +    - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
>> +
>> +  - If EL3 is present:
>> +
>> +    - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
> 
> AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need

That's because MDCR_EL3.TDA=0, enables access to many other debug registers
beside FEAT_Debugv8p9, which are currently used and hence this MDCR_EL3.TDA
=0 requirement is a not a new one but rather a missing one instead ?

> MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably
> check if there's anything else we haven't yet documented in MDCR_EL3.

Will scan through MDCR_EL3 register and match it with existing documentation
i.e Documentation/arch/arm64/booting.rst. If there are some missing MDCR_EL3
fields which should be mentioned, will add them via a separate pre-requisite
patch ?

> 
> [...]
> 
>>  .Lskip_trace_\@:
>> +	mrs	x1, id_aa64dfr0_el1
>> +	ubfx	x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
>> +	cmp	x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
>> +	b.lt	.Lskip_dbg_v8p9_\@
>> +
>> +	mov	x0, #MDCR_EL2_EBWE
>> +	orr	x2, x2, x0
> 
> That can be:
> 
> 	orr	x2, x2, #MDCR_EL2_EBWE

Right, will change.

> 
> Mark.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
  2024-10-23  6:12     ` Anshuman Khandual
@ 2024-10-28 12:35       ` Mark Rutland
  2024-10-28 13:43         ` Anshuman Khandual
  0 siblings, 1 reply; 7+ messages in thread
From: Mark Rutland @ 2024-10-28 12:35 UTC (permalink / raw)
  To: Anshuman Khandual
  Cc: linux-kernel, linux-arm-kernel, Jonathan Corbet, Marc Zyngier,
	Oliver Upton, James Morse, Suzuki K Poulose, Catalin Marinas,
	Will Deacon, Mark Brown, kvmarm, linux-doc

On Wed, Oct 23, 2024 at 11:42:37AM +0530, Anshuman Khandual wrote:
> 
> 
> On 10/22/24 21:40, Mark Rutland wrote:
> > On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote:
> >> Fine grained trap control for MDSELR_EL1 register needs to be configured in
> >> HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
> >> is also present. This adds a new helper __init_el2_fgt2() initializing this
> >> new FEAT_FGT2 based fine grained registers.
> >>
> >> MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
> >> watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
> >> This updates __init_el2_debug() as required for FEAT_Debugv8p9.
> >>
> >> While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.
> > 
> > [...]
> > 
> >> +  For CPUs with FEAT_Debugv8p9 extension present:
> >> +
> >> +  - If the kernel is entered at EL1 and EL2 is present:
> >> +
> >> +    - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
> >> +    - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
> >> +    - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
> >> +
> >> +  - If EL3 is present:
> >> +
> >> +    - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
> > 
> > AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need
> 
> That's because MDCR_EL3.TDA=0, enables access to many other debug registers
> beside FEAT_Debugv8p9, which are currently used and hence this MDCR_EL3.TDA
> =0 requirement is a not a new one but rather a missing one instead ?

Yes, that's why I said we need it regardless; it's an existing
requirement that wasn't documented.

> 
> > MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably
> > check if there's anything else we haven't yet documented in MDCR_EL3.
> 
> Will scan through MDCR_EL3 register and match it with existing documentation
> i.e Documentation/arch/arm64/booting.rst. If there are some missing MDCR_EL3
> fields which should be mentioned, will add them via a separate pre-requisite
> patch ?

Yes please.

Mark.

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
  2024-10-28 12:35       ` Mark Rutland
@ 2024-10-28 13:43         ` Anshuman Khandual
  0 siblings, 0 replies; 7+ messages in thread
From: Anshuman Khandual @ 2024-10-28 13:43 UTC (permalink / raw)
  To: Mark Rutland
  Cc: linux-kernel, linux-arm-kernel, Jonathan Corbet, Marc Zyngier,
	Oliver Upton, James Morse, Suzuki K Poulose, Catalin Marinas,
	Will Deacon, Mark Brown, kvmarm, linux-doc



On 10/28/24 18:05, Mark Rutland wrote:
> On Wed, Oct 23, 2024 at 11:42:37AM +0530, Anshuman Khandual wrote:
>>
>>
>> On 10/22/24 21:40, Mark Rutland wrote:
>>> On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote:
>>>> Fine grained trap control for MDSELR_EL1 register needs to be configured in
>>>> HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
>>>> is also present. This adds a new helper __init_el2_fgt2() initializing this
>>>> new FEAT_FGT2 based fine grained registers.
>>>>
>>>> MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
>>>> watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
>>>> This updates __init_el2_debug() as required for FEAT_Debugv8p9.
>>>>
>>>> While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.
>>>
>>> [...]
>>>
>>>> +  For CPUs with FEAT_Debugv8p9 extension present:
>>>> +
>>>> +  - If the kernel is entered at EL1 and EL2 is present:
>>>> +
>>>> +    - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
>>>> +    - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
>>>> +    - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
>>>> +
>>>> +  - If EL3 is present:
>>>> +
>>>> +    - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
>>>
>>> AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need
>>
>> That's because MDCR_EL3.TDA=0, enables access to many other debug registers
>> beside FEAT_Debugv8p9, which are currently used and hence this MDCR_EL3.TDA
>> =0 requirement is a not a new one but rather a missing one instead ?
> 
> Yes, that's why I said we need it regardless; it's an existing
> requirement that wasn't documented.

Alright, got it.

> 
>>
>>> MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably
>>> check if there's anything else we haven't yet documented in MDCR_EL3.
>>
>> Will scan through MDCR_EL3 register and match it with existing documentation
>> i.e Documentation/arch/arm64/booting.rst. If there are some missing MDCR_EL3
>> fields which should be mentioned, will add them via a separate pre-requisite
>> patch ?
> 
> Yes please.
> 
> Mark.

Sure, will separate those changes in a pre-requisite patch as suggested.

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2024-10-28 13:43 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2024-10-01  4:36 ` [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 Anshuman Khandual
2024-10-02 23:25   ` kernel test robot
2024-10-02 23:25   ` kernel test robot
2024-10-22 16:10   ` Mark Rutland
2024-10-23  6:12     ` Anshuman Khandual
2024-10-28 12:35       ` Mark Rutland
2024-10-28 13:43         ` Anshuman Khandual

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