* [PATCH v2 0/4] x86/resctrl: Non-contiguous bitmasks in Intel CAT
@ 2023-09-22 8:47 Maciej Wieczor-Retman
2023-09-22 8:48 ` [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks Maciej Wieczor-Retman
0 siblings, 1 reply; 6+ messages in thread
From: Maciej Wieczor-Retman @ 2023-09-22 8:47 UTC (permalink / raw)
To: fenghua.yu, reinette.chatre, tglx, mingo, bp, dave.hansen, corbet
Cc: x86, hpa, linux-kernel, linux-doc, ilpo.jarvinen
Until recently Intel CPUs didn't support using non-contiguous 1s
in Cache Allocation Technology (CAT). Writing a bitmask with
non-contiguous 1s to the resctrl schemata file would fail.
Intel CPUs that support non-contiguous 1s can be identified through a
CPUID leaf mentioned in the "Intel® Architecture Instruction Set
Extensions Programming Reference" document available at:
https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
Add kernel support for detecting if non-contiguous 1s in Cache
Allocation Technology (CAT) are supported by the hardware. Also add a
new resctrl FS file to output this information to the userspace.
Keep the hardcoded value for Haswell CPUs only since they do not have
CPUID enumeration support for Cache allocation.
Since the selftests/resctrl files are going through many rewrites and
cleanups the appropriate selftest is still a work in progress. For
basic selftesting capabilities use the bash script attached below this
paragraph. It checks whether various bitmasks written into resctrl FS
generate output consistent with reported feature support.
#!/bin/bash
# must be run as root, depends on a recent cpuid tool (20230406 or later)
# variables
RESCTRL_INFO="/sys/fs/resctrl/info"
L3_NON_CONT_VAL="${RESCTRL_INFO}/L3/sparse_bitmaps"
L2_NON_CONT_VAL="${RESCTRL_INFO}/L2/sparse_bitmaps"
L3_NON_CONT_CBM="${RESCTRL_INFO}/L3/cbm_mask"
L2_NON_CONT_CBM="${RESCTRL_INFO}/L2/cbm_mask"
L3_CPUID_CMD="cpuid -1 -l 0x10 -s 0x01"
L2_CPUID_CMD="cpuid -1 -l 0x10 -s 0x02"
PASSED_TESTS=0
L3_SUPPORT=0
L2_SUPPORT=0
TESTS=0
run_test() {
# L2 or L3
CACHE_LEVEL=$1
CACHE_LEVEL_SUPPORT="${CACHE_LEVEL}_SUPPORT"
echo "Checking ${RESCTRL_INFO}/${CACHE_LEVEL}..."
if [[ -d "${RESCTRL_INFO}/${CACHE_LEVEL}" ]]; then
eval "${CACHE_LEVEL_SUPPORT}=1"
echo "${CACHE_LEVEL} CAT Feature is supported"
else
echo "${CACHE_LEVEL} CAT Feature is not supported"
fi
if [[ ${!CACHE_LEVEL_SUPPORT} -eq 1 ]]; then
echo " --- Running tests for ${CACHE_LEVEL} CAT ---"
# read sysfs entries
# are non-contiguous cbm supported? (driver sysfs)
eval "NON_CONT_VAL=${CACHE_LEVEL}_NON_CONT_VAL"
eval "NON_CONT_FEAT=$( cat ${!NON_CONT_VAL} )"
# are non-contiguous cbm supported? (cpuid)
CACHE_CPUID_CMD="${CACHE_LEVEL}_CPUID_CMD"
NONCONT_CPUID=$(${!CACHE_CPUID_CMD} | grep non-contiguous | grep true)
NONCONT_CPUID_RET=$(( !$? ))
# what is the mask size?
eval "NON_CONT_CBM=${CACHE_LEVEL}_NON_CONT_CBM"
MAX_MASK=$(( 16#$( cat ${!NON_CONT_CBM} ) ))
# prepare contiguous and non-contiguous masks for tests
BC_STRING="l(${MAX_MASK})/l(2)"
MAX_MASK_BIT_COUNT=$(echo ${BC_STRING} | bc -l)
MAX_MASK_BIT_COUNT=$(printf "%.0f" "$MAX_MASK_BIT_COUNT")
BITSHIFT=$(( $MAX_MASK_BIT_COUNT/2 - ($MAX_MASK_BIT_COUNT/2 % 4) ))
CONT_MASK=$(( $MAX_MASK >> $BITSHIFT ))
NONCONT_MASK=$(( ~( $MAX_MASK & ( 15<<$BITSHIFT) ) ))
NONCONT_MASK=$(( $NONCONT_MASK & $MAX_MASK ))
# test if cpuid reported support matches the sysfs one
echo " * Testing if CPUID matches ${CACHE_LEVEL}/sparse_bitmaps..."
TESTS=$((TESTS + 1))
if [[ $NONCONT_CPUID_RET -eq $NON_CONT_FEAT ]]; then
PASSED_TESTS=$((PASSED_TESTS + 1))
echo "There is a match!"
else
echo "Error - no match!"
fi
# test by writing CBMs to the schemata
printf " * Writing 0x%x mask to the schemata...\n" ${CONT_MASK}
TESTS=$((TESTS + 1))
SCHEMATA=$(printf "${CACHE_LEVEL}:0=%x" $CONT_MASK)
echo "$SCHEMATA" > /sys/fs/resctrl/schemata
if [[ $? -eq 0 ]]; then
PASSED_TESTS=$((PASSED_TESTS + 1))
echo "Contiguous ${CACHE_LEVEL} write correct!"
else
echo "Contiguous ${CACHE_LEVEL} write ERROR!"
fi
printf " * Writing 0x%x mask to the schemata...\n" ${NONCONT_MASK}
TESTS=$((TESTS + 1))
SCHEMATA=$(printf "${CACHE_LEVEL}:0=%x" $NONCONT_MASK)
echo "$SCHEMATA" > /sys/fs/resctrl/schemata
if [[ (($? -eq 0) && ($NON_CONT_FEAT -eq 1)) || \
(($? -ne 0) && ($NON_CONT_FEAT -eq 0)) ]]; then
PASSED_TESTS=$((PASSED_TESTS + 1))
echo "Non-contiguous ${CACHE_LEVEL} write correct!"
else
echo "Non-contiguous ${CACHE_LEVEL} write ERROR!"
fi
fi
}
# mount resctrl
mount -t resctrl resctrl /sys/fs/resctrl
run_test L3
run_test L2
echo "TESTS PASSED / ALL TESTS : ${PASSED_TESTS} / ${TESTS}"
# unmount resctrl
umount /sys/fs/resctrl
Changelog v2:
- Change git signature from Wieczor-Retman Maciej to Maciej
Wieczor-Retman.
- Change bitmap naming convention to bit mask.
- Add patch to change arch_has_sparce_bitmaps name to match bitmask
naming convention.
Fenghua Yu (2):
x86/resctrl: Add sparse_masks file in info
Documentation/x86: Document resctrl's new sparse_masks
Maciej Wieczor-Retman (2):
x86/resctrl: Enable non-contiguous bits in Intel CAT
x86/resctrl: Rename arch_has_sparse_bitmaps
Documentation/arch/x86/resctrl.rst | 16 ++++++++++++----
arch/x86/kernel/cpu/resctrl/core.c | 11 +++++++----
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 14 ++++++++------
arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++++++++++
include/linux/resctrl.h | 6 +++---
6 files changed, 57 insertions(+), 17 deletions(-)
base-commit: 27bbf45eae9ca98877a2d52a92a188147cd61b07
--
2.42.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks 2023-09-22 8:47 [PATCH v2 0/4] x86/resctrl: Non-contiguous bitmasks in Intel CAT Maciej Wieczor-Retman @ 2023-09-22 8:48 ` Maciej Wieczor-Retman 2023-09-27 22:47 ` Moger, Babu 0 siblings, 1 reply; 6+ messages in thread From: Maciej Wieczor-Retman @ 2023-09-22 8:48 UTC (permalink / raw) To: Fenghua Yu, Reinette Chatre, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin, Jonathan Corbet Cc: linux-kernel, linux-doc From: Fenghua Yu <fenghua.yu@intel.com> The documentation mentions that non-contiguous bit masks are not supported in Intel Cache Allocation Technology (CAT). Update the documentation on how to determine if sparse bit masks are allowed in L2 and L3 CAT. Mention the file with feature support information is located in the /sys/fs/resctrl/info/{resource}/ directories and enumerate what are the possible outputs on file read operation. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com> --- Changelog v2: - Change bitmap naming convention to bit mask. (Reinette) Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index cb05d90111b4..4c6421e2aa31 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -124,6 +124,13 @@ related to allocation: "P": Corresponding region is pseudo-locked. No sharing allowed. +"sparse_masks": + Indicates if non-contiguous 1s value in CBM is supported. + + "0": + Only contiguous 1s value in CBM is supported. + "1": + Non-contiguous 1s value in CBM is supported. Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: @@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available for allocation using a bitmask. The maximum value of the mask is defined by each cpu model (and may be different for different cache levels). It is found using CPUID, but is also provided in the "info" directory of -the resctrl file system in "info/{resource}/cbm_mask". Intel hardware +the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware requires that these masks have all the '1' bits in a contiguous block. So 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 -and 0xA are not. On a system with a 20-bit mask each bit represents 5% -of the capacity of the cache. You could partition the cache into four -equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. +and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks +if non-contiguous 1s value is supported. On a system with a 20-bit mask +each bit represents 5% of the capacity of the cache. You could partition +the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. Memory bandwidth Allocation and monitoring ========================================== -- 2.42.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks 2023-09-22 8:48 ` [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks Maciej Wieczor-Retman @ 2023-09-27 22:47 ` Moger, Babu 2023-09-27 22:58 ` Reinette Chatre 0 siblings, 1 reply; 6+ messages in thread From: Moger, Babu @ 2023-09-27 22:47 UTC (permalink / raw) To: Maciej Wieczor-Retman, Fenghua Yu, Reinette Chatre, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin, Jonathan Corbet Cc: linux-kernel, linux-doc Hi Maciej On 9/22/2023 3:48 AM, Maciej Wieczor-Retman wrote: > From: Fenghua Yu <fenghua.yu@intel.com> > > The documentation mentions that non-contiguous bit masks are not > supported in Intel Cache Allocation Technology (CAT). > > Update the documentation on how to determine if sparse bit masks are > allowed in L2 and L3 CAT. > > Mention the file with feature support information is located in > the /sys/fs/resctrl/info/{resource}/ directories and enumerate what > are the possible outputs on file read operation. > > Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> > Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com> > --- > Changelog v2: > - Change bitmap naming convention to bit mask. (Reinette) > > Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst > index cb05d90111b4..4c6421e2aa31 100644 > --- a/Documentation/arch/x86/resctrl.rst > +++ b/Documentation/arch/x86/resctrl.rst > @@ -124,6 +124,13 @@ related to allocation: > "P": > Corresponding region is pseudo-locked. No > sharing allowed. > +"sparse_masks": > + Indicates if non-contiguous 1s value in CBM is supported. > + > + "0": > + Only contiguous 1s value in CBM is supported. This is little confusing. How about? Non-contiguous 1s value in CBM is not supported Thanks Babu > + "1": > + Non-contiguous 1s value in CBM is supported. > > Memory bandwidth(MB) subdirectory contains the following files > with respect to allocation: > @@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available > for allocation using a bitmask. The maximum value of the mask is defined > by each cpu model (and may be different for different cache levels). It > is found using CPUID, but is also provided in the "info" directory of > -the resctrl file system in "info/{resource}/cbm_mask". Intel hardware > +the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware > requires that these masks have all the '1' bits in a contiguous block. So > 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 > -and 0xA are not. On a system with a 20-bit mask each bit represents 5% > -of the capacity of the cache. You could partition the cache into four > -equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. > +and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks > +if non-contiguous 1s value is supported. On a system with a 20-bit mask > +each bit represents 5% of the capacity of the cache. You could partition > +the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. > > Memory bandwidth Allocation and monitoring > ========================================== ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks 2023-09-27 22:47 ` Moger, Babu @ 2023-09-27 22:58 ` Reinette Chatre 2023-09-27 23:02 ` Fenghua Yu 0 siblings, 1 reply; 6+ messages in thread From: Reinette Chatre @ 2023-09-27 22:58 UTC (permalink / raw) To: babu.moger, Maciej Wieczor-Retman, Fenghua Yu, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin, Jonathan Corbet Cc: linux-kernel, linux-doc Hi Babu, On 9/27/2023 3:47 PM, Moger, Babu wrote: > On 9/22/2023 3:48 AM, Maciej Wieczor-Retman wrote: >> From: Fenghua Yu <fenghua.yu@intel.com> >> >> The documentation mentions that non-contiguous bit masks are not >> supported in Intel Cache Allocation Technology (CAT). >> >> Update the documentation on how to determine if sparse bit masks are >> allowed in L2 and L3 CAT. >> >> Mention the file with feature support information is located in >> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what >> are the possible outputs on file read operation. >> >> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> >> Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com> >> --- >> Changelog v2: >> - Change bitmap naming convention to bit mask. (Reinette) >> >> Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- >> 1 file changed, 12 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst >> index cb05d90111b4..4c6421e2aa31 100644 >> --- a/Documentation/arch/x86/resctrl.rst >> +++ b/Documentation/arch/x86/resctrl.rst >> @@ -124,6 +124,13 @@ related to allocation: >> "P": >> Corresponding region is pseudo-locked. No >> sharing allowed. >> +"sparse_masks": >> + Indicates if non-contiguous 1s value in CBM is supported. >> + >> + "0": >> + Only contiguous 1s value in CBM is supported. > > This is little confusing. How about? > > Non-contiguous 1s value in CBM is not supported > It is not clear to me how changing it to a double negative reduces confusion. Reinette ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks 2023-09-27 22:58 ` Reinette Chatre @ 2023-09-27 23:02 ` Fenghua Yu 2023-09-28 13:59 ` Moger, Babu 0 siblings, 1 reply; 6+ messages in thread From: Fenghua Yu @ 2023-09-27 23:02 UTC (permalink / raw) To: Reinette Chatre, babu.moger, Maciej Wieczor-Retman, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin, Jonathan Corbet Cc: linux-kernel, linux-doc On 9/27/23 15:58, Reinette Chatre wrote: > Hi Babu, > > On 9/27/2023 3:47 PM, Moger, Babu wrote: >> On 9/22/2023 3:48 AM, Maciej Wieczor-Retman wrote: >>> From: Fenghua Yu <fenghua.yu@intel.com> >>> >>> The documentation mentions that non-contiguous bit masks are not >>> supported in Intel Cache Allocation Technology (CAT). >>> >>> Update the documentation on how to determine if sparse bit masks are >>> allowed in L2 and L3 CAT. >>> >>> Mention the file with feature support information is located in >>> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what >>> are the possible outputs on file read operation. >>> >>> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> >>> Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com> >>> --- >>> Changelog v2: >>> - Change bitmap naming convention to bit mask. (Reinette) >>> >>> Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- >>> 1 file changed, 12 insertions(+), 4 deletions(-) >>> >>> diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst >>> index cb05d90111b4..4c6421e2aa31 100644 >>> --- a/Documentation/arch/x86/resctrl.rst >>> +++ b/Documentation/arch/x86/resctrl.rst >>> @@ -124,6 +124,13 @@ related to allocation: >>> "P": >>> Corresponding region is pseudo-locked. No >>> sharing allowed. >>> +"sparse_masks": >>> + Indicates if non-contiguous 1s value in CBM is supported. >>> + >>> + "0": >>> + Only contiguous 1s value in CBM is supported. >> >> This is little confusing. How about? >> >> Non-contiguous 1s value in CBM is not supported >> > > It is not clear to me how changing it to a double > negative reduces confusion. Agree with Reinette. The original statement is clearer and more direct to explicitly state what is supported without introducing a negative assertion (not supported). Thanks. -Fenghua ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks 2023-09-27 23:02 ` Fenghua Yu @ 2023-09-28 13:59 ` Moger, Babu 0 siblings, 0 replies; 6+ messages in thread From: Moger, Babu @ 2023-09-28 13:59 UTC (permalink / raw) To: Fenghua Yu, Reinette Chatre, Maciej Wieczor-Retman, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin, Jonathan Corbet Cc: linux-kernel, linux-doc On 9/27/23 18:02, Fenghua Yu wrote: > > > On 9/27/23 15:58, Reinette Chatre wrote: >> Hi Babu, >> >> On 9/27/2023 3:47 PM, Moger, Babu wrote: >>> On 9/22/2023 3:48 AM, Maciej Wieczor-Retman wrote: >>>> From: Fenghua Yu <fenghua.yu@intel.com> >>>> >>>> The documentation mentions that non-contiguous bit masks are not >>>> supported in Intel Cache Allocation Technology (CAT). >>>> >>>> Update the documentation on how to determine if sparse bit masks are >>>> allowed in L2 and L3 CAT. >>>> >>>> Mention the file with feature support information is located in >>>> the /sys/fs/resctrl/info/{resource}/ directories and enumerate what >>>> are the possible outputs on file read operation. >>>> >>>> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> >>>> Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com> >>>> --- >>>> Changelog v2: >>>> - Change bitmap naming convention to bit mask. (Reinette) >>>> >>>> Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- >>>> 1 file changed, 12 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/Documentation/arch/x86/resctrl.rst >>>> b/Documentation/arch/x86/resctrl.rst >>>> index cb05d90111b4..4c6421e2aa31 100644 >>>> --- a/Documentation/arch/x86/resctrl.rst >>>> +++ b/Documentation/arch/x86/resctrl.rst >>>> @@ -124,6 +124,13 @@ related to allocation: >>>> "P": >>>> Corresponding region is pseudo-locked. No >>>> sharing allowed. >>>> +"sparse_masks": >>>> + Indicates if non-contiguous 1s value in CBM is supported. >>>> + >>>> + "0": >>>> + Only contiguous 1s value in CBM is supported. >>> >>> This is little confusing. How about? >>> >>> Non-contiguous 1s value in CBM is not supported >>> >> >> It is not clear to me how changing it to a double >> negative reduces confusion. > Agree with Reinette. > > The original statement is clearer and more direct to explicitly state what > is supported without introducing a negative assertion (not supported). Ok. If you all agree, fine with me as well. -- Thanks Babu Moger ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-09-28 13:59 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-22 8:47 [PATCH v2 0/4] x86/resctrl: Non-contiguous bitmasks in Intel CAT Maciej Wieczor-Retman 2023-09-22 8:48 ` [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks Maciej Wieczor-Retman 2023-09-27 22:47 ` Moger, Babu 2023-09-27 22:58 ` Reinette Chatre 2023-09-27 23:02 ` Fenghua Yu 2023-09-28 13:59 ` Moger, Babu
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox