* [PATCH v7 02/11] x86/virt/tdx: Allocate page bitmap for Dynamic PAMT
From: Rick Edgecombe @ 2026-07-18 1:44 UTC (permalink / raw)
To: bp, dave.hansen, hpa, kas, kvm, linux-coco, linux-doc,
linux-kernel, mingo, nik.borisov, pbonzini, seanjc, tglx,
vannapurve, x86, chao.gao, yan.y.zhao, kai.huang, tony.lindgren,
binbin.wu
Cc: rick.p.edgecombe, Binbin Wu
In-Reply-To: <20260718014500.2231262-1-rick.p.edgecombe@intel.com>
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
The TDX Physical Address Metadata Table (PAMT) holds data about the
physical memory used by TDX, and must be allocated by the kernel during
TDX module initialization.
The exact size of the required PAMT memory is determined by the TDX module
and may vary between TDX module versions. Currently it is approximately
0.4% of the system memory. This is a significant commitment, especially if
it is not known upfront whether the machine will run any TDX guests.
Each memory region that the TDX module might use needs three separate PAMT
allocations. One for each supported page size (1GB, 2MB, 4KB). The
TDX module supports a new feature designed to reduce PAMT overhead called
Dynamic PAMT. Under Dynamic PAMT the 4KB level is allocated dynamically
during runtime, while the 1GB and 2MB levels remain allocated on TDX
module initialization.
However, in the details, Dynamic PAMT still needs some smaller per 4KB
page scoped data (currently it is 1 bit per page). The TDX module exposes
the number of bits as a separate piece of metadata than the 4KB static
allocation for normal PAMT. Although the size is enumerated differently,
it is handed to the TDX module in the same way the 4KB page size PAMT
allocation is for normal PAMT.
Begin to implement Dynamic PAMT in the kernel by reading the bits-per-page
needed for Dynamic PAMT. Calculate the size needed for the bitmap,
and use it instead of the 4KB size determined for normal PAMT, in the case
of Dynamic PAMT.
The existing metadata reading code was generated by a script, but the
current plan is to stop generating this code, as the script has continued
to need adjustments. So add manually written code and adjust the comment
about it being autogenerated to be more generic. Start to adopt a more
normal kernel code style without the ternary statements and if
conditionals assignments that the auto generated code has.
AI was used under supervision to collect/apply feedback, review code and
workshop logs.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Co-developed-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Reviewed-by: Vishal Annapurve <vannapurve@google.com>
Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com>
Reviewed-by: Tony Lindgren <tony.lindgren@linux.intel.com>
Reviewed-by: Yan Zhao <yan.y.zhao@intel.com>
---
v7:
- Re-order pamt size calculations for greater readability (Kiryl)
- Move comment to its own line in tdx_supports_dynamic_pamt() (Yan,
Sohil)
- Log tweak (Sohil)
- Make comment in metadata reading more appropriate (Sohil)
- Drop Assisted-by tag and cover AI use in log (Dave)
- Move tdx_supports_dynamic_pamt() to not static inline to reduce
churn in later changes
v6:
- Improve comment (Binbin)
- Log tweaks
- Mark tdmr_get_pamt_bitmap_sz() __init in response to upstream
changes
- Switch to more normal kernel code style, even though it differs from
the existing auto generated code.
---
arch/x86/include/asm/tdx.h | 2 ++
arch/x86/include/asm/tdx_global_metadata.h | 3 +++
arch/x86/virt/vmx/tdx/tdx.c | 29 +++++++++++++++++++--
arch/x86/virt/vmx/tdx/tdx_global_metadata.c | 23 +++++++++++++++-
4 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h
index 89e97d5761d89..d414064436221 100644
--- a/arch/x86/include/asm/tdx.h
+++ b/arch/x86/include/asm/tdx.h
@@ -118,6 +118,8 @@ static inline bool tdx_supports_runtime_update(const struct tdx_sys_info *sysinf
return sysinfo->features.tdx_features0 & TDX_FEATURES0_TD_PRESERVING;
}
+bool tdx_supports_dynamic_pamt(const struct tdx_sys_info *sysinfo);
+
int tdx_guest_keyid_alloc(void);
u32 tdx_get_nr_guest_keyids(void);
void tdx_guest_keyid_free(unsigned int keyid);
diff --git a/arch/x86/include/asm/tdx_global_metadata.h b/arch/x86/include/asm/tdx_global_metadata.h
index 41150d546589c..2a42551fc33cd 100644
--- a/arch/x86/include/asm/tdx_global_metadata.h
+++ b/arch/x86/include/asm/tdx_global_metadata.h
@@ -21,6 +21,9 @@ struct tdx_sys_info_tdmr {
u16 pamt_4k_entry_size;
u16 pamt_2m_entry_size;
u16 pamt_1g_entry_size;
+
+ /* Optional metadata, if Dynamic PAMT is supported */
+ u8 pamt_page_bitmap_entry_bits;
};
struct tdx_sys_info_td_ctrl {
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index e77a5265c2c84..f395f1fe95093 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -510,6 +510,18 @@ static __init int fill_out_tdmrs(struct list_head *tmb_list,
return 0;
}
+static __init unsigned long tdmr_get_pamt_bitmap_sz(struct tdmr_info *tdmr)
+{
+ unsigned long pamt_sz, nr_pamt_entries;
+ int bits_per_entry;
+
+ bits_per_entry = tdx_sysinfo.tdmr.pamt_page_bitmap_entry_bits;
+ nr_pamt_entries = tdmr->size >> PAGE_SHIFT;
+ pamt_sz = DIV_ROUND_UP(nr_pamt_entries * bits_per_entry, BITS_PER_BYTE);
+
+ return PAGE_ALIGN(pamt_sz);
+}
+
/*
* Calculate PAMT size given a TDMR and a page size. The returned
* PAMT size is always aligned up to 4K page boundary.
@@ -578,9 +590,16 @@ static __init int tdmr_set_up_pamt(struct tdmr_info *tdmr,
* Calculate the PAMT size for each TDX supported page size
* and the total PAMT size.
*/
- tdmr->pamt_4k_size = tdmr_get_pamt_sz(tdmr, TDX_PS_4K);
- tdmr->pamt_2m_size = tdmr_get_pamt_sz(tdmr, TDX_PS_2M);
tdmr->pamt_1g_size = tdmr_get_pamt_sz(tdmr, TDX_PS_1G);
+ tdmr->pamt_2m_size = tdmr_get_pamt_sz(tdmr, TDX_PS_2M);
+
+ if (tdx_supports_dynamic_pamt(&tdx_sysinfo)) {
+ /* With Dynamic PAMT, PAMT_4K is replaced with a bitmap */
+ tdmr->pamt_4k_size = tdmr_get_pamt_bitmap_sz(tdmr);
+ } else {
+ tdmr->pamt_4k_size = tdmr_get_pamt_sz(tdmr, TDX_PS_4K);
+ }
+
tdmr_pamt_size = tdmr->pamt_4k_size + tdmr->pamt_2m_size + tdmr->pamt_1g_size;
/*
@@ -1969,6 +1988,12 @@ u64 tdh_phymem_page_wbinvd_hkid(u64 hkid, kvm_pfn_t pfn)
}
EXPORT_SYMBOL_FOR_KVM(tdh_phymem_page_wbinvd_hkid);
+bool tdx_supports_dynamic_pamt(const struct tdx_sys_info *sysinfo)
+{
+ /* To be enabled when kernel is ready. */
+ return false;
+}
+
void tdx_sys_disable(void)
{
struct tdx_module_args args = {};
diff --git a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c b/arch/x86/virt/vmx/tdx/tdx_global_metadata.c
index e49c300f23d43..8393d2aa59dbe 100644
--- a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c
+++ b/arch/x86/virt/vmx/tdx/tdx_global_metadata.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Automatically generated functions to read TDX global metadata.
+ * Functions to read TDX global metadata.
*
* This file doesn't compile on its own as it lacks of inclusion
* of SEAMCALL wrapper primitive which reads global metadata.
@@ -33,6 +33,18 @@ static __init int get_tdx_sys_info_features(struct tdx_sys_info_features *sysinf
return ret;
}
+static __init int get_tdx_sys_info_tdmr_dpamt(struct tdx_sys_info_tdmr *sysinfo_tdmr)
+{
+ int ret;
+ u64 val;
+
+ ret = read_sys_metadata_field(0x9100000100000013, &val);
+ if (!ret)
+ sysinfo_tdmr->pamt_page_bitmap_entry_bits = val;
+
+ return ret;
+}
+
static __init int get_tdx_sys_info_tdmr(struct tdx_sys_info_tdmr *sysinfo_tdmr)
{
int ret = 0;
@@ -129,5 +141,14 @@ static __init int get_tdx_sys_info(struct tdx_sys_info *sysinfo)
ret = ret ?: get_tdx_sys_info_td_ctrl(&sysinfo->td_ctrl);
ret = ret ?: get_tdx_sys_info_td_conf(&sysinfo->td_conf);
+ /*
+ * The kernel supports using TDX without Dynamic PAMT, so
+ * avoid reporting failure if it's not supported. Don't try
+ * to support buggy TDX modules that advertise Dynamic PAMT
+ * but don't expose the metadata.
+ */
+ if (!ret && tdx_supports_dynamic_pamt(sysinfo))
+ ret = get_tdx_sys_info_tdmr_dpamt(&sysinfo->tdmr);
+
return ret;
}
--
2.54.0
^ permalink raw reply related
* [PATCH v7 01/11] x86/virt/tdx: Simplify PAMT layout calculation
From: Rick Edgecombe @ 2026-07-18 1:44 UTC (permalink / raw)
To: bp, dave.hansen, hpa, kas, kvm, linux-coco, linux-doc,
linux-kernel, mingo, nik.borisov, pbonzini, seanjc, tglx,
vannapurve, x86, chao.gao, yan.y.zhao, kai.huang, tony.lindgren,
binbin.wu
Cc: rick.p.edgecombe, Binbin Wu
In-Reply-To: <20260718014500.2231262-1-rick.p.edgecombe@intel.com>
For each memory region that the TDX module might use (called TDMR), three
separate traditional PAMT allocations are needed. There is one for each
supported page size (1GB, 2MB, 4KB). These store information on each page
in the TDMR. In Linux, they are allocated out of one physically contiguous
block, in order to more efficiently use some internal TDX module
bookkeeping resources. So some simple math is needed to break the single
large allocation into three smaller allocations for each page size.
There are some commonalities in the math needed to calculate the base and
size for each smaller allocation, and so an effort was made to share logic
across the three. Unfortunately doing this turned out unnaturally tortured,
with a loop iterating over the three page sizes, only to call into a
function with case statements for each page size. In the future Dynamic
PAMT will add more logic that is special to the 4KB page size, making the
benefit of the math sharing even more questionable.
Three is not a very high number, so get rid of the loop and just duplicate
the small calculation three times. In doing so, setup for future Dynamic
PAMT changes.
Since the loop that iterates over it is gone, further simplify the code by
dropping the array of intermediate size and base storage. Just store the
values to their final locations. Accept the small complication of having
to clear tdmr->pamt_4k_base in the error path, so that tdmr_do_pamt_func()
will not try to operate on the TDMR struct when attempting to free it.
AI was used under supervision to collect/apply feedback, review code and
workshop logs.
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com>
Reviewed-by: Kiryl Shutsemau (Meta) <kas@kernel.org>
Reviewed-by: Chao Gao <chao.gao@intel.com>
Reviewed-by: Yan Zhao <yan.y.zhao@intel.com>
Reviewed-by: Tony Lindgren <tony.lindgren@linux.intel.com>
---
v7:
- Remove accidentital whitespace changes (Kiryl)
- Drop stale sentence in log (Chao)
- Better patch subject (Yan)
- Drop Assisted-by tag and cover AI use in log (Dave)
v6:
- Drop {} by moving a comment (Binbin)
- Log tweaks
---
arch/x86/virt/vmx/tdx/tdx.c | 90 ++++++++++++-------------------------
1 file changed, 28 insertions(+), 62 deletions(-)
diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c
index 42df8ea464c47..e77a5265c2c84 100644
--- a/arch/x86/virt/vmx/tdx/tdx.c
+++ b/arch/x86/virt/vmx/tdx/tdx.c
@@ -514,31 +514,21 @@ static __init int fill_out_tdmrs(struct list_head *tmb_list,
* Calculate PAMT size given a TDMR and a page size. The returned
* PAMT size is always aligned up to 4K page boundary.
*/
-static __init unsigned long tdmr_get_pamt_sz(struct tdmr_info *tdmr, int pgsz,
- u16 pamt_entry_size)
+static __init unsigned long tdmr_get_pamt_sz(struct tdmr_info *tdmr, int pgsz)
{
unsigned long pamt_sz, nr_pamt_entries;
+ const int tdx_pg_size_shift[TDX_PS_NR] = { PAGE_SHIFT, PMD_SHIFT, PUD_SHIFT };
+ const u16 pamt_entry_size[TDX_PS_NR] = {
+ tdx_sysinfo.tdmr.pamt_4k_entry_size,
+ tdx_sysinfo.tdmr.pamt_2m_entry_size,
+ tdx_sysinfo.tdmr.pamt_1g_entry_size,
+ };
- switch (pgsz) {
- case TDX_PS_4K:
- nr_pamt_entries = tdmr->size >> PAGE_SHIFT;
- break;
- case TDX_PS_2M:
- nr_pamt_entries = tdmr->size >> PMD_SHIFT;
- break;
- case TDX_PS_1G:
- nr_pamt_entries = tdmr->size >> PUD_SHIFT;
- break;
- default:
- WARN_ON_ONCE(1);
- return 0;
- }
+ nr_pamt_entries = tdmr->size >> tdx_pg_size_shift[pgsz];
+ pamt_sz = nr_pamt_entries * pamt_entry_size[pgsz];
- pamt_sz = nr_pamt_entries * pamt_entry_size;
/* TDX requires PAMT size must be 4K aligned */
- pamt_sz = ALIGN(pamt_sz, PAGE_SIZE);
-
- return pamt_sz;
+ return PAGE_ALIGN(pamt_sz);
}
/*
@@ -576,15 +566,11 @@ static __init int tdmr_get_nid(struct tdmr_info *tdmr, struct list_head *tmb_lis
* within @tdmr, and set up PAMTs for @tdmr.
*/
static __init int tdmr_set_up_pamt(struct tdmr_info *tdmr,
- struct list_head *tmb_list,
- u16 pamt_entry_size[])
+ struct list_head *tmb_list)
{
- unsigned long pamt_base[TDX_PS_NR];
- unsigned long pamt_size[TDX_PS_NR];
- unsigned long tdmr_pamt_base;
unsigned long tdmr_pamt_size;
struct page *pamt;
- int pgsz, nid;
+ int nid;
nid = tdmr_get_nid(tdmr, tmb_list);
@@ -592,12 +578,10 @@ static __init int tdmr_set_up_pamt(struct tdmr_info *tdmr,
* Calculate the PAMT size for each TDX supported page size
* and the total PAMT size.
*/
- tdmr_pamt_size = 0;
- for (pgsz = TDX_PS_4K; pgsz < TDX_PS_NR; pgsz++) {
- pamt_size[pgsz] = tdmr_get_pamt_sz(tdmr, pgsz,
- pamt_entry_size[pgsz]);
- tdmr_pamt_size += pamt_size[pgsz];
- }
+ tdmr->pamt_4k_size = tdmr_get_pamt_sz(tdmr, TDX_PS_4K);
+ tdmr->pamt_2m_size = tdmr_get_pamt_sz(tdmr, TDX_PS_2M);
+ tdmr->pamt_1g_size = tdmr_get_pamt_sz(tdmr, TDX_PS_1G);
+ tdmr_pamt_size = tdmr->pamt_4k_size + tdmr->pamt_2m_size + tdmr->pamt_1g_size;
/*
* Allocate one chunk of physically contiguous memory for all
@@ -606,25 +590,17 @@ static __init int tdmr_set_up_pamt(struct tdmr_info *tdmr,
*/
pamt = alloc_contig_pages(tdmr_pamt_size >> PAGE_SHIFT, GFP_KERNEL,
nid, &node_online_map);
+
+ /*
+ * tdmr->pamt_4k_base is still zero so the error
+ * path of the caller will skip freeing the pamt.
+ */
if (!pamt)
return -ENOMEM;
- /*
- * Break the contiguous allocation back up into the
- * individual PAMTs for each page size.
- */
- tdmr_pamt_base = page_to_pfn(pamt) << PAGE_SHIFT;
- for (pgsz = TDX_PS_4K; pgsz < TDX_PS_NR; pgsz++) {
- pamt_base[pgsz] = tdmr_pamt_base;
- tdmr_pamt_base += pamt_size[pgsz];
- }
-
- tdmr->pamt_4k_base = pamt_base[TDX_PS_4K];
- tdmr->pamt_4k_size = pamt_size[TDX_PS_4K];
- tdmr->pamt_2m_base = pamt_base[TDX_PS_2M];
- tdmr->pamt_2m_size = pamt_size[TDX_PS_2M];
- tdmr->pamt_1g_base = pamt_base[TDX_PS_1G];
- tdmr->pamt_1g_size = pamt_size[TDX_PS_1G];
+ tdmr->pamt_4k_base = page_to_phys(pamt);
+ tdmr->pamt_2m_base = tdmr->pamt_4k_base + tdmr->pamt_4k_size;
+ tdmr->pamt_1g_base = tdmr->pamt_2m_base + tdmr->pamt_2m_size;
return 0;
}
@@ -655,10 +631,7 @@ static __init void tdmr_do_pamt_func(struct tdmr_info *tdmr,
tdmr_get_pamt(tdmr, &pamt_base, &pamt_size);
/* Do nothing if PAMT hasn't been allocated for this TDMR */
- if (!pamt_size)
- return;
-
- if (WARN_ON_ONCE(!pamt_base))
+ if (!pamt_base)
return;
pamt_func(pamt_base, pamt_size);
@@ -684,14 +657,12 @@ static __init void tdmrs_free_pamt_all(struct tdmr_info_list *tdmr_list)
/* Allocate and set up PAMTs for all TDMRs */
static __init int tdmrs_set_up_pamt_all(struct tdmr_info_list *tdmr_list,
- struct list_head *tmb_list,
- u16 pamt_entry_size[])
+ struct list_head *tmb_list)
{
int i, ret = 0;
for (i = 0; i < tdmr_list->nr_consumed_tdmrs; i++) {
- ret = tdmr_set_up_pamt(tdmr_entry(tdmr_list, i), tmb_list,
- pamt_entry_size);
+ ret = tdmr_set_up_pamt(tdmr_entry(tdmr_list, i), tmb_list);
if (ret)
goto err;
}
@@ -968,18 +939,13 @@ static __init int construct_tdmrs(struct list_head *tmb_list,
struct tdmr_info_list *tdmr_list,
struct tdx_sys_info_tdmr *sysinfo_tdmr)
{
- u16 pamt_entry_size[TDX_PS_NR] = {
- sysinfo_tdmr->pamt_4k_entry_size,
- sysinfo_tdmr->pamt_2m_entry_size,
- sysinfo_tdmr->pamt_1g_entry_size,
- };
int ret;
ret = fill_out_tdmrs(tmb_list, tdmr_list);
if (ret)
return ret;
- ret = tdmrs_set_up_pamt_all(tdmr_list, tmb_list, pamt_entry_size);
+ ret = tdmrs_set_up_pamt_all(tdmr_list, tmb_list);
if (ret)
return ret;
--
2.54.0
^ permalink raw reply related
* [PATCH v7 00/11] Dynamic PAMT
From: Rick Edgecombe @ 2026-07-18 1:44 UTC (permalink / raw)
To: bp, dave.hansen, hpa, kas, kvm, linux-coco, linux-doc,
linux-kernel, mingo, nik.borisov, pbonzini, seanjc, tglx,
vannapurve, x86, chao.gao, yan.y.zhao, kai.huang, tony.lindgren,
binbin.wu
Cc: rick.p.edgecombe
Hi,
This is hopefully the last revision of Dynamic PAMT TDX series. Thank you
to all the reviewers that helped polish off the last rough spots in v6[0].
Sean please consider acking the two KVM patches. Dave, please consider
taking through tip.
Kiryl and Vishal, I left your RBs because the other changes were trivial.
Please shout if you prefer to drop them.
Background
==========
Dynamic PAMT is a TDX feature that allows saving memory by allocating some
of its page tracking metadata dynamically, instead of statically at boot.
These static allocations take roughly 0.4% of system memory. The savings
are variable depending on system and TDX usage, but could be up to 100x.
For more Dynamic PAMT background, please refer to [1]. For more analysis
of the savings in different scenarios, see the v6 coverleter[0].
It occurred to me that since the Dynamic PAMT effort began, RAM has become
much more expensive. Consequently, this feature is even more valuable now.
It would be good to enable it for TDX users.
Changes
=======
Besides the polishing type comments, there were two substantial ones. These
ended up getting addressed with the same small change.
Chao asked why the TDX module doesn't do the keyid range checks itself
that it requires, and then only expose the Dynamic PAMT feature0 bit when
it actually can support Dynamic PAMT. It seems the TDX module is open to
this change, but in any case, no modules exist today that have it. Since
Dynamic PAMT enablement failure will cause TDX enablement to fail, Dynamic
PAMT is made an opt-in for now by adding a kernel parameter for it. Then
the kernel side keyid checks are dropped.
The other significant comment was Dave asking whether the "x86/virt/tdx:
Optimize tdx_pamt_get/put()" was really needed. Later we discussed offline
to keep the patch for the sake of maintaining performance and being kind
to KVM's efforts to fault under a shared lock. However, now that the
feature requires an opt-in, it could be for limited use and not disturb any
kernel upgraders. Then the optimization patch actually does become more
optional. So here it is moved to the end. I think the patch is in good
shape, but if there are any doubts we can drop it out of the initial
support.
Base
====
This is based on v7.2-rc3. A full branch can be found here: [2].
Testing
=======
This series was tested in the usual suite, and also with the optimization
patch removed.
[0] https://lore.kernel.org/lkml/20260526023515.288829-1-rick.p.edgecombe@intel.com/
[1] https://lore.kernel.org/lkml/20250918232224.2202592-1-rick.p.edgecombe@intel.com/
[2] https://github.com/intel-staging/tdx/tree/dpamt_v7
Kiryl Shutsemau (9):
x86/virt/tdx: Allocate page bitmap for Dynamic PAMT
x86/virt/tdx: Add tdx_alloc/free_control_page() helpers
x86/virt/tdx: Allocate refcounts for Dynamic PAMT memory
x86/virt/tdx: Handle multiple callers in tdx_pamt_get/put()
KVM: TDX: Allocate PAMT memory for TD and vCPU control structures
KVM: TDX: Get/put PAMT pages when (un)mapping private memory
x86/virt/tdx: Enable Dynamic PAMT
Documentation/x86: Add documentation for TDX's Dynamic PAMT
x86/virt/tdx: Optimize tdx_pamt_get/put()
Rick Edgecombe (2):
x86/virt/tdx: Simplify PAMT layout calculation
x86/tdx: Add APIs to support Dynamic PAMT ops from KVM's fault path
.../admin-guide/kernel-parameters.txt | 10 +
Documentation/arch/x86/tdx.rst | 28 ++
arch/x86/include/asm/kvm-x86-ops.h | 1 +
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/include/asm/tdx.h | 26 +
arch/x86/include/asm/tdx_global_metadata.h | 3 +
arch/x86/kvm/mmu/mmu.c | 4 +
arch/x86/kvm/vmx/tdx.c | 98 ++--
arch/x86/kvm/vmx/tdx.h | 2 +
arch/x86/virt/vmx/tdx/tdx.c | 452 +++++++++++++++---
arch/x86/virt/vmx/tdx/tdx.h | 2 +
arch/x86/virt/vmx/tdx/tdx_global_metadata.c | 23 +-
12 files changed, 559 insertions(+), 92 deletions(-)
--
2.54.0
^ permalink raw reply
* Re: [PATCH v2 0/2] mm/zswap: Fixes and improves the zswap global shrinker
From: Yosry Ahmed @ 2026-07-18 1:28 UTC (permalink / raw)
To: Andrew Morton
Cc: Hao Jia, tj, hannes, shakeel.butt, mhocko, mkoutny, nphamcs,
chengming.zhou, muchun.song, roman.gushchin, linux-mm,
linux-kernel, linux-doc, Hao Jia
In-Reply-To: <20260717181839.c94d0335ccef0084707d3d85@linux-foundation.org>
On Fri, Jul 17, 2026 at 6:18 PM Andrew Morton <akpm@linux-foundation.org> wrote:
>
> On Fri, 17 Jul 2026 16:51:49 +0800 Hao Jia <jiahao.kernel@gmail.com> wrote:
>
> > This series fixes and improves the zswap global shrinker (shrink_worker()):
> > Patch 1: Fix missing global shrinker when memory cgroup is disabled.
> > Patch 2: Extend shrink_memcg() to support batch writeback and update its
> > return value semantics, thereby improving the writeback efficiency
> > in the shrink_worker() path.
>
> Thanks.
>
> [1/2] is a cc:stable fix so it isn't really appropriate to combine this
> with [2/2] which doesn't fix any bugs. Because the two patches may
> take different paths into mainline, with different timings. But that's
> OK, I can deal with the splitup if needed.
Thank you!
>
> The [1/2] changelog lacks a description of how the flaw impacts users.
> Please describe this fully and maintain that info within the
> changelogging. This info helps -stable maintainers and others
> understand why we're proposing a backport and helps myself and others
> with timing decisions.
The first line in the changelog should be sufficient imo: "Zswap
writeback on hitting the pool limit is broken when memory cgroup is
disabled"
^ permalink raw reply
* Re: [PATCH v2 0/2] mm/zswap: Fixes and improves the zswap global shrinker
From: Yosry Ahmed @ 2026-07-18 1:22 UTC (permalink / raw)
To: Andrew Morton
Cc: Hao Jia, tj, hannes, shakeel.butt, mhocko, mkoutny, nphamcs,
chengming.zhou, muchun.song, roman.gushchin, linux-mm,
linux-kernel, linux-doc, Hao Jia
In-Reply-To: <20260717181839.c94d0335ccef0084707d3d85@linux-foundation.org>
On Fri, Jul 17, 2026 at 6:18 PM Andrew Morton <akpm@linux-foundation.org> wrote:
>
> On Fri, 17 Jul 2026 16:51:49 +0800 Hao Jia <jiahao.kernel@gmail.com> wrote:
>
> > This series fixes and improves the zswap global shrinker (shrink_worker()):
> > Patch 1: Fix missing global shrinker when memory cgroup is disabled.
> > Patch 2: Extend shrink_memcg() to support batch writeback and update its
> > return value semantics, thereby improving the writeback efficiency
> > in the shrink_worker() path.
>
> Thanks.
>
> [1/2] is a cc:stable fix so it isn't really appropriate to combine this
> with [2/2] which doesn't fix any bugs. Because the two patches may
> take different paths into mainline, with different timings. But that's
> OK, I can deal with the splitup if needed.
>
> The [1/2] changelog lacks a description of how the flaw impacts users.
> Please describe this fully and maintain that info within the
> changelogging. This info helps -stable maintainers and others
> understand why we're proposing a backport and helps myself and others
> with timing decisions.
>
> Finally, AI review might have found an issue:
> https://sashiko.dev/#/patchset/20260717085151.22822-1-jiahao.kernel@gmail.com
We discussed this one in the previous version, it's a theoretical
scenario that can already happen today.
^ permalink raw reply
* Re: [PATCH v2 0/2] mm/zswap: Fixes and improves the zswap global shrinker
From: Andrew Morton @ 2026-07-18 1:18 UTC (permalink / raw)
To: Hao Jia
Cc: tj, hannes, shakeel.butt, mhocko, yosry, mkoutny, nphamcs,
chengming.zhou, muchun.song, roman.gushchin, linux-mm,
linux-kernel, linux-doc, Hao Jia
In-Reply-To: <20260717085151.22822-1-jiahao.kernel@gmail.com>
On Fri, 17 Jul 2026 16:51:49 +0800 Hao Jia <jiahao.kernel@gmail.com> wrote:
> This series fixes and improves the zswap global shrinker (shrink_worker()):
> Patch 1: Fix missing global shrinker when memory cgroup is disabled.
> Patch 2: Extend shrink_memcg() to support batch writeback and update its
> return value semantics, thereby improving the writeback efficiency
> in the shrink_worker() path.
Thanks.
[1/2] is a cc:stable fix so it isn't really appropriate to combine this
with [2/2] which doesn't fix any bugs. Because the two patches may
take different paths into mainline, with different timings. But that's
OK, I can deal with the splitup if needed.
The [1/2] changelog lacks a description of how the flaw impacts users.
Please describe this fully and maintain that info within the
changelogging. This info helps -stable maintainers and others
understand why we're proposing a backport and helps myself and others
with timing decisions.
Finally, AI review might have found an issue:
https://sashiko.dev/#/patchset/20260717085151.22822-1-jiahao.kernel@gmail.com
^ permalink raw reply
* Re: [PATCH v12 02/29] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state
From: Mark Brown @ 2026-07-18 0:35 UTC (permalink / raw)
To: Mark Rutland
Cc: Marc Zyngier, Joey Gouly, Catalin Marinas, Suzuki K Poulose,
Will Deacon, Paolo Bonzini, Jonathan Corbet, Shuah Khan,
Oliver Upton, Dave Martin, Fuad Tabba, Ben Horgan,
Jean-Philippe Brucker, linux-arm-kernel, kvmarm, linux-kernel,
kvm, linux-doc, linux-kselftest, Peter Maydell, Eric Auger
In-Reply-To: <15a9ae14-395d-472a-a5be-9e46524fb493@sirena.org.uk>
[-- Attachment #1: Type: text/plain, Size: 1017 bytes --]
On Thu, Jul 16, 2026 at 04:28:02PM +0100, Mark Brown wrote:
> On Thu, Jul 16, 2026 at 11:52:36AM +0100, Mark Rutland wrote:
> > > if (test_thread_flag(TIF_SME)) {
> > > - unsigned long vq = sve_vq_from_vl(sme_vl);
> > > - sysreg_clear_set_s(SYS_SMCR_EL1, SMCR_ELx_LEN, vq - 1);
> > > + sysreg_cond_update_s(SYS_SMCR_EL1, task_smcr(current));
> > > + isb();
> > > }
> > What's the ISB for? That mysteriously appeared in v11 without
> > explanation. It wasn't in the original code, prior versions of the
> > series, or my suggested rework with the task_smcr() helper.
> > I don't believe it's necessary to add an ISB here.
> I can't remember or figure it out, I'll delete.
Actually I remembered: while SCMR_EL1.LEN is self synchronising the
"without the need for explict synchronization" wording is not present
for SMCR_EL1.{FA64,EZT0} and this is no longer explicitly just an update
of LEN. It's possible I'm being overly paranoid here, I'll leave the
isb() and add a comment for the next version.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v9 00/10] tracing: wprobe: x86: Add wprobe for watchpoint
From: Masami Hiramatsu @ 2026-07-17 23:47 UTC (permalink / raw)
To: Borislav Petkov
Cc: Steven Rostedt, Peter Zijlstra, Ingo Molnar, x86, Jinchao Wang,
Mathieu Desnoyers, Thomas Gleixner, Dave Hansen, H . Peter Anvin,
Alexander Shishkin, Ian Rogers, linux-kernel, linux-trace-kernel,
linux-doc, linux-perf-users
In-Reply-To: <20260717162857.GAalpYSaZ_emTMUEEW@fat_crate.local>
On Fri, 17 Jul 2026 09:28:57 -0700
Borislav Petkov <bp@alien8.de> wrote:
> Hi,
>
> On Fri, Jul 17, 2026 at 11:19:30PM +0900, Masami Hiramatsu (Google) wrote:
> > Here is the 9th version of the series for adding new wprobe (watch probe)
>
> any chance you won't blast out your patchset every day?
Ah, sorry about that. I'll rate limit myself this weekend on this series.
(I hope I have fixed most of major issues...)
Thanks,
>
> Thx.
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
--
Masami Hiramatsu (Google) <mhiramat@kernel.org>
^ permalink raw reply
* Re: [PATCH v7 12/12] Documentation: PCI: Add documentation for Live Update
From: Pasha Tatashin @ 2026-07-17 23:38 UTC (permalink / raw)
To: David Matlack
Cc: kexec, linux-doc, linux-kernel, linux-mm, linux-pci,
Adithya Jayachandran, Alexander Graf, Alex Williamson,
Bjorn Helgaas, Chris Li, David Rientjes, Jacob Pan,
Jason Gunthorpe, Jonathan Corbet, Josh Hilke, Leon Romanovsky,
Lukas Wunner, Mike Rapoport, Parav Pandit, Pasha Tatashin,
Pranjal Shrivastava, Pratyush Yadav, Saeed Mahameed,
Samiullah Khawaja, Shuah Khan, Vipin Sharma, William Tu, Yi Liu
In-Reply-To: <20260710212616.1351130-13-dmatlack@google.com>
On Fri, 10 Jul 2026 21:26:15 +0000, David Matlack <dmatlack@google.com> wrote:
> diff --git a/Documentation/PCI/liveupdate.rst b/Documentation/PCI/liveupdate.rst
> new file mode 100644
> index 000000000000..eba55f8a92ae
> --- /dev/null
> +++ b/Documentation/PCI/liveupdate.rst
> @@ -0,0 +1,29 @@
> +.. SPDX-License-Identifier: GPL-2.0-or-later
> +
> +===========================
> +PCI Support for Live Update
> +===========================
> +
> +.. kernel-doc:: drivers/pci/liveupdate.c
> + :doc: PCI Live Update
> +
> +Driver API
> +==========
> +
> +.. kernel-doc:: drivers/pci/liveupdate.c
> + :export:
I think you need:
+Internal API
+============
+
+.. kernel-doc:: drivers/pci/liveupdate.c
+ :internal:
+
In order to include docs for structs such as pci_flb_outgoing, etc.
--
Pasha Tatashin <pasha.tatashin@soleen.com>
^ permalink raw reply
* Re: [PATCH v7 11/12] PCI: liveupdate: Do not disable bus mastering on preserved devices during kexec
From: Pasha Tatashin @ 2026-07-17 23:32 UTC (permalink / raw)
To: David Matlack
Cc: kexec, linux-doc, linux-kernel, linux-mm, linux-pci,
Adithya Jayachandran, Alexander Graf, Alex Williamson,
Bjorn Helgaas, Chris Li, David Rientjes, Jacob Pan,
Jason Gunthorpe, Jonathan Corbet, Josh Hilke, Leon Romanovsky,
Lukas Wunner, Mike Rapoport, Parav Pandit, Pasha Tatashin,
Pranjal Shrivastava, Pratyush Yadav, Saeed Mahameed,
Samiullah Khawaja, Shuah Khan, Vipin Sharma, William Tu, Yi Liu
In-Reply-To: <20260710212616.1351130-12-dmatlack@google.com>
On Fri, 10 Jul 2026 21:26:14 +0000, David Matlack <dmatlack@google.com> wrote:
> Do not disable bus mastering on outgoing preserved devices during
> pci_device_shutdown() for kexec.
>
> Preserved devices must be allowed to perform memory transactions during
> a Live Update to ensure continuous operation. Clearing the bus
> mastering bit would prevent these devices from issuing any memory
> requests while the new kernel boots.
>
> [...]
Reviewed-by: Pasha Tatashin <pasha.tatashin@soleen.com>
--
Pasha Tatashin <pasha.tatashin@soleen.com>
^ permalink raw reply
* Re: [PATCH v7 10/12] PCI: liveupdate: Freeze preservation status during shutdown
From: Pasha Tatashin @ 2026-07-17 23:30 UTC (permalink / raw)
To: David Matlack
Cc: kexec, linux-doc, linux-kernel, linux-mm, linux-pci,
Adithya Jayachandran, Alexander Graf, Alex Williamson,
Bjorn Helgaas, Chris Li, David Rientjes, Jacob Pan,
Jason Gunthorpe, Jonathan Corbet, Josh Hilke, Leon Romanovsky,
Lukas Wunner, Mike Rapoport, Parav Pandit, Pasha Tatashin,
Pranjal Shrivastava, Pratyush Yadav, Saeed Mahameed,
Samiullah Khawaja, Shuah Khan, Vipin Sharma, William Tu, Yi Liu
In-Reply-To: <20260710212616.1351130-11-dmatlack@google.com>
On Fri, 10 Jul 2026 21:26:13 +0000, David Matlack <dmatlack@google.com> wrote:
> Freeze a device's outgoing preservation status (preserved or not
> preserved) during shutdown. This enables the PCI core and drivers to
> safely make decisions based on the device's preservation status during
> shutdown.
>
> Note that pci_liveupdate_freeze() is triggered by the PCI core rather
> than from drivers participating in Live Update so that all devices can
> have their status frozen (i.e. prevent non-preserved devices from
> getting preserved late).
>
> [...]
Reviewed-by: Pasha Tatashin <pasha.tatashin@soleen.com>
--
Pasha Tatashin <pasha.tatashin@soleen.com>
^ permalink raw reply
* Re: [PATCH v7 09/12] PCI: liveupdate: Inherit ARI Forwarding Enable on preserved bridges
From: Pasha Tatashin @ 2026-07-17 23:29 UTC (permalink / raw)
To: David Matlack
Cc: kexec, linux-doc, linux-kernel, linux-mm, linux-pci,
Adithya Jayachandran, Alexander Graf, Alex Williamson,
Bjorn Helgaas, Chris Li, David Rientjes, Jacob Pan,
Jason Gunthorpe, Jonathan Corbet, Josh Hilke, Leon Romanovsky,
Lukas Wunner, Mike Rapoport, Parav Pandit, Pasha Tatashin,
Pranjal Shrivastava, Pratyush Yadav, Saeed Mahameed,
Samiullah Khawaja, Shuah Khan, Vipin Sharma, William Tu, Yi Liu
In-Reply-To: <20260710212616.1351130-10-dmatlack@google.com>
On Fri, 10 Jul 2026 21:26:12 +0000, David Matlack <dmatlack@google.com> wrote:
> diff --git a/drivers/pci/liveupdate.c b/drivers/pci/liveupdate.c
> index a95bfe5eff77..74a11e520f0d 100644
> --- a/drivers/pci/liveupdate.c
> +++ b/drivers/pci/liveupdate.c
> @@ -816,6 +820,20 @@ int pci_liveupdate_enable_acs(struct pci_dev *dev)
> return 0;
> }
>
> +int pci_liveupdate_configure_ari(struct pci_dev *dev)
> +{
> + u16 val;
> +
> + guard(rwsem_read)(&pci_liveupdate.rwsem);
> +
> + if (!dev->liveupdate.incoming)
> + return -EINVAL;
> +
> + pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &val);
> + dev->ari_enabled = !!(val & PCI_EXP_DEVCTL2_ARI);
unsigned int ari_enabled:1;
Sashiko asks a valid question, what protects other bits in this word
during modication? At a very list a comment is needed.
--
Pasha Tatashin <pasha.tatashin@soleen.com>
^ permalink raw reply
* [RFC] cxl: Device protocol AER injection
From: Terry Bowman @ 2026-07-17 22:57 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
This patch is intended to provide a method of testing the recently submitted
cxl series "cxl: Enable CXL PCIe Port Protocol Error handling and logging" found
here:
https://lore.kernel.org/linux-cxl/20260717222706.3540281-1-terry.bowman@amd.com/T/#md90ec1fdd1b374bf1e32e7736e2b3e34b328c701
The changes in this patch will allow CXL RAS protocol testing by injecting
AER errors using AER EINJ. The RAS register block status is updated
using a central function to augment RAS register block returned by
to_ras_base(). This supports all CXL devices including Root Ports,
Upstream Switch Ports, Downstream Switch Ports, Endpoints, and RCH
Downstream Ports.
Add debugfs-based CXL protocol error injection for testing CXL RAS
error handling paths. Injects CXL RAS protocol errors using AER internal
error inject interface via /sys/kernel/debug/cxl/aer_einj_inject.
RAS CXL status is set using to_ras_base() function override when kernel config
CONFIG_CXL_PROTO_AER_EINJ is enabled.
Usage:
echo "DDDD:BB:DD.F [UCE|CE] AER_STATUS RAS_STATUS [RCH]" > \
/sys/kernel/debug/cxl/aer_einj_inject
Move struct aer_error_inj and aer_inject() to linux/aer.h so CXL
can invoke AER injection directly. Export aer_inject() with
EXPORT_SYMBOL_GPL.
Make cxl_debugfs non-static in port.c and declare it extern in
core.h so the debugfs file can be created under the existing CXL
debugfs root.
Co-developed-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
drivers/cxl/Kconfig | 13 +++
drivers/cxl/core/core.h | 21 ++++
drivers/cxl/core/port.c | 2 +-
drivers/cxl/core/ras.c | 208 ++++++++++++++++++++++++++++++++++
drivers/cxl/core/ras_rch.c | 12 ++
drivers/pci/pcie/aer_inject.c | 29 ++---
include/linux/aer.h | 15 +++
7 files changed, 281 insertions(+), 19 deletions(-)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 80aeb0d556bd7..ef449228b2549 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -238,6 +238,19 @@ config CXL_RAS
def_bool y
depends on ACPI_APEI_GHES && PCIEAER && CXL_BUS
+config CXL_PROTO_AER_EINJ
+ bool "CXL: RAS Protocol Error Injection using AER EINJ"
+ depends on CXL_RAS
+ depends on PCIEAER_INJECT
+ help
+ Enable debugfs-based CXL protocol error injection. Writes to
+ /sys/kernel/debug/cxl/aer_einj_inject inject CXL RAS protocol
+ errors using the AER internal error inject interface.
+
+ This is a debug/test facility. Say N for production kernels.
+
+ If unsure say N.
+
config CXL_ATL
def_bool y
depends on CXL_REGION
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index a55a4e409feda..91910d2bb5d39 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -182,6 +182,9 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)
return port->uport_dev;
return &port->dev;
}
+
+extern struct dentry *cxl_debugfs;
+
#ifdef CONFIG_CXL_RAS
void cxl_ras_init(void);
void cxl_ras_exit(void);
@@ -244,4 +247,22 @@ int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
struct cxl_dport *dport);
+
+#ifdef CONFIG_CXL_PROTO_AER_EINJ
+
+#define AER_REGISTER_SIZE 5
+#define RAS_REGISTER_SIZE (CXL_RAS_CAPABILITY_LENGTH / sizeof(u32))
+
+struct cxl_aer_einj {
+ int correctable;
+ bool is_rch;
+ struct mutex *lock;
+ struct device *dev;
+ u32 aer_registers[AER_REGISTER_SIZE];
+ u32 ras_registers[RAS_REGISTER_SIZE];
+};
+
+extern struct cxl_aer_einj cxl_aer_einj;
+#endif
+
#endif /* __CXL_CORE_H__ */
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index a76f3ee05cba8..79657e5fddaac 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2501,7 +2501,7 @@ const struct bus_type cxl_bus_type = {
};
EXPORT_SYMBOL_NS_GPL(cxl_bus_type, "CXL");
-static struct dentry *cxl_debugfs;
+struct dentry *cxl_debugfs;
struct dentry *cxl_debugfs_create_dir(const char *dir)
{
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index d77208af41e03..d41deea899d30 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -3,6 +3,7 @@
#include <linux/pci.h>
#include <linux/aer.h>
+#include <linux/debugfs.h>
#include <cxl/event.h>
#include <cxlmem.h>
#include <cxlpci.h>
@@ -117,6 +118,195 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)
}
static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
+#if IS_ENABLED(CONFIG_CXL_PROTO_AER_EINJ)
+
+static DEFINE_MUTEX(cxl_aer_einj_mutex);
+
+struct cxl_aer_einj cxl_aer_einj = {
+ .lock = &cxl_aer_einj_mutex,
+};
+
+static const char cxl_aer_einj_usage[] =
+ "ssss:bb:dd.f [UCE|CE] AER_STATUS RAS_STATUS [RCH]\n";
+
+static int cxl_aer_inject_error(struct pci_dev *pdev, bool correctable,
+ u32 aer_status, u32 ras_status)
+{
+ /* RCD errors are signaled as internal errors on the associated RCEC */
+ if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) {
+ if (!pdev->rcec)
+ return -ENODEV;
+ pdev = pdev->rcec;
+ }
+
+ struct aer_error_inj einj = {
+ .bus = pdev->bus->number,
+ .dev = PCI_SLOT(pdev->devfn),
+ .fn = PCI_FUNC(pdev->devfn),
+ .domain = pci_domain_nr(pdev->bus),
+ };
+ int ret;
+ int aer_offset;
+ int ras_offset;
+
+ if (correctable) {
+ einj.cor_status = aer_status | PCI_ERR_COR_INTERNAL;
+ aer_offset = PCI_ERR_COR_STATUS / sizeof(u32);
+ ras_offset = CXL_RAS_CORRECTABLE_STATUS_OFFSET / sizeof(u32);
+ } else {
+ einj.uncor_status = aer_status | PCI_ERR_UNC_INTN;
+ aer_offset = PCI_ERR_UNCOR_STATUS / sizeof(u32);
+ ras_offset = CXL_RAS_UNCORRECTABLE_STATUS_OFFSET / sizeof(u32);
+ }
+
+ cxl_aer_einj.correctable = correctable;
+ cxl_aer_einj.aer_registers[aer_offset] = aer_status;
+ cxl_aer_einj.ras_registers[ras_offset] = ras_status;
+
+ ret = aer_inject(&einj);
+ if (ret) {
+ pr_err("cxl-einj: aer_inject failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static ssize_t cxl_aer_einj_write(struct file *file,
+ const char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char sbdf[16], severity[4], topology[4] = "";
+ unsigned int domain, bus, dev, fn;
+ u32 aer_status, ras_status;
+ struct cxl_dport *dport;
+ char buf[128];
+ int nargs;
+ int ret;
+
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+
+ if (count >= sizeof(buf)) {
+ pr_err("cxl-einj: input too long (%zu bytes, max %zu)\n", count, sizeof(buf) - 1);
+ return -EINVAL;
+ }
+
+ if (copy_from_user(buf, ubuf, count)) {
+ pr_err("cxl-einj: copy_from_user failed\n");
+ return -EFAULT;
+ }
+ buf[count] = '\0';
+
+ nargs = sscanf(buf, "%15s %3s %x %x %3s", sbdf, severity,
+ &aer_status, &ras_status, topology);
+ if (nargs < 4) {
+ pr_err("cxl-einj: expected format: <SBDF> <UCE|CE> <aer_status> <ras_status>\n");
+ return -EINVAL;
+ }
+
+ if (nargs == 5 && strcmp(topology, "RCH") != 0)
+ return -EINVAL;
+
+ if (strcmp(severity, "UCE") != 0 && strcmp(severity, "CE") != 0) {
+ pr_err("cxl-einj: expected 'UCE' or 'CE', got '%s'\n", severity);
+ return -EINVAL;
+ }
+
+ if (sscanf(sbdf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn) != 4) {
+ pr_err("cxl-einj: invalid SBDF format '%s', expected DDDD:BB:DD.F\n", sbdf);
+ return -EINVAL;
+ }
+
+ struct pci_dev *pdev __free(pci_dev_put) =
+ pci_get_domain_bus_and_slot(domain, bus, PCI_DEVFN(dev, fn));
+ if (!pdev) {
+ pr_err("cxl-einj: device %s not found\n", sbdf);
+ return -ENODEV;
+ }
+
+ guard(mutex)(cxl_aer_einj.lock);
+ cxl_aer_einj.dev = NULL;
+
+ struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_dev(&pdev->dev, &dport);
+ if (!port) {
+ dev_err(&pdev->dev, "cxl-einj: Failed to find CXL Port.\n");
+ return -ENODEV;
+ }
+
+ if (!to_ras_base(port, dport)) {
+ dev_err(&pdev->dev, "cxl-einj: RAS not initialized.\n");
+ return -ENODEV;
+ }
+
+ cxl_aer_einj.is_rch = (nargs == 5 && strcmp(topology, "RCH") == 0);
+ if (!cxl_aer_einj.is_rch)
+ pci_dev_get(pdev);
+ cxl_aer_einj.dev = cxl_aer_einj.is_rch ? pdev->dev.parent : &pdev->dev;
+ ret = cxl_aer_inject_error(pdev, strcmp(severity, "CE") == 0,
+ aer_status, ras_status);
+ if (ret) {
+ if (!cxl_aer_einj.is_rch)
+ pci_dev_put(pdev);
+ cxl_aer_einj.dev = NULL;
+ pr_err("cxl-einj: injection failed for %s: %d\n", sbdf, ret);
+ return ret;
+ }
+
+ return count;
+}
+
+static ssize_t cxl_aer_einj_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ return simple_read_from_buffer(ubuf, count, ppos,
+ cxl_aer_einj_usage,
+ sizeof(cxl_aer_einj_usage) - 1);
+}
+
+static const struct file_operations cxl_ras_error_fops = {
+ .owner = THIS_MODULE,
+ .read = cxl_aer_einj_read,
+ .write = cxl_aer_einj_write,
+ .llseek = default_llseek,
+};
+
+static void cxl_ras_create_debugfs(struct dentry *dir)
+{
+ debugfs_create_file("aer_einj_inject", 0600, dir, NULL,
+ &cxl_ras_error_fops);
+}
+
+static void __iomem *to_einj_ras_base(struct cxl_port *port, struct cxl_dport *dport)
+{
+ if (dport) {
+ if (cxl_aer_einj.is_rch) {
+ if (cxl_aer_einj.dev == dport->dport_dev) {
+ cxl_aer_einj.dev = NULL;
+ return (__force void __iomem *)cxl_aer_einj.ras_registers;
+ }
+ } else {
+ if (cxl_aer_einj.dev == dport->dport_dev) {
+ pci_dev_put(to_pci_dev(cxl_aer_einj.dev));
+ cxl_aer_einj.dev = NULL;
+ return (__force void __iomem *)cxl_aer_einj.ras_registers;
+ }
+ }
+ } else if (!cxl_aer_einj.is_rch) {
+ struct device *dev = is_cxl_endpoint(port) ?
+ port->uport_dev->parent : port->uport_dev;
+
+ if (dev_is_pci(dev) && cxl_aer_einj.dev == dev) {
+ pci_dev_put(to_pci_dev(cxl_aer_einj.dev));
+ cxl_aer_einj.dev = NULL;
+ return (__force void __iomem *)cxl_aer_einj.ras_registers;
+ }
+ }
+
+ return NULL;
+}
+#endif
+
static void cxl_unmask_proto_interrupts(struct device *dev)
{
struct pci_dev *pdev;
@@ -238,6 +428,14 @@ void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport)
if (!port)
return NULL;
+#if IS_ENABLED(CONFIG_CXL_PROTO_AER_EINJ)
+ if (cxl_aer_einj.dev) {
+ void __iomem *einj = to_einj_ras_base(port, dport);
+ if (einj)
+ return einj;
+ }
+#endif
+
if (dport)
return dport->regs.ras;
@@ -458,10 +656,20 @@ void cxl_ras_init(void)
cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work);
cxl_register_proto_err_work(&cxl_proto_err_work,
cxl_proto_err_do_flush);
+#if IS_ENABLED(CONFIG_CXL_PROTO_AER_EINJ)
+ cxl_ras_create_debugfs(cxl_debugfs);
+#endif
}
void cxl_ras_exit(void)
{
cxl_unregister_proto_err_work();
cxl_cper_unregister_prot_err_work();
+#if IS_ENABLED(CONFIG_CXL_PROTO_AER_EINJ)
+ if (cxl_aer_einj.dev) {
+ if (!cxl_aer_einj.is_rch)
+ pci_dev_put(to_pci_dev(cxl_aer_einj.dev));
+ cxl_aer_einj.dev = NULL;
+ }
+#endif
}
diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
index 14bb3bdb2d092..5071cf86e4a68 100644
--- a/drivers/cxl/core/ras_rch.c
+++ b/drivers/cxl/core/ras_rch.c
@@ -110,6 +110,14 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev)
if (!dport)
return;
+#if IS_ENABLED(CONFIG_CXL_PROTO_AER_EINJ)
+ if (cxl_aer_einj.is_rch && cxl_aer_einj.dev) {
+ severity = cxl_aer_einj.correctable ?
+ AER_CORRECTABLE : AER_FATAL;
+ goto handle_ras;
+ }
+#endif
+
if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
return;
@@ -117,6 +125,10 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev)
return;
pci_print_aer(pdev, severity, &aer_regs);
+
+#if IS_ENABLED(CONFIG_CXL_PROTO_AER_EINJ)
+handle_ras:
+#endif
if (severity == AER_CORRECTABLE)
cxl_handle_cor_ras(dport->port, dport,
to_ras_base(port, dport), pdev->dsn);
diff --git a/drivers/pci/pcie/aer_inject.c b/drivers/pci/pcie/aer_inject.c
index 09bfc7194ef31..b313adef680ae 100644
--- a/drivers/pci/pcie/aer_inject.c
+++ b/drivers/pci/pcie/aer_inject.c
@@ -14,6 +14,7 @@
#define dev_fmt(fmt) "aer_inject: " fmt
+#include <linux/aer.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -31,19 +32,6 @@
static bool aer_mask_override;
module_param(aer_mask_override, bool, 0);
-struct aer_error_inj {
- u8 bus;
- u8 dev;
- u8 fn;
- u32 uncor_status;
- u32 cor_status;
- u32 header_log0;
- u32 header_log1;
- u32 header_log2;
- u32 header_log3;
- u32 domain;
-};
-
struct aer_error {
struct list_head list;
u32 domain;
@@ -316,7 +304,7 @@ static int pci_bus_set_aer_ops(struct pci_bus *bus)
return 0;
}
-static int aer_inject(struct aer_error_inj *einj)
+int aer_inject(struct aer_error_inj *einj)
{
struct aer_error *err, *rperr;
struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
@@ -332,10 +320,14 @@ static int aer_inject(struct aer_error_inj *einj)
dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
if (!dev)
return -ENODEV;
- rpdev = pcie_find_root_port(dev);
- /* If Root Port not found, try to find an RCEC */
- if (!rpdev)
- rpdev = dev->rcec;
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC)
+ rpdev = dev;
+ else {
+ rpdev = pcie_find_root_port(dev);
+ /* If Root Port not found, try to find an RCEC */
+ if (!rpdev)
+ rpdev = dev->rcec;
+ }
if (!rpdev) {
pci_err(dev, "Neither Root Port nor RCEC found\n");
ret = -ENODEV;
@@ -482,6 +474,7 @@ static int aer_inject(struct aer_error_inj *einj)
pci_dev_put(dev);
return ret;
}
+EXPORT_SYMBOL_GPL(aer_inject);
static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
size_t usize, loff_t *off)
diff --git a/include/linux/aer.h b/include/linux/aer.h
index b3657b80564b9..65c22ba597657 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -27,6 +27,21 @@
struct pci_dev;
struct work_struct;
+struct aer_error_inj {
+ u8 bus;
+ u8 dev;
+ u8 fn;
+ u32 uncor_status;
+ u32 cor_status;
+ u32 header_log0;
+ u32 header_log1;
+ u32 header_log2;
+ u32 header_log3;
+ u32 domain;
+};
+
+int aer_inject(struct aer_error_inj *einj);
+
struct pcie_tlp_log {
union {
u32 dw[PCIE_STD_MAX_TLP_HEADERLOG];
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 1/2] x86/resctrl, Documentation: Keep mbm_assign_mode "default" on boot
From: Reinette Chatre @ 2026-07-17 22:56 UTC (permalink / raw)
To: Babu Moger, tony.luck, bp
Cc: x86, Dave.Martin, james.morse, corbet, skhan, tglx, mingo,
dave.hansen, hpa, linux-kernel, linux-doc, eranian, peternewman
In-Reply-To: <8cb66e18e32e4087a9712c1e68ee6da614efe244.1784322818.git.babu.moger@amd.com>
Hi Babu,
On 7/17/26 2:13 PM, Babu Moger wrote:
> The kernel currently enables the ABMC-based "mbm_event" mode by default on
> hardware that supports it. However, this can cause bandwidth monitoring
> failures with existing userspace tools such as pqos.
>
> The pqos tool mounts the resctrl filesystem and creates 16 or more resctrl
> groups by default. On systems with 32 or fewer ABMC counters, this default
> configuration can consume all available counters, since each group requires
> one counter for local MBM and another for total MBM. If additional
> monitoring groups are created, counter resources are exhausted and pqos
> tool reports memory bandwidth counters as zero for those groups.
It is not obvious to me that this is a problem. If I understand correctly
there are two scenarios possible with this pqos behavior:
- ABMC is not in use ("mbm_assign_mode" is set to "default")
- pqos can create 16 or more monitor groups
- hardware still supports a limited number of counters with consequence that
underlying counters reset at any time as the different monitoring groups
need to be tracked.
- pqos can read monitoring data of all 16 monitor groups, sometimes reading the
events would return "Unavailable", sometimes reading the events return data.
- *None* of the monitoring numbers returned are guaranteed to be accurate.
- ABMC is in use ("mbm_assign_mode" is set to "mbm_event"):
- pqos can create 16 or more monitor groups
- only a subset of monitoring groups have counters assigned and these counters
are guaranteed to only track the monitor groups/events they are assigned to
- pqos can read monitoring data of all 16 monitor groups with two possibilities:
- monitor group/event has counter assigned: monitoring numbers are guaranteed to be accurate
- monitor group/event does not have counter assigned: monitoring numbers return 0
If my understanding is correct then the preference is to rather have wrong data than
see 0? This does not sound right. What am I missing?
The changelog starts with "this can cause bandwidth monitoring failures with existing
userspace tools such as pqos". How could returning accurate memory bandwidth data be
considered a failure? How does this issue manifest itself?
>
> Avoid this compatibility issue by leaving mbm_assign_mode in the "default"
> mode during initialization. Users who want to use ABMC can continue to
> enable it explicitly:
>
> echo mbm_event > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode
>
> Update the resctrl documentation to reflect the new boot-time default and
> adjust the mbm_assign_mode examples accordingly.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> There are plans to enable "mbm_event" by default once additional counters
> are available. For now, keep the default mode to maintain compatibility
> with existing tools.
This is not ideal. resctrl should aim to provide a consistent user interface
across kernel versions.
Reinette
^ permalink raw reply
* Re: [PATCH v7 03/12] PCI: liveupdate: Track incoming preserved PCI devices
From: Alex Williamson @ 2026-07-17 22:38 UTC (permalink / raw)
To: David Matlack
Cc: kexec, linux-doc, linux-kernel, linux-mm, linux-pci,
Adithya Jayachandran, Alexander Graf, Bjorn Helgaas, Chris Li,
David Rientjes, Jacob Pan, Jason Gunthorpe, Jonathan Corbet,
Josh Hilke, Leon Romanovsky, Lukas Wunner, Mike Rapoport,
Parav Pandit, Pasha Tatashin, Pranjal Shrivastava, Pratyush Yadav,
Saeed Mahameed, Samiullah Khawaja, Shuah Khan, Vipin Sharma,
William Tu, Yi Liu, alex
In-Reply-To: <20260710212616.1351130-4-dmatlack@google.com>
On Fri, 10 Jul 2026 21:26:06 +0000
David Matlack <dmatlack@google.com> wrote:
> @@ -298,6 +377,87 @@ void pci_liveupdate_unpreserve(struct pci_dev *dev)
> }
> EXPORT_SYMBOL_GPL(pci_liveupdate_unpreserve);
>
> +static struct pci_flb_incoming *pci_liveupdate_flb_get_incoming(void)
> +{
> + struct pci_flb_incoming *incoming = NULL;
> + int ret;
> +
> + ret = liveupdate_flb_get_incoming(&pci_liveupdate_flb, (void **)&incoming);
> +
> + /* Live Update is not enabled. */
> + if (ret == -EOPNOTSUPP)
> + return NULL;
> +
> + /* Live Update is enabled, but there is no incoming FLB data. */
> + if (ret == -ENODATA)
> + return NULL;
> +
> + /*
> + * Live Update is enabled and there is incoming FLB data, but none of it
> + * matches pci_liveupdate_flb.compatible.
> + *
> + * This could mean that no PCI FLB data was passed by the previous
> + * kernel, but it could also mean the previous kernel used a different
> + * compatibility string (i.e. a different ABI).
> + */
> + if (ret == -ENOENT) {
> + pr_info_once("No incoming FLB matched %s\n", pci_liveupdate_flb.compatible);
> + return NULL;
> + }
> +
> + /*
> + * There is incoming FLB data that matches pci_liveupdate_flb.compatible
> + * but it cannot be retrieved.
> + */
> + if (ret)
> + panic("Failed to retrieve incoming FLB data (%d)\n", ret);
> +
> + return incoming;
> +}
I'm having trouble following the error escalation here. What's
fundamentally the difference between FLB data being provided and not
compatible (subtle log message) versus FLB data being provided and
compatible but we cannot access it (panic!)?
Don't both suggest devices are running but we can't get their FLB data
to continue letting them run?
The errno interpretation is also slightly different than the comment
above liveupdate_flb_get_incoming():
* Return: 0 on success, or a negative errno on failure. -ENODATA means no
* incoming FLB data, -ENOENT means specific flb not found in the incoming
* data, -ENODEV if the FLB's module is unloading, and -EOPNOTSUPP when
* live update is disabled or not configured.
Thanks,
Alex
^ permalink raw reply
* [PATCH v18 13/13] Documentation: cxl: Document CXL protocol error handling
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
Add Documentation/driver-api/cxl/linux/protocol-error-handling.rst
describing the end-to-end CXL protocol error path: AER ingress, the
AER-CXL kfifo handoff, the cxl_core consumer worker, RCD/RCH special
cases, severity policy, trace events, and a source code map.
This documents the architecture introduced by the preceding patches in
this series.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- Simplify document for readability (Jonathan)
- Drop historical context that goes stale (Jonathan)
- Shorten ASCII flow diagram (Jonathan)
- Drop manual backtick markup, use automarkup (Jonathan)
- Clarify USP/DSP as single switch component (Dave)
- Fix line wrapping to 80 chars (Jonathan)
---
Documentation/driver-api/cxl/index.rst | 1 +
.../cxl/linux/protocol-error-handling.rst | 222 ++++++++++++++++++
2 files changed, 223 insertions(+)
create mode 100644 Documentation/driver-api/cxl/linux/protocol-error-handling.rst
diff --git a/Documentation/driver-api/cxl/index.rst b/Documentation/driver-api/cxl/index.rst
index 3dfae1d310ca5..6861b2e5726a3 100644
--- a/Documentation/driver-api/cxl/index.rst
+++ b/Documentation/driver-api/cxl/index.rst
@@ -42,6 +42,7 @@ that have impacts on each other. The docs here break up configurations steps.
linux/dax-driver
linux/memory-hotplug
linux/access-coordinates
+ linux/protocol-error-handling
.. toctree::
:maxdepth: 2
diff --git a/Documentation/driver-api/cxl/linux/protocol-error-handling.rst b/Documentation/driver-api/cxl/linux/protocol-error-handling.rst
new file mode 100644
index 0000000000000..67f0492e56702
--- /dev/null
+++ b/Documentation/driver-api/cxl/linux/protocol-error-handling.rst
@@ -0,0 +1,222 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==============================
+CXL Protocol Error Handling
+==============================
+
+CXL devices report protocol-layer failures (CXL.cachemem RAS) as PCIe
+AER Internal Errors: PCI_ERR_COR_INTERNAL for correctable events and
+PCI_ERR_UNC_INTN for uncorrectable events. The actual fault
+information lives in CXL RAS capability registers, not in the PCIe AER
+status registers.
+
+The kernel routes every CXL Internal Error through a producer/consumer
+pipeline shared by all CXL device types: Root Ports, Upstream/Downstream
+Switch Ports, Endpoints, and Restricted CXL Devices (RCDs).
+
+
+Architecture
+============
+
+Two error planes run side by side:
+
+* The **PCIe AER plane** handles native PCIe errors (receiver
+ overflows, malformed TLPs, completion timeouts, etc.).
+* The **CXL protocol error plane** handles CXL Internal Errors.
+ The AER core forwards them to cxl_core via a dedicated kfifo;
+ cxl_core reads the CXL RAS registers, emits trace events, and
+ applies recovery/panic policy.
+
+The boundary between the two planes is enforced by is_cxl_error() in
+aer_cxl_vh.c. It checks info->is_cxl, the PCIe device type
+(Endpoint, Root Port, Upstream, or Downstream), and whether the AER
+status word indicates an internal error. RC_END devices are excluded
+from is_cxl_error() because they reach the kfifo via the separate
+cxl_rch_handle_error() path instead.
+
+The pipeline:
+
+1. **Producer** (aer_cxl_vh.c, aer_cxl_rch.c) - AER threaded
+ handler context. Classifies and enqueues a
+ struct cxl_proto_err_work_data into the kfifo.
+2. **Queue** - the AER-CXL kfifo plus a backing work_struct.
+3. **Consumer** (cxl_core/ras.c) - workqueue context. Resolves
+ the CXL port topology and dispatches to CE/UE handlers.
+
+
+Topologies
+==========
+
+Virtual Hierarchy (VH)
+----------------------
+
+Standard PCIe topology: Root Port, optional switch (Upstream Port with
+one or more Downstream Ports), and Endpoints. Each component raises
+Internal Errors directly via the Root Port's AER interrupt.
+
+Producer: cxl_forward_error() in aer_cxl_vh.c.
+
+Restricted CXL Host (RCH)
+--------------------------
+
+A Root Complex Event Collector (RCEC) aggregates errors from RCDs
+attached as Root Complex Integrated Endpoints. The AER driver
+iterates RCDs beneath the RCEC via pcie_walk_rcec() and forwards
+each qualifying device through cxl_forward_error() into the same
+kfifo.
+
+Producer: cxl_forward_error() in aer_cxl_vh.c, called from
+cxl_rch_handle_error_iter() via pcie_walk_rcec().
+
+
+Error flow
+==========
+
+.. code-block:: text
+
+ CXL device raises AER Internal Error
+ (PCI_ERR_COR_INTERNAL or PCI_ERR_UNC_INTN)
+ |
+ v
+ +--------------------------------------+
+ | AER core (aer.c) |
+ | aer_irq() -> aer_isr() |
+ | -> find_source_device() |
+ | -> handle_error_source(dev, info) |
+ +--------------------------------------+
+ |
+ v
+ +--------------------------------------+
+ | handle_error_source() dispatch |
+ | |
+ | 1. cxl_rch_handle_error() |
+ | [always; filters internally] |
+ | |
+ | 2. if is_cxl_error(): |
+ | cxl_forward_error() |
+ | [enqueue to kfifo] |
+ | |
+ | 3. if cxl_pending && non-CE: |
+ | cxl_proto_err_flush() |
+ | [sync drain before recovery] |
+ | |
+ | 4. pci_aer_handle_error() [always] |
+ +--------------------------------------+
+ |
+ (kfifo -> workqueue)
+ |
+ v
+ +--------------------------------------+
+ | __cxl_proto_err_work_fn() consumer |
+ | |
+ | if is_cxl_restricted(pdev): |
+ | cxl_handle_rdport_errors() |
+ | [RCH dport RAS first] |
+ | |
+ | port = find_cxl_port_by_dev( |
+ | &pdev->dev, NULL) |
+ | dport = cxl_find_dport_by_dev( |
+ | port, &pdev->dev) |
+ | [dport NULL for EP/USP; set RP/DSP] |
+ | |
+ | cxl_handle_proto_error() |
+ +--------------------------------------+
+ | |
+ v v
+ +-----------------+ +--------------------+
+ | CE | | UCE |
+ | cxl_handle_ | | cxl_do_recovery() |
+ | cor_ras() | | read RAS status |
+ | trace + clear | | trace + panic |
+ +-----------------+ +--------------------+
+
+cxl_do_recovery() reads the CXL RAS uncorrectable status register.
+If UE bits are set, it emits the trace event and panics. If no bits
+are set (e.g. RAS mapped but error already cleared), it logs a
+diagnostic and defers to AER recovery.
+
+
+Severity policy
+===============
+
+**CE** - cxl_handle_cor_ras() reads the CXL RAS correctable status
+register, clears set bits, and emits a cxl_aer_correctable_error
+trace event. No recovery action.
+
+**UCE (non-fatal, and fatal on Root Port/Downstream Port)** - cxl_do_recovery() reads the CXL RAS
+uncorrectable status register. If UE bits are set, the kernel panics.
+CXL.cachemem traffic cannot be safely recovered once an uncorrectable
+error is signaled; continuing risks silent data corruption across
+interleaved HDM regions. This panic policy applies to the native AER
+path. On firmware-first (CPER/GHES) platforms the CPER handler emits
+trace events only and does not call cxl_do_recovery().
+
+**Fatal UCE on EP/USP** - The AER core driver does not read AER status
+registers for Endpoint and Upstream Ports with fatal events because the
+link is down. Without AER status, is_cxl_error() cannot classify
+the event as a CXL protocol error and it falls through to standard
+AER recovery.
+
+RCH special case
+================
+
+When the consumer sees is_cxl_restricted(pdev), it calls
+cxl_handle_rdport_errors() first to process the RCH Downstream
+Port's RAS registers (accessed via RCRB, not standard config space).
+It then continues to process the RCD Endpoint's own RAS registers
+via the common path. Both register blocks are checked because
+errors can appear in either independently.
+
+cxl_handle_rdport_errors() acquires the port lock internally.
+Callers must not hold it.
+
+
+Trace events
+============
+
+Two trace events cover all device types and both the native AER and
+CPER/GHES firmware-first paths:
+
+* cxl_aer_correctable_error
+* cxl_aer_uncorrectable_error
+
+Fields:
+
+* ``memdev`` - memdev name for Endpoints; empty for non-Endpoints.
+* ``port`` - CXL port device name.
+* ``dport`` - Downstream Port device name; empty when not applicable.
+* ``host`` - parent host bridge or uport device name.
+* ``serial`` - PCI Device Serial Number from pdev->dsn (cached at
+ enumeration; no config-space read in the error path).
+
+
+Interrupt masking
+=================
+
+CXL Internal Error bits (PCI_ERR_UNC_INTN and PCI_ERR_COR_INTERNAL)
+are unmasked in the AER capability only after the CXL RAS register
+block is successfully mapped. A devm teardown action restores the
+mask when the port or dport is removed, ensuring clean state after
+driver removal.
+
+
+Source files
+============
+
+.. list-table::
+ :header-rows: 1
+
+ * - File
+ - Role
+ * - drivers/pci/pcie/aer.c
+ - AER core; IRQ, dispatch
+ * - drivers/pci/pcie/aer_cxl_vh.c
+ - VH producer; kfifo
+ * - drivers/pci/pcie/aer_cxl_rch.c
+ - RCH dispatch; RCEC walk
+ * - drivers/cxl/core/ras.c
+ - Consumer; CE/UE handlers; CPER
+ * - drivers/cxl/core/ras_rch.c
+ - RCH dport RAS handling
+ * - drivers/acpi/apei/ghes.c
+ - CPER/GHES kfifo producer
--
2.34.1
^ permalink raw reply related
* [PATCH v18 12/13] PCI/CXL: Mask/Unmask CXL protocol errors
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
CXL protocol errors are not enabled for all CXL devices after boot.
They must be enabled in order to process CXL protocol errors. Provide
matching teardown helpers so the masks are restored when a CXL Port
or dport goes away.
Add pci_aer_mask_internal_errors() as the symmetric counterpart to
pci_aer_unmask_internal_errors() and export both for the cxl_core
module.
Introduce cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts()
in cxl_core to wrap the PCI helpers with the dev_is_pci() and
pcie_aer_is_native() gating CXL needs. Both helpers tolerate a NULL
or non-PCI @dev so callers do not have to special-case it.
Wire cxl_unmask_proto_interrupts() into the success path of
cxl_dport_map_ras() and devm_cxl_port_ras_setup() so the unmask
only runs when the RAS register block was actually mapped. Pair each
unmask with a devm_add_action_or_reset() registration of
cxl_mask_proto_irqs() scoped to the host device so the mask is
restored when devres is released. This applies to dports, Endpoints,
Upstream Switch Ports, Downstream Switch Ports, and Root Ports.
Remove the dev_is_pci(dport->dport_dev) guard in
devm_cxl_dport_rch_ras_setup(). On RCH systems dport->dport_dev is the
pci_host_bridge device, which is not on pci_bus_type, so this guard
caused the function to return early on real hardware without mapping
dport RAS or AER registers. The caller already gates on dport->rch,
which is sufficient to exclude cxl_test mock devices.
Co-developed-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- Make cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts() static
- Remove dev_is_pci() guard from devm_cxl_dport_rch_ras_setup(); the guard
blocked real RCH hardware because pci_host_bridge is not on pci_bus_type
Changes in v16->v17:
- Drop redundant cxl_mask_proto_interrupts() calls from unregister_port()
and cxl_dport_remove(); the devres action registered alongside the unmask
is the sole mask path.
- Update title
- Remove unnecessary check for aer_capabilities
- Gate cxl_unmask_proto_interrupts() on pcie_aer_is_native()
- Add pci_aer_mask_internal_errors() and cxl_mask_proto_interrupts()
- Only unmask on successful cxl_map_component_regs()
- NULL-check @dev in cxl_{un,}mask_proto_interrupts()
- Drop static and declare in core/core.h
Change in v15 -> v16:
- None
Change in v14 -> v15:
- None
Changes in v13->v14:
- Update commit title's prefix (Bjorn)
Changes in v12->v13:
- Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Terry)
- Add Dave Jiang's and Ben's review-by
Changes in v11->v12:
- None
---
drivers/cxl/core/ras.c | 73 +++++++++++++++++++++++++++++++----
drivers/pci/pcie/aer.c | 28 ++++++++++++--
include/linux/aer.h | 2 +
tools/testing/cxl/Kbuild | 1 +
tools/testing/cxl/test/mock.c | 12 ++++++
5 files changed, 105 insertions(+), 11 deletions(-)
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 69b320c74469c..d77208af41e03 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -117,16 +117,64 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)
}
static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
+static void cxl_unmask_proto_interrupts(struct device *dev)
+{
+ struct pci_dev *pdev;
+
+ if (!dev || !dev_is_pci(dev))
+ return;
+
+ pdev = to_pci_dev(dev);
+ if (!pcie_aer_is_native(pdev))
+ return;
+
+ pci_aer_unmask_internal_errors(pdev);
+}
+
+static void cxl_mask_proto_interrupts(struct device *dev)
+{
+ struct pci_dev *pdev;
+
+ if (!dev || !dev_is_pci(dev))
+ return;
+
+ pdev = to_pci_dev(dev);
+ if (!pcie_aer_is_native(pdev))
+ return;
+
+ pci_aer_mask_internal_errors(pdev);
+}
+
+static void cxl_mask_proto_irqs(void *dev)
+{
+ cxl_mask_proto_interrupts(dev);
+}
+
static void cxl_dport_map_ras(struct cxl_dport *dport)
{
struct cxl_register_map *map = &dport->reg_map;
struct device *dev = dport->dport_dev;
- if (!map->component_map.ras.valid)
+ if (!map->component_map.ras.valid) {
dev_dbg(dev, "RAS registers not found\n");
- else if (cxl_map_component_regs(map, &dport->regs.component,
- BIT(CXL_CM_CAP_CAP_ID_RAS)))
+ return;
+ }
+
+ if (cxl_map_component_regs(map, &dport->regs.component,
+ BIT(CXL_CM_CAP_CAP_ID_RAS))) {
dev_dbg(dev, "Failed to map RAS capability.\n");
+ return;
+ }
+
+ if (!dev_is_pci(dev))
+ return;
+
+ cxl_unmask_proto_interrupts(dev);
+ if (devm_add_action_or_reset(dport_to_host(dport),
+ cxl_mask_proto_irqs, dev)) {
+ dev_warn(dev, "failed to defer CXL proto-irq mask; CXL protocol error reporting disabled\n");
+ dport->regs.component.ras = NULL;
+ }
}
/**
@@ -143,9 +191,6 @@ void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
{
struct pci_host_bridge *host_bridge;
- if (!dev_is_pci(dport->dport_dev))
- return;
-
devm_cxl_dport_ras_setup(dport);
host_bridge = to_pci_host_bridge(dport->dport_dev);
@@ -160,6 +205,7 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_rch_ras_setup, "CXL");
void devm_cxl_port_ras_setup(struct cxl_port *port)
{
struct cxl_register_map *map = &port->reg_map;
+ struct device *dev;
if (!map->component_map.ras.valid) {
dev_dbg(&port->dev, "RAS registers not found\n");
@@ -168,8 +214,21 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)
map->host = &port->dev;
if (cxl_map_component_regs(map, &port->regs,
- BIT(CXL_CM_CAP_CAP_ID_RAS)))
+ BIT(CXL_CM_CAP_CAP_ID_RAS))) {
dev_dbg(&port->dev, "Failed to map RAS capability\n");
+ return;
+ }
+
+ dev = is_cxl_endpoint(port) ? port->uport_dev->parent : port->uport_dev;
+ if (!dev_is_pci(dev))
+ return;
+
+ cxl_unmask_proto_interrupts(dev);
+ if (devm_add_action_or_reset(&port->dev, cxl_mask_proto_irqs, dev)) {
+ dev_warn(&port->dev,
+ "failed to defer CXL proto-irq mask; CXL protocol error reporting disabled\n");
+ port->regs.ras = NULL;
+ }
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL");
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 0bd23a65e7ebc..be6dc2cbd4491 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1143,12 +1143,32 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
mask &= ~PCI_ERR_COR_INTERNAL;
pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
}
+EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core");
-/*
- * Internal errors are too device-specific to enable generally, however for CXL
- * their behavior is standardized for conveying CXL protocol errors.
+/**
+ * pci_aer_mask_internal_errors - mask internal errors
+ * @dev: pointer to the pci_dev data structure
+ *
+ * Mask internal errors in the Uncorrectable and Correctable Error
+ * Mask registers.
+ *
+ * Note: AER must be enabled and supported by the device which must be
+ * checked in advance, e.g. with pcie_aer_is_native().
*/
-EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core");
+void pci_aer_mask_internal_errors(struct pci_dev *dev)
+{
+ int aer = dev->aer_cap;
+ u32 mask;
+
+ pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
+ mask |= PCI_ERR_UNC_INTN;
+ pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
+
+ pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
+ mask |= PCI_ERR_COR_INTERNAL;
+ pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
+}
+EXPORT_SYMBOL_FOR_MODULES(pci_aer_mask_internal_errors, "cxl_core");
/**
* pci_aer_handle_error - handle logging error into an event log
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 8eba3192e2d15..b3657b80564b9 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -58,6 +58,7 @@ struct aer_capability_regs {
int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
int pcie_aer_is_native(struct pci_dev *dev);
void pci_aer_unmask_internal_errors(struct pci_dev *dev);
+void pci_aer_mask_internal_errors(struct pci_dev *dev);
#else
static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
{
@@ -65,6 +66,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
}
static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }
+static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { }
#endif
#ifdef CONFIG_CXL_RAS
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
index 2be1df80fcc93..957945201f04d 100644
--- a/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@ -6,6 +6,7 @@ ldflags-y += --wrap=acpi_pci_find_root
ldflags-y += --wrap=nvdimm_bus_register
ldflags-y += --wrap=cxl_await_media_ready
ldflags-y += --wrap=devm_cxl_add_rch_dport
+ldflags-y += --wrap=devm_cxl_dport_rch_ras_setup
ldflags-y += --wrap=cxl_endpoint_parse_cdat
ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
ldflags-y += --wrap=hmat_get_extended_linear_cache_size
diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
index 6454b868b122c..5ad3243da8d29 100644
--- a/tools/testing/cxl/test/mock.c
+++ b/tools/testing/cxl/test/mock.c
@@ -220,6 +220,18 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port,
}
EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL");
+void __wrap_devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
+{
+ int index;
+ struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
+
+ if (!ops || !ops->is_mock_port(dport->dport_dev))
+ devm_cxl_dport_rch_ras_setup(dport);
+
+ put_cxl_mock_ops(index);
+}
+EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_dport_rch_ras_setup, "CXL");
+
void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port)
{
int index;
--
2.34.1
^ permalink raw reply related
* [PATCH v18 11/13] PCI: Cache PCI DSN into pci_dev->dsn during probe
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
Subsequent CXL error-reporting code paths need to log the PCI Device
Serial Number (DSN) as part of trace events emitted from interrupt or
panic context. Computing the DSN there via pci_get_dsn() requires PCI
configuration space reads, which are slow, can fail when the link is
down or frozen, and may not be safe in some contexts.
Add a u64 dsn field to struct pci_dev and populate it from pci_get_dsn()
during pci_init_capabilities() at probe time via pci_dsn_init(). Only
write dev->dsn when the read succeeds. The zero initial value from
pci_dev allocation already represents 'no DSN available.'
pci_get_dsn() is not modified because it remains a pure config-space read
with no side effects on pci_dev. The cache is written exclusively by
pci_dsn_init() at probe time.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- New commit.
---
drivers/cxl/core/ras.c | 11 ++++++-----
drivers/cxl/core/ras_rch.c | 4 ++--
drivers/cxl/pci.c | 2 +-
drivers/pci/probe.c | 14 ++++++++++++++
include/linux/pci.h | 1 +
5 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index acf40b2396c3b..69b320c74469c 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -100,10 +100,10 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
dport = cxl_find_dport_by_dev(port, &pdev->dev);
if (data->severity == AER_CORRECTABLE)
- cxl_cper_trace_corr_prot_err(port, dport, pci_get_dsn(pdev),
+ cxl_cper_trace_corr_prot_err(port, dport, pdev->dsn,
&data->ras_cap);
else
- cxl_cper_trace_uncorr_prot_err(port, dport, pci_get_dsn(pdev),
+ cxl_cper_trace_uncorr_prot_err(port, dport, pdev->dsn,
&data->ras_cap);
}
EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);
@@ -195,7 +195,7 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dpo
return;
}
- if (cxl_handle_ras(port, dport, ras_base, pci_get_dsn(pdev)))
+ if (cxl_handle_ras(port, dport, ras_base, pdev->dsn))
panic("CXL cachemem error");
dev_dbg(&pdev->dev,
@@ -307,7 +307,7 @@ pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
* CXL.mem traffic.
*/
ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL),
- pci_get_dsn(pdev));
+ pdev->dsn);
}
/*
@@ -339,7 +339,8 @@ static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport, int severity)
{
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), pci_get_dsn(pdev));
+ cxl_handle_cor_ras(port, dport, to_ras_base(port, dport),
+ pdev->dsn);
else
cxl_do_recovery(pdev, port, dport);
}
diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
index 0385d2f4a2f66..14bb3bdb2d092 100644
--- a/drivers/cxl/core/ras_rch.c
+++ b/drivers/cxl/core/ras_rch.c
@@ -118,8 +118,8 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev)
pci_print_aer(pdev, severity, &aer_regs);
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport),
- pci_get_dsn(pdev));
+ cxl_handle_cor_ras(dport->port, dport,
+ to_ras_base(port, dport), pdev->dsn);
else
cxl_do_recovery(pdev, dport->port, dport);
}
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 6cf1db7b85020..45a994cc782a9 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -807,7 +807,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (!dvsec)
pci_warn(pdev, "Device DVSEC not present, skip CXL.mem init\n");
- mds = cxl_memdev_state_create(&pdev->dev, pci_get_dsn(pdev), dvsec);
+ mds = cxl_memdev_state_create(&pdev->dev, pdev->dsn, dvsec);
if (IS_ERR(mds))
return PTR_ERR(mds);
cxlds = &mds->cxlds;
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index dd0abbc63e18d..92ece5ec211f8 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2638,6 +2638,19 @@ void pcie_report_downtraining(struct pci_dev *dev)
__pcie_print_link_status(dev, false);
}
+/*
+ * Cache the Device Serial Number for use in contexts where config-space
+ * reads are unsafe (interrupt, panic). Process-context callers that
+ * need a fresh value (e.g. hotplug device replacement) use pci_get_dsn().
+ */
+static void pci_dsn_init(struct pci_dev *dev)
+{
+ u64 dsn = pci_get_dsn(dev);
+
+ if (dsn)
+ dev->dsn = dsn;
+}
+
static void pci_imm_ready_init(struct pci_dev *dev)
{
u16 status;
@@ -2674,6 +2687,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
pci_rebar_init(dev); /* Resizable BAR */
pci_dev3_init(dev); /* Device 3 capabilities */
pci_ide_init(dev); /* Link Integrity and Data Encryption */
+ pci_dsn_init(dev); /* Serial number */
pcie_report_downtraining(dev);
pci_init_reset_methods(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 64b308b6e61c1..48a1622639190 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -386,6 +386,7 @@ struct pci_dev {
unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
struct pci_driver *driver; /* Driver bound to this device */
+ u64 dsn; /* PCI Device Serial Number */
u64 dma_mask; /* Mask of the bits of bus address this
device implements. Normally this is
0xffffffff. You only need to change
--
2.34.1
^ permalink raw reply related
* [PATCH v18 10/13] cxl: Add port and dport identifiers to CXL AER trace events
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
From: Dan Williams <djbw@kernel.org>
Pass struct cxl_port * and struct cxl_dport * to the cxl_aer_*
trace events instead of a plain struct device * derived at the
caller. The trace event helpers then derive the right strings for
endpoints, switch ports, root ports, and RCH downstream ports
consistently across the CPER and native AER paths.
The unified cxl_aer_* events keep "memdev" as the legacy field
(endpoint events populate it with the memdev name; non-endpoint
events emit memdev="") and add new "port" and "dport" string fields
populated for all CXL device classes. Updated userspace can key
off "port" and "dport" without a parallel set of events.
Remove the separate cxl_port_aer_uncorrectable_error and
cxl_port_aer_correctable_error trace events. All CXL AER events now
use the unified cxl_aer_* events with port and dport fields.
Rework cxl_cper_handle_prot_err() to use find_cxl_port_by_dev() and
the unified trace helpers, replacing the per-port-type branching and
bus_find_device() memdev lookup.
The TP_printk format string places "port=%s dport=%s" between
"memdev=%s" and "host=%s", changing the text-mode field order from
the pre-patch output. This does not affect consumers such as
rasdaemon that use libtraceevent to parse fields by name rather than
by fixed text position.
For non-endpoint events (switch port, root port, RCH dport),
"memdev" is empty and "port"/"dport" carry the topology information.
The serial number is retrieved via pci_get_dsn() which performs live
PCI configuration space reads. A following patch ("PCI: Cache PCI
DSN into pci_dev->dsn during probe") replaces these with a cached
serial number to avoid config space access in error handlers and panic
paths.
Below are examples of the different CXL devices' error trace logs
after this patch:
---------------------
| CXL RP - 0C:00.0 |
---------------------
|
---------------------
| CXL USP - 0D:00.0 |
---------------------
|
--------------------
| CXL DSP - 0E:00.0 |
--------------------
|
---------------------
| CXL EP - 0F:00.0 |
---------------------
Root Port:
cxl_aer_correctable_error: memdev= port=port1 dport=0000:0c:00.0 \
host=pci0000:0c serial=0: status: 'Memory Data ECC Error'
cxl_aer_uncorrectable_error: memdev= port=port1 dport=0000:0c:00.0 \
host=pci0000:0c serial=0: status: 'Cache Address Parity Error' \
first_error: 'Cache Address Parity Error'
Upstream Switch Port:
cxl_aer_correctable_error: memdev= port=port2 dport= host=0000:0d:00.0 \
serial=0: status: 'Memory Data ECC Error'
UCE NA - Upstream Switch Port UCE's are handled in the portdrv driver's
PCI AER callbacks that are not CXL aware.
Downstream Switch Port:
cxl_aer_correctable_error: memdev= port=port2 dport=0000:0e:00.0 \
host=0000:0d:00.0 serial=0: status: 'Memory Data ECC Error'
cxl_aer_uncorrectable_error: memdev= port=port2 dport=0000:0e:00.0 \
host=0000:0d:00.0 serial=0: status: 'Cache Address Parity Error' \
first_error: 'Cache Address Parity Error'
Endpoint:
cxl_aer_uncorrectable_error: memdev=mem1 port=endpoint4 dport= \
host=0000:0f:00.0 serial=0: status: 'Cache Address Parity Error' \
first_error: 'Cache Address Parity Error'
cxl_aer_correctable_error: memdev=mem1 port=endpoint4 dport= host=0000:0f:00.0 \
serial=0: status: 'Memory Data ECC Error'
Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Dan Williams <djbw@kernel.org>
---
Changes in v17->v18:
- Consolidate double find_cxl_port_by_dev() in cxl_cper_handle_prot_err()
- Add comment noting dport is NULL for Endpoint and Upstream Port devices
- Add cxl_trace_* helpers
- Add CPER refactor
Changes in v16->v17:
- Replace cxlds->serial with pci_get_dsn()
- Change 'memdev' to 'device' (Dan)
- Updated Commit message
Changes in v15->v16:
- Add Dan's review-by
- Incorporate Dan's comment into commit message:
"Add the serial number at the end to preserve compatibility with
libtraceevent parsing of the parameters."
Changes in v14->v15:
- Update commit message.
- Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry)
Changes in v13->v14:
- Update commit headline (Bjorn)
Changes in v12->v13:
- Added Dave Jiang's review-by
Changes in v11 -> v12:
- Correct parameters to call trace_cxl_aer_correctable_error()
- Add reviewed-by for Jonathan and Shiju
Changes in v10->v11:
- Updated CE and UCE trace routines to maintain consistent TP_Struct ABI
and unchanged TP_printk() logging.
---
drivers/cxl/core/core.h | 8 +--
drivers/cxl/core/ras.c | 131 +++++++++++--------------------------
drivers/cxl/core/ras_rch.c | 3 +-
drivers/cxl/core/trace.c | 35 ++++++++++
drivers/cxl/core/trace.h | 91 ++++++++------------------
drivers/cxl/cxlmem.h | 7 ++
6 files changed, 113 insertions(+), 162 deletions(-)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 5ca1275fd8f35..a55a4e409feda 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -186,11 +186,11 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)
void cxl_ras_init(void);
void cxl_ras_exit(void);
bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport,
- void __iomem *ras_base);
+ void __iomem *ras_base, u64 serial);
void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport);
void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport,
- void __iomem *ras_base);
+ void __iomem *ras_base, u64 serial);
void cxl_dport_map_rch_aer(struct cxl_dport *dport);
void cxl_disable_rch_root_ints(struct cxl_dport *dport);
void cxl_handle_rdport_errors(struct pci_dev *pdev);
@@ -200,14 +200,14 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
static inline void cxl_ras_init(void) { }
static inline void cxl_ras_exit(void) { }
static inline bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport,
- void __iomem *ras_base)
+ void __iomem *ras_base, u64 serial)
{
return false;
}
static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport) { }
static inline void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport,
- void __iomem *ras_base) { }
+ void __iomem *ras_base, u64 serial) { }
static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }
static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }
static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { }
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index d5dc2c22565da..acf40b2396c3b 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -12,69 +12,37 @@
static_assert(CXL_HEADERLOG_TRACE_SIZE_U32 == 128,
"rasdaemon ABI requires exactly 128 u32s");
-static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,
- struct cxl_ras_capability_regs ras_cap)
-{
- u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;
-
- trace_cxl_port_aer_correctable_error(&pdev->dev, status);
-}
-
-static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,
- struct cxl_ras_capability_regs ras_cap)
+static void cxl_cper_trace_uncorr_prot_err(struct cxl_port *port, struct cxl_dport *dport,
+ u64 serial, struct cxl_ras_capability_regs *ras_cap)
{
u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] = {};
- u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;
+ u32 status = ras_cap->uncor_status & ~ras_cap->uncor_mask;
u32 fe;
if (hweight32(status) > 1)
fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
- ras_cap.cap_control));
- else
- fe = status;
-
- memcpy(hl, ras_cap.header_log, CXL_HEADERLOG_SIZE);
- trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, hl);
-}
-
-static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd,
- struct cxl_ras_capability_regs ras_cap)
-{
- u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;
-
- trace_cxl_aer_correctable_error(cxlmd, status);
-}
-
-static void
-cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,
- struct cxl_ras_capability_regs ras_cap)
-{
- u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] = {};
- u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;
- u32 fe;
-
- if (hweight32(status) > 1)
- fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
- ras_cap.cap_control));
+ ras_cap->cap_control));
else
fe = status;
/*
- * ras_cap.header_log[] holds CXL_HEADERLOG_SIZE_U32 (16) hardware
+ * ras_cap->header_log[] holds CXL_HEADERLOG_SIZE_U32 (16) hardware
* dwords. Copy them into the front of a zero-filled
* CXL_HEADERLOG_TRACE_SIZE_U32 (128) u32 staging buffer so the trace
* event memcpy sees a full 512-byte source and the userspace ABI
* (rasdaemon) is preserved.
*/
- memcpy(hl, ras_cap.header_log, CXL_HEADERLOG_SIZE);
- trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, hl);
+ memcpy(hl, ras_cap->header_log, CXL_HEADERLOG_SIZE);
+ trace_cxl_aer_uncorrectable_error(port, dport, status, fe,
+ hl, serial);
}
-static int match_memdev_by_parent(struct device *dev, const void *uport)
+static void cxl_cper_trace_corr_prot_err(struct cxl_port *port, struct cxl_dport *dport,
+ u64 serial, struct cxl_ras_capability_regs *ras_cap)
{
- if (is_cxl_memdev(dev) && dev->parent == uport)
- return 1;
- return 0;
+ u32 status = ras_cap->cor_status & ~ras_cap->cor_mask;
+
+ trace_cxl_aer_correctable_error(port, dport, status, serial);
}
@@ -109,47 +77,34 @@ static struct cxl_port *find_cxl_port_by_dev(struct device *dev, struct cxl_dpor
void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
{
+ struct cxl_dport *dport;
unsigned int devfn = PCI_DEVFN(data->prot_err.agent_addr.device,
data->prot_err.agent_addr.function);
- struct pci_dev *pdev __free(pci_dev_put) =
- pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,
- data->prot_err.agent_addr.bus,
- devfn);
- struct cxl_memdev *cxlmd;
- int port_type;
-
- if (!pdev)
- return;
-
- port_type = pci_pcie_type(pdev);
- if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
- port_type == PCI_EXP_TYPE_DOWNSTREAM ||
- port_type == PCI_EXP_TYPE_UPSTREAM) {
- if (data->severity == AER_CORRECTABLE)
- cxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);
- else
- cxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);
-
+ struct pci_dev *pdev __free(pci_dev_put) = pci_get_domain_bus_and_slot(
+ data->prot_err.agent_addr.segment, data->prot_err.agent_addr.bus, devfn);
+ if (!pdev) {
+ pr_err_ratelimited("Failed to find CPER device in CXL topology\n");
return;
}
- guard(device)(&pdev->dev);
- if (!pdev->dev.driver) {
- dev_warn_ratelimited(&pdev->dev,
- "Device is unbound, abort CPER error handling\n");
+ struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_dev(&pdev->dev, NULL);
+ if (!port) {
+ dev_err_ratelimited(&pdev->dev,
+ "Failed to find parent port device in CXL topology\n");
return;
}
- struct device *mem_dev __free(put_device) = bus_find_device(
- &cxl_bus_type, NULL, pdev, match_memdev_by_parent);
- if (!mem_dev)
- return;
+ guard(device)(&port->dev);
+
+ /* dport is NULL for Endpoint and Upstream Port devices */
+ dport = cxl_find_dport_by_dev(port, &pdev->dev);
- cxlmd = to_cxl_memdev(mem_dev);
if (data->severity == AER_CORRECTABLE)
- cxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap);
+ cxl_cper_trace_corr_prot_err(port, dport, pci_get_dsn(pdev),
+ &data->ras_cap);
else
- cxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap);
+ cxl_cper_trace_uncorr_prot_err(port, dport, pci_get_dsn(pdev),
+ &data->ras_cap);
}
EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);
@@ -240,14 +195,14 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dpo
return;
}
- if (cxl_handle_ras(port, dport, ras_base))
+ if (cxl_handle_ras(port, dport, ras_base, pci_get_dsn(pdev)))
panic("CXL cachemem error");
dev_dbg(&pdev->dev,
"CXL UCE signaled but no CXL RAS status bits set\n");
}
-void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base)
+void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base, u64 serial)
{
u32 status;
void __iomem *addr;
@@ -259,12 +214,7 @@ void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, void __i
status = readl(addr);
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
- if (is_cxl_endpoint(port))
- trace_cxl_aer_correctable_error(to_cxl_memdev(port->uport_dev), status);
- else if (dport)
- trace_cxl_port_aer_correctable_error(dport->dport_dev, status);
- else
- trace_cxl_port_aer_correctable_error(port->uport_dev, status);
+ trace_cxl_aer_correctable_error(port, dport, status, serial);
}
}
@@ -289,7 +239,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)
* Log the state of the RAS status registers and prepare them to log the
* next error status. Return 1 if reset needed.
*/
-bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base)
+bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport,
+ void __iomem *ras_base, u64 serial)
{
u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] = {};
void __iomem *addr;
@@ -316,12 +267,7 @@ bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem
}
header_log_copy(ras_base, hl);
- if (is_cxl_endpoint(port))
- trace_cxl_aer_uncorrectable_error(to_cxl_memdev(port->uport_dev), status, fe, hl);
- else if (dport)
- trace_cxl_port_aer_uncorrectable_error(dport->dport_dev, status, fe, hl);
- else
- trace_cxl_port_aer_uncorrectable_error(port->uport_dev, status, fe, hl);
+ trace_cxl_aer_uncorrectable_error(port, dport, status, fe, hl, serial);
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
@@ -360,7 +306,8 @@ pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
* cases below handle AER recovery for devices without active
* CXL.mem traffic.
*/
- ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL));
+ ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL),
+ pci_get_dsn(pdev));
}
/*
@@ -392,7 +339,7 @@ static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport, int severity)
{
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(port, dport, to_ras_base(port, dport));
+ cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), pci_get_dsn(pdev));
else
cxl_do_recovery(pdev, port, dport);
}
diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
index f4b98f2c11a1c..0385d2f4a2f66 100644
--- a/drivers/cxl/core/ras_rch.c
+++ b/drivers/cxl/core/ras_rch.c
@@ -118,7 +118,8 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev)
pci_print_aer(pdev, severity, &aer_regs);
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport));
+ cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport),
+ pci_get_dsn(pdev));
else
cxl_do_recovery(pdev, dport->port, dport);
}
diff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c
index 7f2a9dd0d0e3f..df42d119c53dd 100644
--- a/drivers/cxl/core/trace.c
+++ b/drivers/cxl/core/trace.c
@@ -2,7 +2,42 @@
/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
#include <cxl.h>
+#include <cxlmem.h>
#include "core.h"
+const char *cxl_trace_memdev_name(struct cxl_port *port)
+{
+ if (is_cxl_endpoint(port)) {
+ struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
+
+ return dev_name(&cxlmd->dev);
+ }
+
+ return "";
+}
+
+const char *cxl_trace_host_name(struct cxl_port *port)
+{
+ if (is_cxl_endpoint(port)) {
+ struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
+
+ return dev_name(cxlmd->dev.parent);
+ }
+
+ return dev_name(port->uport_dev);
+}
+
+const char *cxl_trace_port_name(struct cxl_port *port)
+{
+ return dev_name(&port->dev);
+}
+
+const char *cxl_trace_dport_name(struct cxl_dport *dport)
+{
+ if (dport)
+ return dev_name(dport->dport_dev);
+ return "";
+}
+
#define CREATE_TRACE_POINTS
#include "trace.h"
diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
index d37876096dd7c..910aceb2ca3ab 100644
--- a/drivers/cxl/core/trace.h
+++ b/drivers/cxl/core/trace.h
@@ -48,44 +48,15 @@
{ CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
)
-TRACE_EVENT(cxl_port_aer_uncorrectable_error,
- TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
- TP_ARGS(dev, status, fe, hl),
- TP_STRUCT__entry(
- __string(device, dev_name(dev))
- __string(host, dev_name(dev->parent))
- __field(u32, status)
- __field(u32, first_error)
- __array(u32, header_log, CXL_HEADERLOG_TRACE_SIZE_U32)
- ),
- TP_fast_assign(
- __assign_str(device);
- __assign_str(host);
- __entry->status = status;
- __entry->first_error = fe;
- /*
- * Embed headerlog data for user app retrieval and parsing,
- * but no need to print in the trace buffer. Only
- * CXL_HEADERLOG_SIZE_U32 (16) dwords are hardware data;
- * the remaining entries preserve the 512-byte ABI layout
- * rasdaemon depends on and are zero-filled by the caller.
- */
- memcpy(__entry->header_log, hl,
- CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32));
- ),
- TP_printk("device=%s host=%s status: '%s' first_error: '%s'",
- __get_str(device), __get_str(host),
- show_uc_errs(__entry->status),
- show_uc_errs(__entry->first_error)
- )
-);
-
TRACE_EVENT(cxl_aer_uncorrectable_error,
- TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),
- TP_ARGS(cxlmd, status, fe, hl),
+ TP_PROTO(struct cxl_port *port, struct cxl_dport *dport,
+ u32 status, u32 fe, u32 *hl, u64 serial),
+ TP_ARGS(port, dport, status, fe, hl, serial),
TP_STRUCT__entry(
- __string(memdev, dev_name(&cxlmd->dev))
- __string(host, dev_name(cxlmd->dev.parent))
+ __string(memdev, cxl_trace_memdev_name(port))
+ __string(port, cxl_trace_port_name(port))
+ __string(dport, cxl_trace_dport_name(dport))
+ __string(host, cxl_trace_host_name(port))
__field(u64, serial)
__field(u32, status)
__field(u32, first_error)
@@ -93,8 +64,10 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
),
TP_fast_assign(
__assign_str(memdev);
+ __assign_str(port);
+ __assign_str(dport);
__assign_str(host);
- __entry->serial = cxlmd->cxlds->serial;
+ __entry->serial = serial;
__entry->status = status;
__entry->first_error = fe;
/*
@@ -107,8 +80,9 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
memcpy(__entry->header_log, hl,
CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32));
),
- TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'",
- __get_str(memdev), __get_str(host), __entry->serial,
+ TP_printk("memdev=%s port=%s dport=%s host=%s serial=%lld: status: '%s' first_error: '%s'",
+ __get_str(memdev), __get_str(port), __get_str(dport),
+ __get_str(host), __entry->serial,
show_uc_errs(__entry->status),
show_uc_errs(__entry->first_error)
)
@@ -132,42 +106,29 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
{ CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \
)
-TRACE_EVENT(cxl_port_aer_correctable_error,
- TP_PROTO(struct device *dev, u32 status),
- TP_ARGS(dev, status),
- TP_STRUCT__entry(
- __string(device, dev_name(dev))
- __string(host, dev_name(dev->parent))
- __field(u32, status)
- ),
- TP_fast_assign(
- __assign_str(device);
- __assign_str(host);
- __entry->status = status;
- ),
- TP_printk("device=%s host=%s status='%s'",
- __get_str(device), __get_str(host),
- show_ce_errs(__entry->status)
- )
-);
-
TRACE_EVENT(cxl_aer_correctable_error,
- TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),
- TP_ARGS(cxlmd, status),
+ TP_PROTO(struct cxl_port *port, struct cxl_dport *dport,
+ u32 status, u64 serial),
+ TP_ARGS(port, dport, status, serial),
TP_STRUCT__entry(
- __string(memdev, dev_name(&cxlmd->dev))
- __string(host, dev_name(cxlmd->dev.parent))
+ __string(memdev, cxl_trace_memdev_name(port))
+ __string(port, cxl_trace_port_name(port))
+ __string(dport, cxl_trace_dport_name(dport))
+ __string(host, cxl_trace_host_name(port))
__field(u64, serial)
__field(u32, status)
),
TP_fast_assign(
__assign_str(memdev);
+ __assign_str(port);
+ __assign_str(dport);
__assign_str(host);
- __entry->serial = cxlmd->cxlds->serial;
+ __entry->serial = serial;
__entry->status = status;
),
- TP_printk("memdev=%s host=%s serial=%lld: status: '%s'",
- __get_str(memdev), __get_str(host), __entry->serial,
+ TP_printk("memdev=%s port=%s dport=%s host=%s serial=%lld: status: '%s'",
+ __get_str(memdev), __get_str(port), __get_str(dport),
+ __get_str(host), __entry->serial,
show_ce_errs(__entry->status)
)
);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index ed419d0c59f2f..f1ef8b78db18a 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -125,6 +125,13 @@ static inline int cxl_memdev_attach_region(struct cxl_memdev *cxlmd)
#endif
struct cxl_memdev *devm_cxl_add_classdev(struct cxl_dev_state *cxlds);
+
+/* trace-event helpers */
+const char *cxl_trace_memdev_name(struct cxl_port *port);
+const char *cxl_trace_host_name(struct cxl_port *port);
+const char *cxl_trace_port_name(struct cxl_port *port);
+const char *cxl_trace_dport_name(struct cxl_dport *dport);
+
struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds,
const struct cxl_memdev_attach *attach);
int devm_cxl_sanitize_setup_notifier(struct device *host,
--
2.34.1
^ permalink raw reply related
* [PATCH v18 09/13] cxl: Update CXL Endpoint AER handler
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
Rename cxl_error_detected() to cxl_pci_error_detected() and rename
the struct pci_error_handlers instance to cxl_pci_error_handlers to
avoid shadowing the struct type tag.
Document the unconditional CXL RAS read policy: on a dead link,
readl() returns 0xFFFFFFFF which is interpreted as UCE bits set and
triggers a panic. If RAS registers are not mapped the read is
skipped and the frozen/perm_failure switch cases defer to AER
recovery for devices without active CXL.mem traffic.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- Fix cxl_pci_error_detected() to use find_cxl_port_by_uport() and port->uport_dev
- Read CXL RAS unconditionally; panic on UCE regardless of channel state
- Document unconditional read policy and 0xFFFFFFFF behavior in comment
- Drop guard removal paragraph from commit message (not in this diff)
- Drop Reviewed-by tags pending re-review after message change
Changes in v16->v17:
- Rename pci_error_handlers struct instance to cxl_pci_error_handlers to
avoid shadowing the struct type tag.
- Restore scoped_guard(device) and dev->driver check around AER read.
- NULL-check find_cxl_port_by_dev() before deref of port->uport_dev.
- Updated commit message. (Terry)
- Add scope cleanup for port variable in cxl_pci_error_detected() (Terry)
- Drop cxl_uncor_aer_present(), rely on AER state
Changes in v15->v16:
- Update commit message (DaveJ)
- s/cxl_handle_aer()/cxl_uncor_aer_present()/g (Jonathan)
- cxl_uncor_aer_present(): Leave original result calculation based on
if a UCE is present and the provided state (Terry)
- Add call to pci_print_aer(). AER fails to log because is upstream
link (Terry)
Changes in v14->v15:
- Update commit message and title. Added Bjorn's ack.
- Move CE and UCE handling logic here
Changes in v13->v14:
- Add Dave Jiang's review-by
- Update commit message & headline (Bjorn)
- Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to
one line (Jonathan)
- Remove cxl_walk_port() (Dan)
- Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is
sufficient (Dan)
- Remove device_lock_if()
- Combined CE and UCE here (Terry)
Changes in v12->v13:
- Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue
patch (Terry)
- Remove EP case in cxl_get_ras_base(), not used. (Terry)
- Remove check for dport->dport_dev (Dave)
- Remove whitespace (Terry)
Changes in v11->v12:
- Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and
pci_to_cxl_dev()
- Change cxl_error_detected() -> cxl_cor_error_detected()
- Remove NULL variable assignments
- Replace bus_find_device() with find_cxl_port_by_uport() for upstream
port searches.
Changes in v10->v11:
- None
---
drivers/cxl/core/ras.c | 24 +++++++++++++++---------
drivers/cxl/cxlpci.h | 8 ++++----
drivers/cxl/pci.c | 12 ++++++------
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 6f4a3c1b0bb85..d5dc2c22565da 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -328,10 +328,8 @@ bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem
return true;
}
-
-
-pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
- pci_channel_state_t state)
+pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
+ pci_channel_state_t state)
{
struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(&pdev->dev);
bool ue = false;
@@ -349,10 +347,18 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
}
/*
- * A frozen channel indicates an impending reset which is fatal to
- * CXL.mem operation, and will likely crash the system. On the off
- * chance the situation is recoverable dump the status of the RAS
- * capability registers and bounce the active state of the memdev.
+ * The CXL RAS read is unconditional regardless of channel
+ * state. Any uncorrectable error bit set in the CXL RAS
+ * status register triggers a panic because CXL.mem cache
+ * coherency is already lost; continuing risks silent data
+ * corruption across interleaved HDM regions.
+ *
+ * On a dead link readl() returns 0xFFFFFFFF which sets all
+ * UCE bits and also triggers the panic - this is intentional.
+ * If RAS registers are not mapped the read is skipped, the
+ * panic is not reached, and the frozen/perm_failure switch
+ * cases below handle AER recovery for devices without active
+ * CXL.mem traffic.
*/
ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL));
}
@@ -380,7 +386,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
}
return PCI_ERS_RESULT_NEED_RESET;
}
-EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL");
+EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, "CXL");
static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport, int severity)
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 06c46adcf0f6c..8aeb80a4e5732 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -89,13 +89,13 @@ struct cxl_dev_state;
void read_cdat_data(struct cxl_port *port);
#ifdef CONFIG_CXL_RAS
-pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
- pci_channel_state_t state);
+pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
+ pci_channel_state_t state);
void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
void devm_cxl_port_ras_setup(struct cxl_port *port);
#else
-static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
- pci_channel_state_t state)
+static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
+ pci_channel_state_t state)
{
return PCI_ERS_RESULT_NONE;
}
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 5c21db36073fe..6cf1db7b85020 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -1000,18 +1000,18 @@ static void cxl_reset_done(struct pci_dev *pdev)
}
}
-static const struct pci_error_handlers cxl_error_handlers = {
- .error_detected = cxl_error_detected,
- .slot_reset = cxl_slot_reset,
- .resume = cxl_error_resume,
- .reset_done = cxl_reset_done,
+static const struct pci_error_handlers cxl_pci_error_handlers = {
+ .error_detected = cxl_pci_error_detected,
+ .slot_reset = cxl_slot_reset,
+ .resume = cxl_error_resume,
+ .reset_done = cxl_reset_done,
};
static struct pci_driver cxl_pci_driver = {
.name = KBUILD_MODNAME,
.id_table = cxl_mem_pci_tbl,
.probe = cxl_pci_probe,
- .err_handler = &cxl_error_handlers,
+ .err_handler = &cxl_pci_error_handlers,
.dev_groups = cxl_rcd_groups,
.driver = {
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
--
2.34.1
^ permalink raw reply related
* [PATCH v18 08/13] cxl/pci: Thread port and dport through RAS handling helpers
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
From: Dan Williams <djbw@kernel.org>
The callers of cxl_handle_ras() and cxl_handle_cor_ras() already hold
a struct cxl_port * and struct cxl_dport * for the device being
handled. Passing a generic struct device * requires is_cxl_memdev()
to distinguish Endpoints from ports at trace emission time. Threading
port and dport directly enables is_cxl_endpoint(port) and explicit
dport/port branching for cleaner trace dispatch.
Refactor cxl_handle_ras() and cxl_handle_cor_ras() to accept struct
cxl_port * and struct cxl_dport * directly. The CXL RAS trace event
emission logic is split into three branches: Endpoint events are
identified via is_cxl_endpoint(port) and emit with the memdev, dport
events emit with dport->dport_dev, and Upstream Port events fall back
to port->uport_dev.
Update cxl_handle_rdport_errors() in ras_rch.c and
cxl_handle_proto_error() in ras.c to pass port and dport to the
refactored functions.
RCH Downstream Port correctable trace events now report the dport
device (dport->dport_dev) as a consequence of threading port and dport
through the RAS helpers. The following trace event rework ("cxl: Add
port and dport identifiers to CXL AER trace events") adds explicit
memdev, port, dport, and host fields that provide full context for
all device types.
Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Dan Williams <djbw@kernel.org>
---
Changes in v17 -> v18:
- New patch.
---
drivers/cxl/core/core.h | 12 ++++++++----
drivers/cxl/core/ras.c | 29 +++++++++++++++--------------
drivers/cxl/core/ras_rch.c | 2 +-
3 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 272634ff2615b..5ca1275fd8f35 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -185,10 +185,12 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)
#ifdef CONFIG_CXL_RAS
void cxl_ras_init(void);
void cxl_ras_exit(void);
-bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);
+bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport,
+ void __iomem *ras_base);
void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport);
-void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);
+void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport,
+ void __iomem *ras_base);
void cxl_dport_map_rch_aer(struct cxl_dport *dport);
void cxl_disable_rch_root_ints(struct cxl_dport *dport);
void cxl_handle_rdport_errors(struct pci_dev *pdev);
@@ -197,13 +199,15 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
#else
static inline void cxl_ras_init(void) { }
static inline void cxl_ras_exit(void) { }
-static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
+static inline bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport,
+ void __iomem *ras_base)
{
return false;
}
static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport) { }
-static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }
+static inline void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport,
+ void __iomem *ras_base) { }
static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }
static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }
static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { }
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 9a142abcf4f8b..6f4a3c1b0bb85 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -232,7 +232,6 @@ void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport)
void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport)
{
- struct device *dev = dport ? dport->dport_dev : port->uport_dev;
void __iomem *ras_base = to_ras_base(port, dport);
if (!ras_base) {
@@ -241,14 +240,14 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dpo
return;
}
- if (cxl_handle_ras(dev, ras_base))
+ if (cxl_handle_ras(port, dport, ras_base))
panic("CXL cachemem error");
dev_dbg(&pdev->dev,
"CXL UCE signaled but no CXL RAS status bits set\n");
}
-void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
+void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base)
{
u32 status;
void __iomem *addr;
@@ -260,10 +259,12 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
status = readl(addr);
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
- if (is_cxl_memdev(dev))
- trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);
+ if (is_cxl_endpoint(port))
+ trace_cxl_aer_correctable_error(to_cxl_memdev(port->uport_dev), status);
+ else if (dport)
+ trace_cxl_port_aer_correctable_error(dport->dport_dev, status);
else
- trace_cxl_port_aer_correctable_error(dev, status);
+ trace_cxl_port_aer_correctable_error(port->uport_dev, status);
}
}
@@ -288,7 +289,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)
* Log the state of the RAS status registers and prepare them to log the
* next error status. Return 1 if reset needed.
*/
-bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
+bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void __iomem *ras_base)
{
u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] = {};
void __iomem *addr;
@@ -315,10 +316,12 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
}
header_log_copy(ras_base, hl);
- if (is_cxl_memdev(dev))
- trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);
+ if (is_cxl_endpoint(port))
+ trace_cxl_aer_uncorrectable_error(to_cxl_memdev(port->uport_dev), status, fe, hl);
+ else if (dport)
+ trace_cxl_port_aer_uncorrectable_error(dport->dport_dev, status, fe, hl);
else
- trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl);
+ trace_cxl_port_aer_uncorrectable_error(port->uport_dev, status, fe, hl);
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
@@ -351,7 +354,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
* chance the situation is recoverable dump the status of the RAS
* capability registers and bounce the active state of the memdev.
*/
- ue = cxl_handle_ras(port->uport_dev, to_ras_base(port, NULL));
+ ue = cxl_handle_ras(port, NULL, to_ras_base(port, NULL));
}
/*
@@ -382,10 +385,8 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL");
static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,
struct cxl_dport *dport, int severity)
{
- struct device *dev = dport ? dport->dport_dev : port->uport_dev;
-
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(dev, to_ras_base(port, dport));
+ cxl_handle_cor_ras(port, dport, to_ras_base(port, dport));
else
cxl_do_recovery(pdev, port, dport);
}
diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
index f2d2fb83758b9..f4b98f2c11a1c 100644
--- a/drivers/cxl/core/ras_rch.c
+++ b/drivers/cxl/core/ras_rch.c
@@ -118,7 +118,7 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev)
pci_print_aer(pdev, severity, &aer_regs);
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(&pdev->dev, to_ras_base(port, dport));
+ cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport));
else
cxl_do_recovery(pdev, dport->port, dport);
}
--
2.34.1
^ permalink raw reply related
* [PATCH v18 07/13] PCI/CXL: Add RCH support to CXL handlers
From: Terry Bowman @ 2026-07-17 22:27 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
Restricted CXL Host (RCH) error handling is a separate path from the
new CXL Port error handling flow. Fold RCH error handling into the
Port flow so both share a common entry point.
Update cxl_rch_handle_error_iter() to forward RCH protocol errors
through the AER-CXL kfifo. Change cxl_rch_handle_error() return type
from void to bool so handle_error_source() can determine whether work
was enqueued and call cxl_proto_err_flush() before AER recovery
proceeds.
For RC_END devices, __cxl_proto_err_work_fn() calls
cxl_handle_rdport_errors() to process RCH Downstream Port errors,
then falls through to the VH path for RC_END Endpoint handling.
An RCD uncorrectable CXL RAS error now panics via cxl_do_recovery().
Before this patch the RCH Downstream Port UCE path called
cxl_handle_ras() but ignored its return value - no panic. After this
patch the same condition calls cxl_do_recovery() which panics on
confirmed UCE. The Endpoint UCE path already panicked at the parent
commit. This matches the panic policy added in the common CXL Port
protocol error flow.
Remove cxl_cor_error_detected() and its .cor_error_detected
registration in cxl_error_handlers. Correctable Endpoint errors are
now routed through the AER-CXL kfifo like all other CXL protocol
errors.
Drop the cxlds->rcd / cxl_handle_rdport_errors(cxlds) branches from
cxl_error_detected(). RCH downstream port error handling is now
performed by __cxl_proto_err_work_fn() via the kfifo path, which
calls cxl_handle_rdport_errors(pdev) before the common dispatch.
Change cxl_handle_rdport_errors() to take a struct pci_dev * instead
of a struct cxl_dev_state *, matching the new caller context. Re-fetch
dport under guard() to close the TOCTOU window between
cxl_pci_find_port()'s lockless xa_load() and the first dereference of
the returned pointer.
Change find_cxl_port_by_dev() RC_END lookup from
find_cxl_port_by_dport(dev->parent) to find_cxl_port_by_uport(dev),
matching the Endpoint lookup path. RC_END Endpoint port resolution
uses the uport (the RC_END device itself), while the separate RCH
Downstream Port lookup is handled by cxl_handle_rdport_errors().
The RCH Downstream Port and the RCD Endpoint (RC_END) are separate
devices with independent RAS register blocks. cxl_handle_rdport_errors()
handles the RCH Downstream Port RAS. RCD Endpoint (RC_END) is handled in
cxl_handle_proto_error().
Use to_ras_base() in cxl_handle_rdport_errors() instead of referencing
dport->regs.ras directly. Make to_ras_base() non-static in ras.c and
declare it in core.h so ras_rch.c can access it. Route all RAS base address lookups
through a single helper to prepare for CXL RAS error injection testing
that follows this series.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- Pass &pdev->dev instead of dport->port->uport_dev in
cxl_handle_rdport_errors() to avoid dropping RCH trace events.
- Document trace event attribution change.
- Document removal of cxl_cor_error_detected() and cxlds->rcd branches.
- Capitalize Endpoint per PCI spec convention.
- Use to_ras_base() in cxl_handle_rdport_errors() to centralize RAS base
address lookup in preparation for error injection testing.
Changes in v16->v17:
- Drop now-dead cxlds->rcd branches from cxl_{cor_,}error_detected().
- Drop duplicate subject line from commit body.
- Document panic-on-uncorrectable behavior change for RCD path.
- Document trace event device-name change (memN -> PCI BDF) for RCH path.
- Rewrite cxl_handle_proto_error() RC_END comment to clarify RCD/RCH shared
interrupt relationship
- Rewrite commit message
Changes in v16:
- New commit
---
drivers/cxl/core/core.h | 10 +++++--
drivers/cxl/core/ras.c | 50 ++++++++--------------------------
drivers/cxl/core/ras_rch.c | 16 ++++++-----
drivers/cxl/cxlpci.h | 3 --
drivers/cxl/pci.c | 1 -
drivers/pci/pcie/aer.c | 4 +--
drivers/pci/pcie/aer_cxl_rch.c | 39 ++++++++++++--------------
drivers/pci/pcie/portdrv.h | 4 +--
8 files changed, 48 insertions(+), 79 deletions(-)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 7c70bea06c2db..272634ff2615b 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -191,7 +191,8 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);
void cxl_dport_map_rch_aer(struct cxl_dport *dport);
void cxl_disable_rch_root_ints(struct cxl_dport *dport);
-void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);
+void cxl_handle_rdport_errors(struct pci_dev *pdev);
+void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport);
void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
#else
static inline void cxl_ras_init(void) { }
@@ -205,7 +206,12 @@ static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }
static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }
static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }
-static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }
+static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { }
+static inline void __iomem *to_ras_base(struct cxl_port *port,
+ struct cxl_dport *dport)
+{
+ return NULL;
+}
static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { }
#endif /* CONFIG_CXL_RAS */
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index b190e69c2d415..9a142abcf4f8b 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -218,7 +218,8 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL");
-static void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport)
+
+void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport)
{
if (!port)
return NULL;
@@ -324,37 +325,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
return true;
}
-void cxl_cor_error_detected(struct pci_dev *pdev)
-{
- guard(device)(&pdev->dev);
- if (!pdev->dev.driver)
- return;
-
- struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(&pdev->dev);
- if (!port)
- return;
-
- if (is_cxl_restricted(pdev)) {
- struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
- struct cxl_memdev *cxlmd = cxlds->cxlmd;
- scoped_guard(device, &cxlmd->dev) {
- cxl_handle_rdport_errors(cxlds);
- }
- }
-
- scoped_guard(device, &port->dev) {
- if (!port->dev.driver) {
- dev_warn(&pdev->dev,
- "%s: port disabled, abort error handling\n",
- dev_name(&port->dev));
- return;
- }
-
- cxl_handle_cor_ras(port->uport_dev, to_ras_base(port, NULL));
- }
-}
-EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
@@ -365,14 +336,6 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
if (!port)
return PCI_ERS_RESULT_DISCONNECT;
- if (is_cxl_restricted(pdev)) {
- struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
- struct cxl_memdev *cxlmd = cxlds->cxlmd;
-
- scoped_guard(device, &cxlmd->dev) {
- cxl_handle_rdport_errors(cxlds);
- }
- }
scoped_guard(device, &port->dev) {
if (!port->dev.driver) {
@@ -429,6 +392,15 @@ static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,
static void __cxl_proto_err_work_fn(struct cxl_proto_err_work_data *wd)
{
+ /*
+ * For RC_END (RCD) devices, handle RCH Downstream Port errors
+ * first. cxl_handle_rdport_errors() does its own port lookup
+ * and locking, keeping the Downstream Port lock separate from the
+ * Endpoint Port lock taken below.
+ */
+ if (is_cxl_restricted(wd->pdev))
+ cxl_handle_rdport_errors(wd->pdev);
+
struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_dev(&wd->pdev->dev, NULL);
if (!port) {
dev_err_ratelimited(&wd->pdev->dev,
diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c
index 44b335d560708..f2d2fb83758b9 100644
--- a/drivers/cxl/core/ras_rch.c
+++ b/drivers/cxl/core/ras_rch.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2025 AMD Corporation. All rights reserved. */
-#include <linux/types.h>
#include <linux/aer.h>
#include "cxl.h"
#include "core.h"
@@ -96,18 +95,21 @@ static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs,
return false;
}
-void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
+void cxl_handle_rdport_errors(struct pci_dev *pdev)
{
- struct pci_dev *pdev = to_pci_dev(cxlds->dev);
struct aer_capability_regs aer_regs;
struct cxl_dport *dport;
int severity;
- struct cxl_port *port __free(put_cxl_port) =
- cxl_pci_find_port(pdev, &dport);
+ struct cxl_port *port __free(put_cxl_port) = cxl_pci_find_port(pdev, NULL);
if (!port)
return;
+ guard(device)(&port->dev);
+ dport = cxl_find_dport_by_dev(port, pdev->dev.parent);
+ if (!dport)
+ return;
+
if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
return;
@@ -116,7 +118,7 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
pci_print_aer(pdev, severity, &aer_regs);
if (severity == AER_CORRECTABLE)
- cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras);
+ cxl_handle_cor_ras(&pdev->dev, to_ras_base(port, dport));
else
- cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras);
+ cxl_do_recovery(pdev, dport->port, dport);
}
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index b826eb53cf7ba..06c46adcf0f6c 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -89,14 +89,11 @@ struct cxl_dev_state;
void read_cdat_data(struct cxl_port *port);
#ifdef CONFIG_CXL_RAS
-void cxl_cor_error_detected(struct pci_dev *pdev);
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state);
void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
void devm_cxl_port_ras_setup(struct cxl_port *port);
#else
-static inline void cxl_cor_error_detected(struct pci_dev *pdev) { }
-
static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 7c6faee7f85ed..5c21db36073fe 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -1004,7 +1004,6 @@ static const struct pci_error_handlers cxl_error_handlers = {
.error_detected = cxl_error_detected,
.slot_reset = cxl_slot_reset,
.resume = cxl_error_resume,
- .cor_error_detected = cxl_cor_error_detected,
.reset_done = cxl_reset_done,
};
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 2d9d40528e709..0bd23a65e7ebc 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1185,9 +1185,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
{
- bool cxl_pending = false;
-
- cxl_rch_handle_error(dev, info);
+ bool cxl_pending = cxl_rch_handle_error(dev, info);
if (is_cxl_error(dev, info))
cxl_pending |= cxl_forward_error(dev, info);
diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c
index e471eefec9c40..683712fc965ff 100644
--- a/drivers/pci/pcie/aer_cxl_rch.c
+++ b/drivers/pci/pcie/aer_cxl_rch.c
@@ -34,42 +34,37 @@ static bool cxl_error_is_native(struct pci_dev *dev)
return (pcie_ports_native || host->native_aer);
}
+struct cxl_rch_error_ctx {
+ struct aer_err_info *info;
+ bool enqueued;
+};
+
static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
{
- struct aer_err_info *info = (struct aer_err_info *)data;
- const struct pci_error_handlers *err_handler;
+ struct cxl_rch_error_ctx *ctx = data;
if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
return 0;
- guard(device)(&dev->dev);
-
- err_handler = dev->driver ? dev->driver->err_handler : NULL;
- if (!err_handler)
- return 0;
-
- if (info->severity == AER_CORRECTABLE) {
- if (err_handler->cor_error_detected)
- err_handler->cor_error_detected(dev);
- } else if (err_handler->error_detected) {
- if (info->severity == AER_NONFATAL)
- err_handler->error_detected(dev, pci_channel_io_normal);
- else if (info->severity == AER_FATAL)
- err_handler->error_detected(dev, pci_channel_io_frozen);
- }
+ if (cxl_forward_error(dev, ctx->info))
+ ctx->enqueued = true;
return 0;
}
-void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
+bool cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
{
+ struct cxl_rch_error_ctx ctx = { .info = info };
+
/*
- * Internal errors of an RCEC indicate an AER error in an
- * RCH's downstream port. Check and handle them in the CXL.mem
- * device driver.
+ * An RCEC AER internal error indicates an error in an
+ * associated RCH Downstream Port or RC_END device or both.
+ * Forward to the cxl_core module for handling.
*/
if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
is_aer_internal_error(info))
- pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
+ pcie_walk_rcec(dev, cxl_rch_handle_error_iter, &ctx);
+
+ return ctx.enqueued;
}
static int handles_cxl_error_iter(struct pci_dev *dev, void *data)
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index fd203010877bf..807bca90dee0e 100644
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -128,14 +128,14 @@ struct aer_err_info;
#ifdef CONFIG_CXL_RAS
bool is_aer_internal_error(struct aer_err_info *info);
-void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info);
+bool cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info);
void cxl_rch_enable_rcec(struct pci_dev *rcec);
bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info);
bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info);
void cxl_proto_err_flush(void);
#else
static inline bool is_aer_internal_error(struct aer_err_info *info) { return false; }
-static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { }
+static inline bool cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { return false; }
static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { }
static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) { return false; }
static inline bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) { return false; }
--
2.34.1
^ permalink raw reply related
* [PATCH v18 06/13] PCI: Establish common CXL Port protocol error flow
From: Terry Bowman @ 2026-07-17 22:26 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
Add CXL protocol error dispatch in handle_error_source() using
is_cxl_error() and cxl_forward_error() to route errors through the
AER-CXL kfifo. Expand is_cxl_error() from Endpoint-only to include
Root Port, Upstream Port, and Downstream Port device types. The
producer and consumer go live in the same commit to avoid silently
dropping CXL errors during bisect.
For uncorrectable events, call cxl_proto_err_flush() to ensure CXL RAS
registers are read, panic policy is applied, and CXL state is cleared
before pci_aer_handle_error() drives PCIe recovery. Without the flush,
AER recovery can tear down drivers and unmap the CXL RAS iomaps while
the kfifo consumer is still reading them. Correctable events do not
need the flush and run asynchronously. RCH kfifo support is added in
the following patch ("PCI/CXL: Add RCH support to CXL handlers").
Add cxl_handle_proto_error() to dispatch correctable and uncorrectable
errors through the CXL RAS helpers. Add cxl_do_recovery() to coordinate
uncorrectable recovery. Panic when a UCE is confirmed by a successful
CXL RAS status register read. If the RAS registers cannot be read the
UCE cannot be confirmed and panic is not triggered. Gate error handling
on the port driver being bound to avoid processing errors on disabled
devices.
The kfifo consumer holds guard(device)(&port->dev) and checks
port->dev.driver before accessing RAS registers, serializing against
driver unbind and devm iomap teardown. For UCE, cxl_proto_err_flush()
runs the worker synchronously before AER recovery, ensuring the device
is present during RAS register access.
Add to_ras_base() to centralize RAS base lookup: dport->regs.ras for
Root/Downstream Ports, port->regs.ras for Upstream Ports and Endpoints.
Use to_ras_base() to access the CXL devices' RAS registers as it will
provide an avenue to inject status simulation during testing.
Add CXL RAS logging in cxl_handle_cor_ras() and cxl_handle_ras(). The
existing cxl_cor_error_detected() and cxl_error_detected() AER
callbacks remain for all Endpoints and are reworked to use
find_cxl_port_by_uport() and to_ras_base(), with UCE now triggering
panic unconditionally. These callbacks are further updated in the
following patch ("PCI/CXL: Add RCH support to CXL handlers").
Fix a pre-existing race for cxlds between cxl_handle_rdport_errors() and
cxl_memdev_shutdown() by holding a cxlmd device scoped_guard() around
the rdport call. Release the lock before taking the Port lock to avoid
the lock inversion.
Co-developed-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- Fix pre-existing race: hold memdev device lock around
cxl_handle_rdport_errors(), release before port lock
- Fix handle_error_source() to call pci_aer_handle_error() unconditionally
so AER handling always runs after cxl_forward_error()
- Add cxl_proto_err_flush() call for CXL UCE to drain kfifo before AER
recovery tears down the device
- Fix NULL dereference of dport->dport_dev in cxl_handle_cor_ras() and
cxl_handle_ras() for UPSTREAM/ENDPOINT port types: use dport->dport_dev
when dport is non-NULL, else fall back to port->uport_dev
- Remove duplicate pcie_clear_device_status() call from
cxl_handle_proto_error() CE path; pci_aer_handle_error() already clears it
- Clarify panic policy: panic only on confirmed UCE via RAS status read
- Document kfifo consumer serialization against driver unbind via
guard(device)(&port->dev) and port->dev.driver check
Changes in v16->v17:
- get_cxl_port() -> find_cxl_port_by_dev()
- Simplified find_cxl_port_by_dev()
- Replace and remove cxl_serial_number() w/ pci_get_dsn()
- cxl_get_ras_base() -> to_ras_base()
- Drop dependency on PCI_ERS_RESULT_PANIC; cxl_do_recovery() panics
directly. (PANIC enum patch dropped from series.)
- Clarify panic semantics: panic on any uncorrectable CXL RAS error, not
only AER-FATAL severities.
- Add is_cxl_error() switch in handle_error_source() here, paired with the
kfifo consumer registration, to keep each commit bisect-safe.
- Drop pcie_aer_is_native() guard in cxl_do_recovery() (always native).
- Swap order with the "Limit" patch for bisectability w/ cxl_ras_exit()
- Reword for "any uncorrectable" CXL RAS error panics.
- Restore log messages for port-not-found and port-unbound cases.
- Whitespace cleanup (Jonathan)
- Update to get_cxl_port() documentation (Terry)
- Fix __cxl_proto_err_work_fn() to return 0 for transient errors.
- Drop !port check in cxl_do_recovery(), caller already validated
- Fix kerneldoc @pdev -> @dev in find_cxl_port_by_dev()
- Fix missing space in pr_err_ratelimited()
- Made pcie_clear_device_status() and pci_aer_clear_fatal_status()
EXPORT_SYMBOL_FOR_MODULES("cxl_core") (Dan)
- Move find_cxl_port_by_dport() and find_cxl_port_by_uport()
de-staticisation and core.h declarations from the rename patch to
here, where the first cross-file callers in find_cxl_port_by_dev()
land.
Changes in v15->v16:
- get_ras_base(), initialize dport to NULL (Jonathan)
- Remove guard(device)(&cxlmd->dev) (Jonathan)
- Fix dev_warns() (Jonathan)
- Remove comment in cxl_port_error_detected() (Dan)
- Update switch-case brackets to follow clang-format (Dan)
- Add PCI_EXP_TYPE_RC_END for cxl_get_ras_base() (Terry)
- Add NULL port check in cxl_serial_number() (Terry)
Changes in v14->v15:
- Update commit message and title. Added Bjorn's ack.
- Move CE and UCE handling logic here
Changes in v13->v14:
- Add Dave Jiang's review-by
- Update commit message & headline (Bjorn)
- Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to
one line (Jonathan)
- Remove cxl_walk_port() (Dan)
- Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is
sufficient (Dan)
- Remove device_lock_if()
- Combined CE and UCE here (Terry)
Changes in v12->v13:
- Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue
patch (Terry)
- Remove EP case in cxl_get_ras_base(), not used. (Terry)
- Remove check for dport->dport_dev (Dave)
- Remove whitespace (Terry)
Changes in v11->v12:
- Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and
pci_to_cxl_dev()
- Change cxl_error_detected() -> cxl_cor_error_detected()
- Remove NULL variable assignments
- Replace bus_find_device() with find_cxl_port_by_uport() for upstream
port searches.
Changes in v10->v11:
- None
---
drivers/cxl/core/core.h | 7 ++
drivers/cxl/core/port.c | 6 +-
drivers/cxl/core/ras.c | 223 +++++++++++++++++++++++++++-------
drivers/pci/pci.h | 1 -
drivers/pci/pcie/aer.c | 13 ++
drivers/pci/pcie/aer_cxl_vh.c | 16 ++-
6 files changed, 220 insertions(+), 46 deletions(-)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 23fe40ddf4c6b..7c70bea06c2db 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -186,6 +186,8 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)
void cxl_ras_init(void);
void cxl_ras_exit(void);
bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);
+void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
+ struct cxl_dport *dport);
void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);
void cxl_dport_map_rch_aer(struct cxl_dport *dport);
void cxl_disable_rch_root_ints(struct cxl_dport *dport);
@@ -198,6 +200,8 @@ static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
{
return false;
}
+static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port,
+ struct cxl_dport *dport) { }
static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }
static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }
static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }
@@ -206,6 +210,9 @@ static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { }
#endif /* CONFIG_CXL_RAS */
int cxl_gpf_port_setup(struct cxl_dport *dport);
+struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev,
+ struct cxl_dport **dport);
+struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev);
struct cxl_hdm;
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index cadb51f70f854..a76f3ee05cba8 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1400,8 +1400,8 @@ static struct cxl_port *__find_cxl_port_by_dport(struct cxl_find_port_ctx *ctx)
* Return a 'struct cxl_port' with an elevated reference if found. Use
* __free(put_cxl_port) to release.
*/
-static struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev,
- struct cxl_dport **dport)
+struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev,
+ struct cxl_dport **dport)
{
struct cxl_find_port_ctx ctx = {
.dport_dev = dport_dev,
@@ -1596,7 +1596,7 @@ static int match_port_by_uport(struct device *dev, const void *data)
* Function takes a device reference on the port device. Caller should do a
* put_device() when done.
*/
-static struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev)
+struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev)
{
struct device *dev;
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 135f1997e6f4f..b190e69c2d415 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -77,6 +77,36 @@ static int match_memdev_by_parent(struct device *dev, const void *uport)
return 0;
}
+
+/**
+ * find_cxl_port_by_dev - Use @dev as hint to do a _by_dport or _by_uport lookup
+ * @dev: generic device that may either be a companion of port or target dport
+ * @dport: output parameter; set to the matched dport for dport-class
+ * lookups (Root Port, Downstream Port), NULL otherwise.
+ *
+ * Return a 'struct cxl_port' with an elevated reference if found. Use
+ * __free(put_cxl_port) to release.
+ */
+static struct cxl_port *find_cxl_port_by_dev(struct device *dev, struct cxl_dport **dport)
+{
+ if (dport)
+ *dport = NULL;
+ if (!dev_is_pci(dev))
+ return NULL;
+
+ switch (pci_pcie_type(to_pci_dev(dev))) {
+ case PCI_EXP_TYPE_ROOT_PORT:
+ case PCI_EXP_TYPE_DOWNSTREAM:
+ return find_cxl_port_by_dport(dev, dport);
+ case PCI_EXP_TYPE_UPSTREAM:
+ case PCI_EXP_TYPE_ENDPOINT:
+ case PCI_EXP_TYPE_RC_END:
+ return find_cxl_port_by_uport(dev);
+ }
+
+ return NULL;
+}
+
void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
{
unsigned int devfn = PCI_DEVFN(data->prot_err.agent_addr.device,
@@ -132,16 +162,6 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)
}
static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
-void cxl_ras_init(void)
-{
- cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work);
-}
-
-void cxl_ras_exit(void)
-{
- cxl_cper_unregister_prot_err_work();
-}
-
static void cxl_dport_map_ras(struct cxl_dport *dport)
{
struct cxl_register_map *map = &dport->reg_map;
@@ -198,10 +218,39 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL");
+static void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport)
+{
+ if (!port)
+ return NULL;
+
+ if (dport)
+ return dport->regs.ras;
+
+ return port->regs.ras;
+}
+
+void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport)
+{
+ struct device *dev = dport ? dport->dport_dev : port->uport_dev;
+ void __iomem *ras_base = to_ras_base(port, dport);
+
+ if (!ras_base) {
+ dev_err(&pdev->dev,
+ "CXL UCE signaled but RAS registers not mapped\n");
+ return;
+ }
+
+ if (cxl_handle_ras(dev, ras_base))
+ panic("CXL cachemem error");
+
+ dev_dbg(&pdev->dev,
+ "CXL UCE signaled but no CXL RAS status bits set\n");
+}
+
void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
{
- void __iomem *addr;
u32 status;
+ void __iomem *addr;
if (!ras_base)
return;
@@ -210,7 +259,10 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)
status = readl(addr);
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
- trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);
+ if (is_cxl_memdev(dev))
+ trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);
+ else
+ trace_cxl_port_aer_correctable_error(dev, status);
}
}
@@ -262,7 +314,11 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
}
header_log_copy(ras_base, hl);
- trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);
+ if (is_cxl_memdev(dev))
+ trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);
+ else
+ trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl);
+
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
return true;
@@ -270,22 +326,32 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
void cxl_cor_error_detected(struct pci_dev *pdev)
{
- struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
- struct cxl_memdev *cxlmd = cxlds->cxlmd;
- struct device *dev = &cxlds->cxlmd->dev;
+ guard(device)(&pdev->dev);
+ if (!pdev->dev.driver)
+ return;
+
+ struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(&pdev->dev);
+ if (!port)
+ return;
+
+ if (is_cxl_restricted(pdev)) {
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ struct cxl_memdev *cxlmd = cxlds->cxlmd;
- scoped_guard(device, dev) {
- if (!dev->driver) {
+ scoped_guard(device, &cxlmd->dev) {
+ cxl_handle_rdport_errors(cxlds);
+ }
+ }
+
+ scoped_guard(device, &port->dev) {
+ if (!port->dev.driver) {
dev_warn(&pdev->dev,
- "%s: memdev disabled, abort error handling\n",
- dev_name(dev));
+ "%s: port disabled, abort error handling\n",
+ dev_name(&port->dev));
return;
}
- if (cxlds->rcd)
- cxl_handle_rdport_errors(cxlds);
-
- cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);
+ cxl_handle_cor_ras(port->uport_dev, to_ras_base(port, NULL));
}
}
EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
@@ -293,42 +359,53 @@ EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
- struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
- struct cxl_memdev *cxlmd = cxlds->cxlmd;
- struct device *dev = &cxlmd->dev;
- bool ue;
+ struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(&pdev->dev);
+ bool ue = false;
- scoped_guard(device, dev) {
- if (!dev->driver) {
+ if (!port)
+ return PCI_ERS_RESULT_DISCONNECT;
+
+ if (is_cxl_restricted(pdev)) {
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ struct cxl_memdev *cxlmd = cxlds->cxlmd;
+
+ scoped_guard(device, &cxlmd->dev) {
+ cxl_handle_rdport_errors(cxlds);
+ }
+ }
+
+ scoped_guard(device, &port->dev) {
+ if (!port->dev.driver) {
dev_warn(&pdev->dev,
- "%s: memdev disabled, abort error handling\n",
- dev_name(dev));
+ "%s: port disabled, abort error handling\n",
+ dev_name(&port->dev));
return PCI_ERS_RESULT_DISCONNECT;
}
- if (cxlds->rcd)
- cxl_handle_rdport_errors(cxlds);
/*
* A frozen channel indicates an impending reset which is fatal to
* CXL.mem operation, and will likely crash the system. On the off
* chance the situation is recoverable dump the status of the RAS
* capability registers and bounce the active state of the memdev.
*/
- ue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);
+ ue = cxl_handle_ras(port->uport_dev, to_ras_base(port, NULL));
}
+ /*
+ * CXL.mem UCE means cache coherency is lost. Continuing risks
+ * silent data corruption across interleaved HDM regions.
+ */
+ if (ue)
+ panic("CXL cachemem error");
+
switch (state) {
case pci_channel_io_normal:
- if (ue) {
- device_release_driver(dev);
- return PCI_ERS_RESULT_NEED_RESET;
- }
return PCI_ERS_RESULT_CAN_RECOVER;
case pci_channel_io_frozen:
dev_warn(&pdev->dev,
"%s: frozen state error detected, disable CXL.mem\n",
- dev_name(dev));
- device_release_driver(dev);
+ dev_name(port->uport_dev));
+ device_release_driver(port->uport_dev);
return PCI_ERS_RESULT_NEED_RESET;
case pci_channel_io_perm_failure:
dev_warn(&pdev->dev,
@@ -338,3 +415,67 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
return PCI_ERS_RESULT_NEED_RESET;
}
EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL");
+
+static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,
+ struct cxl_dport *dport, int severity)
+{
+ struct device *dev = dport ? dport->dport_dev : port->uport_dev;
+
+ if (severity == AER_CORRECTABLE)
+ cxl_handle_cor_ras(dev, to_ras_base(port, dport));
+ else
+ cxl_do_recovery(pdev, port, dport);
+}
+
+static void __cxl_proto_err_work_fn(struct cxl_proto_err_work_data *wd)
+{
+ struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_dev(&wd->pdev->dev, NULL);
+ if (!port) {
+ dev_err_ratelimited(&wd->pdev->dev,
+ "Failed to find parent port device in CXL topology\n");
+ return;
+ }
+ guard(device)(&port->dev);
+ if (!port->dev.driver) {
+ dev_err_ratelimited(&port->dev,
+ "Port device is unbound, abort error handling\n");
+ return;
+ }
+
+ struct cxl_dport *dport = cxl_find_dport_by_dev(port, &wd->pdev->dev);
+ if (!dport && (pci_pcie_type(wd->pdev) == PCI_EXP_TYPE_ROOT_PORT ||
+ pci_pcie_type(wd->pdev) == PCI_EXP_TYPE_DOWNSTREAM)) {
+ dev_err_ratelimited(&wd->pdev->dev,
+ "Failed to find dport device in CXL topology\n");
+ return;
+ }
+
+ cxl_handle_proto_error(wd->pdev, port, dport, wd->severity);
+}
+
+static void cxl_proto_err_work_fn(struct work_struct *work)
+{
+ struct cxl_proto_err_work_data wd;
+
+ for_each_cxl_proto_err(&wd, __cxl_proto_err_work_fn);
+}
+
+static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn);
+
+static void cxl_proto_err_do_flush(void)
+{
+ flush_work(&cxl_proto_err_work);
+}
+
+void cxl_ras_init(void)
+{
+ cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work);
+ cxl_register_proto_err_work(&cxl_proto_err_work,
+ cxl_proto_err_do_flush);
+}
+
+void cxl_ras_exit(void)
+{
+ cxl_unregister_proto_err_work();
+ cxl_cper_unregister_prot_err_work();
+}
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4469e1a77f3c1..a83e2aef75912 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -1296,7 +1296,6 @@ void pci_restore_aer_state(struct pci_dev *dev);
static inline void pci_no_aer(void) { }
static inline void pci_aer_init(struct pci_dev *d) { }
static inline void pci_aer_exit(struct pci_dev *d) { }
-static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
static inline void pci_save_aer_state(struct pci_dev *dev) { }
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index c5bce25df51cb..2d9d40528e709 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1185,7 +1185,20 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
{
+ bool cxl_pending = false;
+
cxl_rch_handle_error(dev, info);
+
+ if (is_cxl_error(dev, info))
+ cxl_pending |= cxl_forward_error(dev, info);
+
+ /*
+ * Wait for UCE CXL work to complete before AER recovery
+ * tears down the device. CE can run asynchronously.
+ */
+ if (cxl_pending && info->severity != AER_CORRECTABLE)
+ cxl_proto_err_flush();
+
pci_aer_handle_error(dev, info);
pci_dev_put(dev);
}
diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c
index 93bed07936100..ecf47bba0c9d4 100644
--- a/drivers/pci/pcie/aer_cxl_vh.c
+++ b/drivers/pci/pcie/aer_cxl_vh.c
@@ -49,8 +49,22 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info)
if (!info || !info->is_cxl)
return false;
- if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT)
+ /*
+ * RC_END (Restricted CXL Device) is not included here because RC_END
+ * reports errors on behalf of upstream RCH Downstream Port and thus
+ * requires a unique discovery detailed in CXL4.0 spec (12.2.1.1).
+ * The RCH device error discovery and RC_END forwarding flow begins
+ * in cxl_rch_handle_error().
+ */
+ switch (pci_pcie_type(pdev)) {
+ case PCI_EXP_TYPE_ENDPOINT:
+ case PCI_EXP_TYPE_ROOT_PORT:
+ case PCI_EXP_TYPE_UPSTREAM:
+ case PCI_EXP_TYPE_DOWNSTREAM:
+ break;
+ default:
return false;
+ }
return is_aer_internal_error(info);
}
--
2.34.1
^ permalink raw reply related
* [PATCH v18 05/13] PCI/AER: Introduce AER-CXL protocol error kfifo
From: Terry Bowman @ 2026-07-17 22:26 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
CXL VH RAS handling requires a path for the AER driver to hand off
CXL protocol errors to cxl_core for logging and recovery before PCIe
AER recovery tears down the device. Add
drivers/pci/pcie/aer_cxl_vh.c to implement this handoff via a kfifo-backed
work item.
Introduce is_aer_internal_error() to identify CXL protocol errors
from AER internal error status bits across both correctable and
uncorrectable severities.
Introduce is_cxl_error() to gate the VH kfifo path.
Introduce struct cxl_proto_err_work_data to carry the error source
PCI device and severity through the kfifo. Encapsulate the kfifo,
per-producer spinlock, registration rwsem, and work pointer in struct
cxl_proto_err_kfifo. Initialize the embedded kfifo via INIT_KFIFO()
from a subsys_initcall so its metadata is populated before any
producer or consumer runs.
Introduce cxl_forward_error() to enqueue a CXL protocol error. A
reference is taken on the PCI device; the consumer releases it via
for_each_cxl_proto_err(). On enqueue failure the reference is
released immediately, the error is dropped, and the consumer is
scheduled to drain existing entries. A subsequent patch wires
cxl_forward_error() into handle_error_source() where correctable and
uncorrectable status clearing is left to pci_aer_handle_error().
Introduce cxl_proto_err_flush() to synchronously wait for the
consumer worker to drain the kfifo. A subsequent patch wires this
into handle_error_source() for UCE events so the CXL plane completes
error handling and panic policy before pci_aer_handle_error() drives
PCIe recovery.
Introduce cxl_register_proto_err_work() and
cxl_unregister_proto_err_work() for cxl_core to register and
deregister its work handler. On unregistration, pending kfifo entries
are drained and their pdev references released before
cancel_work_sync() runs. Export these and for_each_cxl_proto_err()
via EXPORT_SYMBOL_FOR_MODULES restricted to cxl_core.
Protect the work pointer with a rwsem to correctly serialize
registration, deregistration, enqueue, and dequeue against concurrent
AER IRQ threads. Serialize concurrent kfifo writers with a spinlock.
Add MAINTAINERS entries for aer_cxl_vh.c and aer_cxl_rch.c under
the CXL entry so CXL maintainers are CC'd on changes to the AER-CXL
bridging code.
Co-developed-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Dan Williams <djbw@kernel.org>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
Changes in v17->v18:
- Remove correctable status clear from cxl_forward_error(); the AER core
clears all status bits via pci_aer_handle_error() info->status writeback
- Schedule consumer on kfifo overflow so existing entries can be drained
Changes in v16->v17:
- Reword "kfifo semaphore" to "kfifo spinlock" to match fifo_lock.
- Defer the handle_error_source() is_cxl_error() switch to the patch that
registers the kfifo consumer to keep each commit bisect-safe.
- Rename rwsema to rwsem
- Change CPER exports to use EXPORT_SYMBOL_FOR_MODULES.
- Add work cancel function.
- Replace kfifo_put() with kfifo_in_spinlocked() for multiple producers
- Add fifo_lock spinlock for concurrent producer serialisation
- Initialize the embedded kfifo with INIT_KFIFO() in a subsys_initcall so
kfifo->mask, ->esize and ->data are set before first use.
- Clear PCI_ERR_COR_STATUS in cxl_forward_error() after enqueue so the
device is acked for correctable events even when the consumer drops the
event. Uncorrectable status is left for cxl_do_recovery() to clear after
recovery completes, mirroring the AER core convention.
- WARN on double-registration in cxl_register_proto_err_work() to make an
unintended second consumer visible at runtime.
- Add direct rwsem.h, cleanup.h and workqueue.h includes for symbols used
in aer_cxl_vh.c
- Add MAINTAINERS entries for drivers/pci/pcie/aer_cxl_*.c
- Update message
---
MAINTAINERS | 2 +
drivers/pci/pcie/Makefile | 1 +
drivers/pci/pcie/aer.c | 10 --
drivers/pci/pcie/aer_cxl_vh.c | 221 ++++++++++++++++++++++++++++++++++
drivers/pci/pcie/portdrv.h | 6 +
include/linux/aer.h | 24 ++++
6 files changed, 254 insertions(+), 10 deletions(-)
create mode 100644 drivers/pci/pcie/aer_cxl_vh.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 806bd2d80d153..39007aa90b20f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6526,6 +6526,8 @@ S: Maintained
F: Documentation/driver-api/cxl
F: Documentation/userspace-api/fwctl/fwctl-cxl.rst
F: drivers/cxl/
+F: drivers/pci/pcie/aer_cxl_rch.c
+F: drivers/pci/pcie/aer_cxl_vh.c
F: include/cxl/
F: include/uapi/linux/cxl_mem.h
F: tools/testing/cxl/
diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile
index b0b43a18c304b..62d3d3c69a5df 100644
--- a/drivers/pci/pcie/Makefile
+++ b/drivers/pci/pcie/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o bwctrl.o
obj-y += aspm.o
obj-$(CONFIG_PCIEAER) += aer.o err.o tlp.o
obj-$(CONFIG_CXL_RAS) += aer_cxl_rch.o
+obj-$(CONFIG_CXL_RAS) += aer_cxl_vh.o
obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o
obj-$(CONFIG_PCIE_PME) += pme.o
obj-$(CONFIG_PCIE_DPC) += dpc.o
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index c4fd9c0b2a548..c5bce25df51cb 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -1150,16 +1150,6 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
*/
EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core");
-#ifdef CONFIG_CXL_RAS
-bool is_aer_internal_error(struct aer_err_info *info)
-{
- if (info->severity == AER_CORRECTABLE)
- return info->status & PCI_ERR_COR_INTERNAL;
-
- return info->status & PCI_ERR_UNC_INTN;
-}
-#endif
-
/**
* pci_aer_handle_error - handle logging error into an event log
* @dev: pointer to pci_dev data structure of error source device
diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c
new file mode 100644
index 0000000000000..93bed07936100
--- /dev/null
+++ b/drivers/pci/pcie/aer_cxl_vh.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2026 AMD Corporation. All rights reserved. */
+
+#include <linux/aer.h>
+#include <linux/atomic.h>
+#include <linux/cleanup.h>
+#include <linux/init.h>
+#include <linux/kfifo.h>
+#include <linux/rwsem.h>
+#include <linux/wait_bit.h>
+#include <linux/workqueue.h>
+#include "../pci.h"
+#include "portdrv.h"
+
+#define CXL_ERROR_SOURCES_MAX 128
+
+struct cxl_proto_err_kfifo {
+ struct work_struct *work;
+ void (*flush)(void);
+ struct rw_semaphore rwsem;
+ spinlock_t fifo_lock;
+ atomic_t flush_inflight;
+ DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data,
+ CXL_ERROR_SOURCES_MAX);
+};
+
+static struct cxl_proto_err_kfifo cxl_proto_err_kfifo = {
+ .rwsem = __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rwsem),
+ .fifo_lock = __SPIN_LOCK_UNLOCKED(cxl_proto_err_kfifo.fifo_lock),
+};
+
+static int __init cxl_proto_err_kfifo_init(void)
+{
+ INIT_KFIFO(cxl_proto_err_kfifo.fifo);
+ return 0;
+}
+subsys_initcall(cxl_proto_err_kfifo_init);
+
+bool is_aer_internal_error(struct aer_err_info *info)
+{
+ if (info->severity == AER_CORRECTABLE)
+ return info->status & PCI_ERR_COR_INTERNAL;
+
+ return info->status & PCI_ERR_UNC_INTN;
+}
+
+bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info)
+{
+ if (!info || !info->is_cxl)
+ return false;
+
+ if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT)
+ return false;
+
+ return is_aer_internal_error(info);
+}
+
+/**
+ * cxl_forward_error - Forward a CXL protocol error to the CXL subsystem via kfifo
+ * @pdev: PCI device that reported the AER error
+ * @info: AER error info containing severity and status
+ *
+ * Producer side of the AER-CXL kfifo. Enqueues a CXL protocol error work
+ * item and schedules the consumer workqueue. Takes a reference on @pdev
+ * that the consumer releases after handling.
+ *
+ * Return: true if the caller must flush the kfifo before AER recovery,
+ * false if no CXL error handling was initiated due to early return on
+ * error.
+ */
+bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info)
+{
+ struct cxl_proto_err_work_data wd = {
+ .severity = info->severity,
+ .pdev = pdev,
+ };
+
+ guard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);
+
+ if (!cxl_proto_err_kfifo.work) {
+ dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo reader not registered\n");
+ return false;
+ }
+
+ /*
+ * Reference discipline: the AER caller (handle_error_source())
+ * holds a ref on @pdev for the duration of this call and releases
+ * it on return. Take a fresh ref here so the pdev stays live while
+ * queued in the kfifo; the consumer (for_each_cxl_proto_err())
+ * drops that ref after handling. On enqueue failure below, drop
+ * the ref we just took to avoid a leak.
+ */
+ pci_dev_get(pdev);
+
+ /* Serialize concurrent kfifo writers: multiple AER threaded IRQs */
+ if (!kfifo_in_spinlocked(&cxl_proto_err_kfifo.fifo, &wd, 1,
+ &cxl_proto_err_kfifo.fifo_lock)) {
+ /* Dropped; no panic - UCE unconfirmed without RAS read */
+ dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo add failed\n");
+ pci_dev_put(pdev);
+ schedule_work(cxl_proto_err_kfifo.work);
+ return true;
+ }
+
+ schedule_work(cxl_proto_err_kfifo.work);
+ return true;
+}
+
+void cxl_register_proto_err_work(struct work_struct *work,
+ void (*flush)(void))
+{
+ guard(rwsem_write)(&cxl_proto_err_kfifo.rwsem);
+
+ /*
+ * Warn on double-registration to surface driver bugs (e.g. missing
+ * cxl_unregister_proto_err_work() on module exit)
+ */
+ if (WARN(cxl_proto_err_kfifo.work,
+ "AER-CXL kfifo consumer already registered\n"))
+ return;
+ cxl_proto_err_kfifo.work = work;
+ cxl_proto_err_kfifo.flush = flush;
+}
+EXPORT_SYMBOL_FOR_MODULES(cxl_register_proto_err_work, "cxl_core");
+
+static struct work_struct *cancel_cxl_proto_err(void)
+{
+ struct work_struct *work;
+ struct cxl_proto_err_work_data wd;
+
+ guard(rwsem_write)(&cxl_proto_err_kfifo.rwsem);
+ work = cxl_proto_err_kfifo.work;
+ cxl_proto_err_kfifo.work = NULL;
+ cxl_proto_err_kfifo.flush = NULL;
+
+ /* rwsem_write excludes all producers; fifo_lock not needed */
+ while (kfifo_get(&cxl_proto_err_kfifo.fifo, &wd)) {
+ dev_err_ratelimited(&wd.pdev->dev,
+ "AER-CXL error report canceled\n");
+ pci_dev_put(wd.pdev);
+ }
+ return work;
+}
+
+void cxl_unregister_proto_err_work(void)
+{
+ struct work_struct *work;
+
+ lockdep_assert_not_held(&cxl_proto_err_kfifo.rwsem);
+
+ work = cancel_cxl_proto_err();
+
+ /* Wait for any in-flight cxl_proto_err_flush() calls to complete */
+ wait_var_event(&cxl_proto_err_kfifo.flush_inflight,
+ atomic_read(&cxl_proto_err_kfifo.flush_inflight) == 0);
+
+ if (work)
+ cancel_work_sync(work);
+}
+EXPORT_SYMBOL_FOR_MODULES(cxl_unregister_proto_err_work, "cxl_core");
+
+/**
+ * for_each_cxl_proto_err - Call a function for each kfifo work item
+ *
+ * Single-consumer invariant: this function is only called from
+ * cxl_proto_err_work_fn() via a single DECLARE_WORK.
+ *
+ * Holds rwsem_read internally; fn() must not call cxl_register_proto_err_work()
+ * or cxl_unregister_proto_err_work().
+ */
+void for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,
+ cxl_proto_err_fn_t fn)
+{
+ guard(rwsem_read)(&cxl_proto_err_kfifo.rwsem);
+ while (kfifo_get(&cxl_proto_err_kfifo.fifo, wd)) {
+ fn(wd);
+ pci_dev_put(wd->pdev);
+ }
+}
+EXPORT_SYMBOL_FOR_MODULES(for_each_cxl_proto_err, "cxl_core");
+
+/**
+ * cxl_proto_err_flush - drain pending AER-CXL kfifo work synchronously
+ *
+ * Wait for the consumer worker to finish processing all entries
+ * currently in the kfifo. Used by handle_error_source() for UCE so
+ * the CXL plane can read CXL RAS, apply panic policy, and clear CXL
+ * state before pci_aer_handle_error() drives PCIe recovery.
+ *
+ * Snapshots the flush callback under rwsem_read and releases the rwsem
+ * before calling it. This avoids holding rwsem_read across flush_work(),
+ * which would deadlock via the rwsem HANDOFF mechanism when a concurrent
+ * rwsem_write waiter (cxl_unregister_proto_err_work) blocks new readers
+ * including the worker's for_each_cxl_proto_err() rwsem_read acquisition.
+ *
+ * The flush_inflight counter prevents cxl_core module unload while a
+ * flush is in progress outside the rwsem. The counter is incremented
+ * under rwsem_read (mutually exclusive with the rwsem_write in
+ * cancel_cxl_proto_err() that NULLs the flush pointer) and decremented
+ * after the flush completes. cxl_unregister_proto_err_work() waits for
+ * the counter to reach zero before proceeding with cancel_work_sync().
+ *
+ * For correctable events the consumer can run asynchronously; AER
+ * does not need to call this helper for AER_CORRECTABLE.
+ */
+void cxl_proto_err_flush(void)
+{
+ void (*flush)(void);
+
+ scoped_guard(rwsem_read, &cxl_proto_err_kfifo.rwsem) {
+ flush = cxl_proto_err_kfifo.flush;
+ if (flush)
+ atomic_inc(&cxl_proto_err_kfifo.flush_inflight);
+ }
+
+ if (flush) {
+ flush();
+ if (atomic_dec_and_test(&cxl_proto_err_kfifo.flush_inflight))
+ wake_up_var(&cxl_proto_err_kfifo.flush_inflight);
+ }
+}
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index cc58bf2f2c844..fd203010877bf 100644
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -130,9 +130,15 @@ struct aer_err_info;
bool is_aer_internal_error(struct aer_err_info *info);
void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info);
void cxl_rch_enable_rcec(struct pci_dev *rcec);
+bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info);
+bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info);
+void cxl_proto_err_flush(void);
#else
static inline bool is_aer_internal_error(struct aer_err_info *info) { return false; }
static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { }
static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { }
+static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) { return false; }
+static inline bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) { return false; }
+static inline void cxl_proto_err_flush(void) { }
#endif /* CONFIG_CXL_RAS */
#endif /* _PORTDRV_H_ */
diff --git a/include/linux/aer.h b/include/linux/aer.h
index df0f5c382286f..8eba3192e2d15 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -25,6 +25,7 @@
#define PCIE_STD_MAX_TLP_HEADERLOG (PCIE_STD_NUM_TLP_HEADERLOG + 10)
struct pci_dev;
+struct work_struct;
struct pcie_tlp_log {
union {
@@ -66,6 +67,29 @@ static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }
#endif
+#ifdef CONFIG_CXL_RAS
+/**
+ * struct cxl_proto_err_work_data - Error information used in CXL error handling
+ * @pdev: PCI device detecting the error
+ * @severity: AER severity
+ */
+struct cxl_proto_err_work_data {
+ struct pci_dev *pdev;
+ int severity;
+};
+
+/**
+ * Callback for processing a CXL protocol error from the AER-CXL kfifo.
+ */
+typedef void (*cxl_proto_err_fn_t)(struct cxl_proto_err_work_data *wd);
+
+void cxl_register_proto_err_work(struct work_struct *work,
+ void (*flush)(void));
+void for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd,
+ cxl_proto_err_fn_t fn);
+void cxl_unregister_proto_err_work(void);
+#endif
+
void pci_print_aer(struct pci_dev *dev, int aer_severity,
struct aer_capability_regs *aer);
int cper_severity_to_aer(int cper_severity);
--
2.34.1
^ permalink raw reply related
* [PATCH v18 04/13] cxl: Rename find_cxl_port() to find_cxl_port_by_dport()
From: Terry Bowman @ 2026-07-17 22:26 UTC (permalink / raw)
To: Bjorn Helgaas, Dan Williams, Dave Jiang, Ira Weiny,
Jonathan Cameron, Len Brown, Rafael J . Wysocki, Robert Richter
Cc: linux-acpi, linux-cxl, linux-doc, linux-kernel, linux-pci,
linuxppc-dev, Alejandro Lucero, Alison Schofield, Ankit Agrawal,
Ard Biesheuvel, Ben Cheatham, Borislav Petkov, Breno Leitao,
Davidlohr Bueso, Fabio M . De Francesco, Gregory Price,
Hanjun Guo, Jonathan Corbet, Kees Cook,
Kuppuswamy Sathyanarayanan, Li Ming, Mahesh J Salgaonkar,
Mauro Carvalho Chehab, Oliver O'Halloran, Shiju Jose,
Shuah Khan, Shuai Xue, Smita Koralahalli, Terry Bowman, Tony Luck,
Vishal Verma
In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com>
From: Dan Williams <djbw@kernel.org>
find_cxl_port() and find_cxl_port_by_uport() are internal port lookup
functions that search the CXL bus by dport and uport respectively, but
their names do not make the lookup method clear.
Rename find_cxl_port() to find_cxl_port_by_dport() to make the lookup
method explicit and consistent with find_cxl_port_by_uport(). Both
functions remain static to port.c; the upcoming patch that adds the
first cross-file caller will widen their scope.
Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Dan Williams <djbw@kernel.org>
---
Changes in v17 -> v18:
- New commit
---
drivers/cxl/core/port.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index f90f899c31d07..cadb51f70f854 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1379,7 +1379,7 @@ static int match_port_by_dport(struct device *dev, const void *data)
return dport != NULL;
}
-static struct cxl_port *__find_cxl_port(struct cxl_find_port_ctx *ctx)
+static struct cxl_port *__find_cxl_port_by_dport(struct cxl_find_port_ctx *ctx)
{
struct device *dev;
@@ -1392,8 +1392,16 @@ static struct cxl_port *__find_cxl_port(struct cxl_find_port_ctx *ctx)
return NULL;
}
-static struct cxl_port *find_cxl_port(struct device *dport_dev,
- struct cxl_dport **dport)
+/**
+ * find_cxl_port_by_dport - find a cxl_port by one of its targets
+ * @dport_dev: device representing the dport target
+ * @dport: optional output of the 'struct cxl_dport' companion of the @dport_dev
+ *
+ * Return a 'struct cxl_port' with an elevated reference if found. Use
+ * __free(put_cxl_port) to release.
+ */
+static struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev,
+ struct cxl_dport **dport)
{
struct cxl_find_port_ctx ctx = {
.dport_dev = dport_dev,
@@ -1401,7 +1409,7 @@ static struct cxl_port *find_cxl_port(struct device *dport_dev,
};
struct cxl_port *port;
- port = __find_cxl_port(&ctx);
+ port = __find_cxl_port_by_dport(&ctx);
return port;
}
@@ -1895,14 +1903,14 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, "CXL");
struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev,
struct cxl_dport **dport)
{
- return find_cxl_port(pdev->dev.parent, dport);
+ return find_cxl_port_by_dport(pdev->dev.parent, dport);
}
EXPORT_SYMBOL_NS_GPL(cxl_pci_find_port, "CXL");
struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
struct cxl_dport **dport)
{
- return find_cxl_port(grandparent(&cxlmd->dev), dport);
+ return find_cxl_port_by_dport(grandparent(&cxlmd->dev), dport);
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, "CXL");
--
2.34.1
^ permalink raw reply related
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