From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Shuai Xue <xueshuai@linux.alibaba.com>, linux-edac@vger.kernel.org
Cc: yazen.ghannam@amd.com, linux-kernel@vger.kernel.org,
tony.luck@intel.com, x86@kernel.org, muralidhara.mk@amd.com,
joao.m.martins@oracle.com, william.roche@oracle.com,
boris.ostrovsky@oracle.com, john.allen@amd.com,
baolin.wang@linux.alibaba.com
Subject: Re: [PATCH 2/3] x86/mce: Define amd_mce_usable_address()
Date: Wed, 14 Jun 2023 11:09:10 -0400 [thread overview]
Message-ID: <1e9b1a0c-564d-6a3c-c253-1b1da1773ecc@amd.com> (raw)
In-Reply-To: <31fdaacc-cc2b-5ea5-8a0e-e5ccfe674834@linux.alibaba.com>
On 6/13/2023 10:19 PM, Shuai Xue wrote:
>
>
> On 2023/6/13 22:11, Yazen Ghannam wrote:
>> Currently, all valid MCA_ADDR values are assumed to be usable on AMD
>> systems. However, this is not correct in most cases. Notifiers expecting
>> usable addresses may then operate on inappropriate values.
>>
>> Define a helper function to do AMD-specific checks for a usable memory
>> address. List out all known cases.
>>
>> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
>> ---
>> arch/x86/kernel/cpu/mce/amd.c | 38 ++++++++++++++++++++++++++++++
>> arch/x86/kernel/cpu/mce/core.c | 3 +++
>> arch/x86/kernel/cpu/mce/internal.h | 2 ++
>> 3 files changed, 43 insertions(+)
>>
>> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
>> index 1ccfb0c9257f..ca79fa10b844 100644
>> --- a/arch/x86/kernel/cpu/mce/amd.c
>> +++ b/arch/x86/kernel/cpu/mce/amd.c
>> @@ -746,6 +746,44 @@ bool amd_mce_is_memory_error(struct mce *m)
>> return legacy_mce_is_memory_error(m);
>> }
>>
>> +/*
>> + * AMD systems do not have an explicit indicator that the value in MCA_ADDR is
>> + * a system physical address. Therefore individual cases need to be detected.
>> + * Future cases and checks will be added as needed.
>> + *
>> + * 1) General case
>> + * a) Assume address is not usable.
>> + * 2) "Poison" errors
>> + * a) Indicated by MCA_STATUS[43]: POISON. Defined for all banks except legacy
>> + * Northbridge (bank 4).
>> + * b) Refers to poison consumption in the Core. Does not include "no action",
>> + * "action optional", or "deferred" error severities.
>> + * c) Will include a usuable address so that immediate action can be taken.
>> + * 3) Northbridge DRAM ECC errors
>> + * a) Reported in legacy bank 4 with XEC 8.
>> + * b) MCA_STATUS[43] is *not* defined as POISON in legacy bank 4. Therefore,
>> + * this bit should not be checked.
> [nit]
>
>> + *
>> + * NOTE: SMCA UMC memory errors fall into case #1.
>
> hi, Yazen
>
> The address for SMCA UMC memory error is not system physical address, it make sense
> to be not usable. But how we deal with the SMCA address? The MCE chain like
> uc_decode_notifier will do a sanity check with mce_usable_address and it will not
> handle SMCA address.
>
Hi Shuai,
That's correct.
There isn't a good solution today. This will be handled in future changes.
Thanks,
Yazen
next prev parent reply other threads:[~2023-06-14 15:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 14:11 [PATCH 0/3] Properly check for usable addresses on AMD Yazen Ghannam
2023-06-13 14:11 ` [PATCH 1/3] x86/MCE/AMD: Split amd_mce_is_memory_error() Yazen Ghannam
2023-06-14 2:06 ` Shuai Xue
2023-06-14 15:06 ` Yazen Ghannam
2023-06-15 2:03 ` Shuai Xue
2023-06-15 15:09 ` Yazen Ghannam
2023-06-13 14:11 ` [PATCH 2/3] x86/mce: Define amd_mce_usable_address() Yazen Ghannam
2023-06-14 2:19 ` Shuai Xue
2023-06-14 15:09 ` Yazen Ghannam [this message]
2023-06-15 2:12 ` Shuai Xue
2023-06-15 15:15 ` Yazen Ghannam
2023-06-16 1:59 ` Shuai Xue
2023-06-16 7:46 ` William Roche
2023-06-13 14:11 ` [PATCH 3/3] x86/mce: Fixup mce_usable_address() Yazen Ghannam
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