From: Shuai Xue <xueshuai@linux.alibaba.com>
To: Yazen Ghannam <yazen.ghannam@amd.com>, linux-edac@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, tony.luck@intel.com,
x86@kernel.org, muralidhara.mk@amd.com,
joao.m.martins@oracle.com, william.roche@oracle.com,
boris.ostrovsky@oracle.com, john.allen@amd.com,
baolin.wang@linux.alibaba.com
Subject: Re: [PATCH 1/3] x86/MCE/AMD: Split amd_mce_is_memory_error()
Date: Thu, 15 Jun 2023 10:03:00 +0800 [thread overview]
Message-ID: <fcb4a4a9-b266-6135-48f1-c00957ca4dc2@linux.alibaba.com> (raw)
In-Reply-To: <cd4fc492-074f-290f-81ac-cb65715c51b0@amd.com>
On 2023/6/14 23:06, Yazen Ghannam wrote:
> On 6/13/2023 10:06 PM, Shuai Xue wrote:
>>
>>
>> On 2023/6/13 22:11, Yazen Ghannam wrote:
>>> Define helper functions for legacy and SMCA systems in order to reuse
>>> individual checks in later changes.
>>>
>>> Describe what each function is checking for, and correct the XEC bitmask
>>> for SMCA.
>>>
>>> No functional change intended.
>>>
>>> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
>>> ---
>>> arch/x86/kernel/cpu/mce/amd.c | 30 +++++++++++++++++++++++++-----
>>> 1 file changed, 25 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
>>> index 5e74610b39e7..1ccfb0c9257f 100644
>>> --- a/arch/x86/kernel/cpu/mce/amd.c
>>> +++ b/arch/x86/kernel/cpu/mce/amd.c
>>> @@ -713,17 +713,37 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
>>> deferred_error_interrupt_enable(c);
>>> }
>>> -bool amd_mce_is_memory_error(struct mce *m)
>>> +/*
>>> + * DRAM ECC errors are reported in the Northbridge (bank 4) with
>>> + * Extended Error Code 8.
>>> + */
>>> +static bool legacy_mce_is_memory_error(struct mce *m)
>>> +{
>>> + return m->bank == 4 && XEC(m->status, 0x1f) == 8;
>>> +}
>>> +
>>> +/*
>>> + * DRAM ECC errors are reported in Unified Memory Controllers with
>>> + * Extended Error Code 0.
>>> + */
>>> +static bool smca_mce_is_memory_error(struct mce *m)
>>> {
>>> enum smca_bank_types bank_type;
>>> - /* ErrCodeExt[20:16] */
>>> - u8 xec = (m->status >> 16) & 0x1f;
>>> +
>>> + if (XEC(m->status, 0x3f))
>>> + return false;
>>> bank_type = smca_get_bank_type(m->extcpu, m->bank);
>>> +
>>> + return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2;
>>> +}
>>> +
>>> +bool amd_mce_is_memory_error(struct mce *m)
>>> +{
>>> if (mce_flags.smca)
>>> - return (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2) && xec == 0x0;
>>> + return smca_mce_is_memory_error(m);
>>> - return m->bank == 4 && xec == 0x8;
>>> + return legacy_mce_is_memory_error(m);
>>> }
>>> static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
>>
>> Hi, Yazen,
>>
>> Which tree are you working on? This patch can not be applied to Linus master ?
>> (commit b6dad5178ceaf23f369c3711062ce1f2afc33644)
>>
>
> Hi Shuai,
>
> I'm using tip/master as the base.
> https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/log/
>
> Sorry, I forgot to mention this in the cover letter.
Ok. This patch itself looks good to me.
Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
Thanks.
Shuai
next prev parent reply other threads:[~2023-06-15 2:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 14:11 [PATCH 0/3] Properly check for usable addresses on AMD Yazen Ghannam
2023-06-13 14:11 ` [PATCH 1/3] x86/MCE/AMD: Split amd_mce_is_memory_error() Yazen Ghannam
2023-06-14 2:06 ` Shuai Xue
2023-06-14 15:06 ` Yazen Ghannam
2023-06-15 2:03 ` Shuai Xue [this message]
2023-06-15 15:09 ` Yazen Ghannam
2023-06-13 14:11 ` [PATCH 2/3] x86/mce: Define amd_mce_usable_address() Yazen Ghannam
2023-06-14 2:19 ` Shuai Xue
2023-06-14 15:09 ` Yazen Ghannam
2023-06-15 2:12 ` Shuai Xue
2023-06-15 15:15 ` Yazen Ghannam
2023-06-16 1:59 ` Shuai Xue
2023-06-16 7:46 ` William Roche
2023-06-13 14:11 ` [PATCH 3/3] x86/mce: Fixup mce_usable_address() Yazen Ghannam
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