* [v4,8/8] EDAC: armada_xp: Add support for more SoCs
@ 2018-01-12 18:47 Borislav Petkov
0 siblings, 0 replies; 2+ messages in thread
From: Borislav Petkov @ 2018-01-12 18:47 UTC (permalink / raw)
To: Chris Packham
Cc: linux, jlu, thomas.petazzoni, kernel, gregory.clement,
Mauro Carvalho Chehab, linux-edac, linux-kernel
On Fri, Jan 12, 2018 at 02:27:55PM +1300, Chris Packham wrote:
> The Armada 38x and other integrated SoCs use a reduced pin count so the
> width of the SDRAM interface is smaller than the Armada XP SoCs. This
> means that the definition of "full" and "half" width is reduced from
> 64/32 to 32/16.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> drivers/edac/armada_xp_edac.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
> index 70cff01afc8d..03a18b54467a 100644
> --- a/drivers/edac/armada_xp_edac.c
> +++ b/drivers/edac/armada_xp_edac.c
> @@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev)
>
> axp_mc_read_config(mci);
>
> + /* These SoCs have a reduced width bus */
> + if (of_machine_is_compatible("marvell,armada380") ||
> + of_machine_is_compatible("marvell,armadaxp-98dx3236"))
> + drvdata->width /= 2;
> +
> /* configure SBE threshold */
> /* it seems that SBEs are not captured otherwise */
> writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
> --
Reviewed-by: Borislav Petkov <bp@suse.de>
^ permalink raw reply [flat|nested] 2+ messages in thread* [v4,8/8] EDAC: armada_xp: Add support for more SoCs
@ 2018-01-12 1:27 Chris Packham
0 siblings, 0 replies; 2+ messages in thread
From: Chris Packham @ 2018-01-12 1:27 UTC (permalink / raw)
To: linux, bp, jlu
Cc: Chris.Packham, thomas.petazzoni, kernel, gregory.clement,
Chris Packham, Mauro Carvalho Chehab, linux-edac, linux-kernel
The Armada 38x and other integrated SoCs use a reduced pin count so the
width of the SDRAM interface is smaller than the Armada XP SoCs. This
means that the definition of "full" and "half" width is reduced from
64/32 to 32/16.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
drivers/edac/armada_xp_edac.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 70cff01afc8d..03a18b54467a 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -341,6 +341,11 @@ static int axp_mc_probe(struct platform_device *pdev)
axp_mc_read_config(mci);
+ /* These SoCs have a reduced width bus */
+ if (of_machine_is_compatible("marvell,armada380") ||
+ of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+ drvdata->width /= 2;
+
/* configure SBE threshold */
/* it seems that SBEs are not captured otherwise */
writel(1 << SDRAM_ERR_CTRL_THR_OFFSET, drvdata->base + SDRAM_ERR_CTRL_REG);
^ permalink raw reply related [flat|nested] 2+ messages in thread
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