From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <x86@kernel.org>, Tony Luck <tony.luck@intel.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>,
<Smita.KoralahalliChannabasappa@amd.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH v2 11/16] x86/mce: Move machine_check_poll() status checks to helper functions
Date: Thu, 13 Feb 2025 16:46:00 +0000 [thread overview]
Message-ID: <20250213-wip-mca-updates-v2-11-3636547fe05f@amd.com> (raw)
In-Reply-To: <20250213-wip-mca-updates-v2-0-3636547fe05f@amd.com>
There are a number of generic and vendor-specific status checks in
machine_check_poll(). These are used to determine if an error should be
skipped.
Move these into helper functions. Future vendor-specific checks will be
added to the helpers.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Notes:
Link:
https://lore.kernel.org/r/20240523155641.2805411-5-yazen.ghannam@amd.com
v1->v2:
* Change log_poll_error() to should_log_poll_error().
* Keep code comment.
arch/x86/kernel/cpu/mce/core.c | 88 +++++++++++++++++++++++-------------------
1 file changed, 48 insertions(+), 40 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 1ea52f6259a4..372e8b078dd5 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -692,6 +692,52 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i)
DEFINE_PER_CPU(unsigned, mce_poll_count);
+/*
+ * Newer Intel systems that support software error
+ * recovery need to make additional checks. Other
+ * CPUs should skip over uncorrected errors, but log
+ * everything else.
+ */
+static bool ser_should_log_poll_error(struct mce *m)
+{
+ /* Log "not enabled" (speculative) errors */
+ if (!(m->status & MCI_STATUS_EN))
+ return true;
+
+ /*
+ * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
+ * UC == 1 && PCC == 0 && S == 0
+ */
+ if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S))
+ return true;
+
+ return false;
+}
+
+static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
+{
+ struct mce *m = &err->m;
+
+ /* If this entry is not valid, ignore it. */
+ if (!(m->status & MCI_STATUS_VAL))
+ return false;
+
+ /*
+ * If we are logging everything (at CPU online) or this
+ * is a corrected error, then we must log it.
+ */
+ if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC))
+ return true;
+
+ if (mca_cfg.ser)
+ return ser_should_log_poll_error(m);
+
+ if (m->status & MCI_STATUS_UC)
+ return false;
+
+ return true;
+}
+
/*
* Poll for corrected events or events that happened before reset.
* Those are just logged through /dev/mcelog.
@@ -743,48 +789,10 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
if (!mca_cfg.cmci_disabled)
mce_track_storm(m);
- /* If this entry is not valid, ignore it */
- if (!(m->status & MCI_STATUS_VAL))
+ /* Verify that the error should be logged based on hardware conditions. */
+ if (!should_log_poll_error(flags, &err))
continue;
- /*
- * If we are logging everything (at CPU online) or this
- * is a corrected error, then we must log it.
- */
- if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC))
- goto log_it;
-
- /*
- * Newer Intel systems that support software error
- * recovery need to make additional checks. Other
- * CPUs should skip over uncorrected errors, but log
- * everything else.
- */
- if (!mca_cfg.ser) {
- if (m->status & MCI_STATUS_UC)
- continue;
- goto log_it;
- }
-
- /* Log "not enabled" (speculative) errors */
- if (!(m->status & MCI_STATUS_EN))
- goto log_it;
-
- /*
- * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
- * UC == 1 && PCC == 0 && S == 0
- */
- if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S))
- goto log_it;
-
- /*
- * Skip anything else. Presumption is that our read of this
- * bank is racing with a machine check. Leave the log alone
- * for do_machine_check() to deal with it.
- */
- continue;
-
-log_it:
mce_read_aux(&err, i);
m->severity = mce_severity(m, NULL, NULL, false);
/*
--
2.43.0
next prev parent reply other threads:[~2025-02-13 16:46 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-13 16:45 [PATCH v2 00/16] AMD MCA interrupts rework Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 01/16] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-02-17 6:58 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 02/16] x86/mce/amd: Remove return value for mce_threshold_create_device() Yazen Ghannam
2025-02-17 7:11 ` Zhuo, Qiuxu
2025-02-17 14:09 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-02-17 7:57 ` Zhuo, Qiuxu
2025-02-17 14:17 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 04/16] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-02-18 1:28 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 05/16] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-02-13 22:32 ` Luck, Tony
2025-02-17 13:55 ` Yazen Ghannam
2025-02-18 16:40 ` Luck, Tony
2025-02-18 2:15 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 06/16] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-02-18 3:00 ` Zhuo, Qiuxu
2025-02-19 15:53 ` Yazen Ghannam
2025-02-27 15:25 ` Borislav Petkov
2025-02-27 16:31 ` Yazen Ghannam
2025-02-27 19:33 ` Borislav Petkov
2025-02-27 19:59 ` Yazen Ghannam
2025-02-27 20:48 ` Borislav Petkov
2025-02-28 14:29 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 07/16] x86/mce: Define BSP-only init Yazen Ghannam
2025-02-18 3:16 ` Zhuo, Qiuxu
2025-02-19 15:57 ` Yazen Ghannam
2025-02-20 1:37 ` Zhuo, Qiuxu
2025-02-20 14:36 ` Yazen Ghannam
2025-02-24 13:28 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-02-18 3:33 ` Zhuo, Qiuxu
2025-02-19 16:01 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 09/16] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-02-18 5:31 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 10/16] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-02-18 6:03 ` Zhuo, Qiuxu
2025-02-19 16:06 ` Yazen Ghannam
2025-02-20 1:27 ` Zhuo, Qiuxu
2025-02-20 14:37 ` Yazen Ghannam
2025-02-13 16:46 ` Yazen Ghannam [this message]
2025-02-18 6:29 ` [PATCH v2 11/16] x86/mce: Move machine_check_poll() status checks to helper functions Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-02-18 6:42 ` Zhuo, Qiuxu
2025-02-19 16:07 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 13/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-02-18 7:37 ` Zhuo, Qiuxu
2025-02-19 16:09 ` Yazen Ghannam
2025-02-20 1:41 ` Zhuo, Qiuxu
2025-02-20 14:41 ` Yazen Ghannam
2025-02-24 13:31 ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 14/16] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-02-18 8:23 ` Zhuo, Qiuxu
2025-02-19 16:16 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 15/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-02-13 22:34 ` Luck, Tony
2025-02-17 14:06 ` Yazen Ghannam
2025-02-18 13:27 ` Zhuo, Qiuxu
2025-02-19 16:19 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-02-18 13:51 ` Zhuo, Qiuxu
2025-02-13 22:40 ` [PATCH v2 00/16] AMD MCA interrupts rework Luck, Tony
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