From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
To: Tony Luck <tony.luck@intel.com>, Borislav Petkov <bp@alien8.de>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>, Yi Lai <yi1.lai@intel.com>,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 6/8] EDAC/skx_common: Add SubChannel support to ADXL decode
Date: Thu, 21 May 2026 15:31:10 +0800 [thread overview]
Message-ID: <20260521073112.3881223-7-qiuxu.zhuo@intel.com> (raw)
In-Reply-To: <20260521073112.3881223-1-qiuxu.zhuo@intel.com>
Diamond Rapids server RRL (Retry Read error Log) operates at sub-channel
granularity. Add SubChannel support to ADXL decoding in preparation for
enabling this feature.
Also introduce adxl_component_required() to validate mandatory ADXL
components to improve code readability.
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
---
drivers/edac/skx_common.c | 20 +++++++++++++++++++-
drivers/edac/skx_common.h | 5 +++++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c
index f769a354ea45..4d832f02fb59 100644
--- a/drivers/edac/skx_common.c
+++ b/drivers/edac/skx_common.c
@@ -31,10 +31,12 @@ static const char * const component_names[] = {
[INDEX_CHANNEL] = "ChannelId",
[INDEX_DIMM] = "DimmSlotId",
[INDEX_CS] = "ChipSelect",
+ [INDEX_SUBCH] = "SubChId",
[INDEX_NM_MEMCTRL] = "NmMemoryControllerId",
[INDEX_NM_CHANNEL] = "NmChannelId",
[INDEX_NM_DIMM] = "NmDimmSlotId",
[INDEX_NM_CS] = "NmChipSelect",
+ [INDEX_NM_SUBCH] = "NmSubChId",
};
static int component_indices[ARRAY_SIZE(component_names)];
@@ -43,6 +45,7 @@ static const char * const *adxl_component_names;
static u64 *adxl_values;
static char *adxl_msg;
static unsigned long adxl_nm_bitmap;
+static unsigned long adxl_bitmap;
static char skx_msg[MSG_SIZE];
static skx_decode_f driver_decode;
@@ -288,6 +291,15 @@ void skx_show_rrl(struct decoded_addr *res, char *msg, int len, bool scrub_err)
}
EXPORT_SYMBOL_GPL(skx_show_rrl);
+static bool adxl_component_required(int idx)
+{
+ return idx == INDEX_SOCKET ||
+ idx == INDEX_MEMCTRL ||
+ idx == INDEX_CHANNEL ||
+ idx == INDEX_DIMM ||
+ idx == INDEX_CS;
+}
+
int skx_adxl_get(void)
{
const char * const *names;
@@ -306,12 +318,14 @@ int skx_adxl_get(void)
if (i >= INDEX_NM_FIRST)
adxl_nm_bitmap |= 1 << i;
+ else
+ adxl_bitmap |= 1 << i;
break;
}
}
- if (!names[j] && i < INDEX_NM_FIRST)
+ if (!names[j] && adxl_component_required(i))
goto err;
}
@@ -438,11 +452,15 @@ static bool skx_adxl_decode(struct decoded_addr *res, enum error_source err_src)
(int)adxl_values[component_indices[INDEX_NM_DIMM]] : -1;
res->cs = (adxl_nm_bitmap & BIT_NM_CS) ?
(int)adxl_values[component_indices[INDEX_NM_CS]] : -1;
+ res->subch = (adxl_nm_bitmap & BIT_NM_SUBCH) ?
+ (int)adxl_values[component_indices[INDEX_NM_SUBCH]] : -1;
} else {
res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
res->cs = (int)adxl_values[component_indices[INDEX_CS]];
+ res->subch = (adxl_bitmap & BIT_SUBCH) ?
+ (int)adxl_values[component_indices[INDEX_SUBCH]] : -1;
}
if (res->imc < 0) {
diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h
index eea2d95cc0ac..38d96bf71fd9 100644
--- a/drivers/edac/skx_common.h
+++ b/drivers/edac/skx_common.h
@@ -210,11 +210,13 @@ enum {
INDEX_CHANNEL,
INDEX_DIMM,
INDEX_CS,
+ INDEX_SUBCH,
INDEX_NM_FIRST,
INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
INDEX_NM_CHANNEL,
INDEX_NM_DIMM,
INDEX_NM_CS,
+ INDEX_NM_SUBCH,
INDEX_MAX
};
@@ -225,10 +227,12 @@ enum error_source {
ERR_SRC_NOT_MEMORY,
};
+#define BIT_SUBCH BIT_ULL(INDEX_SUBCH)
#define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
#define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
#define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
#define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
+#define BIT_NM_SUBCH BIT_ULL(INDEX_NM_SUBCH)
struct decoded_addr {
struct mce *mce;
@@ -242,6 +246,7 @@ struct decoded_addr {
int chanways;
int dimm;
int cs;
+ int subch;
int rank;
int channel_rank;
u64 rank_address;
--
2.43.0
next prev parent reply other threads:[~2026-05-21 7:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-21 7:31 [PATCH 0/8] EDAC: Add RRL support for Intel Diamond Rapids servers Qiuxu Zhuo
2026-05-21 7:31 ` [PATCH 1/8] EDAC/{skx_common,i10nm,imh}: Move MC register access helpers to skx_common Qiuxu Zhuo
2026-06-15 2:26 ` Borislav Petkov
2026-06-16 2:02 ` Zhuo, Qiuxu
2026-05-21 7:31 ` [PATCH 2/8] EDAC/{skx_common,skx,i10nm}: Split skx_set_decode() Qiuxu Zhuo
2026-05-21 7:31 ` [PATCH 3/8] EDAC/{skx_common,i10nm}: Rename rrl_mode to rrl_source_type Qiuxu Zhuo
2026-05-21 7:31 ` [PATCH 4/8] EDAC/{skx_common,i10nm}: Introduce rrl_ctrl_mode Qiuxu Zhuo
2026-05-21 7:31 ` [PATCH 5/8] EDAC/{skx_common,i10nm}: Move RRL handling to common code Qiuxu Zhuo
2026-05-21 7:31 ` Qiuxu Zhuo [this message]
2026-05-21 7:31 ` [PATCH 7/8] EDAC/{skx_common,i10nm}: Prepare RRL for sub-channel granularity Qiuxu Zhuo
2026-05-21 7:31 ` [PATCH 8/8] EDAC/imh: Add RRL support for Intel Diamond Rapids server Qiuxu Zhuo
2026-05-27 16:18 ` [PATCH 0/8] EDAC: Add RRL support for Intel Diamond Rapids servers Luck, Tony
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