* radeonfb 0.1.5 testing
@ 2002-06-04 2:41 Ani Joshi
2002-06-04 16:11 ` benh
2002-06-04 20:24 ` James Simmons
0 siblings, 2 replies; 4+ messages in thread
From: Ani Joshi @ 2002-06-04 2:41 UTC (permalink / raw)
To: linux-fbdev-devel
[-- Attachment #1: Type: TEXT/PLAIN, Size: 175 bytes --]
Hi all,
Attatched is a patch against 2.4.19-pre9 which fixes a host of problems
with radeonfb, for those experiencing problems please test and give
feedback, thanks!
ani
[-- Attachment #2: Type: TEXT/PLAIN, Size: 20226 bytes --]
diff -uNr linux.orig/drivers/video/radeon.h linux/drivers/video/radeon.h
--- linux.orig/drivers/video/radeon.h Mon Feb 25 14:38:07 2002
+++ linux/drivers/video/radeon.h Mon Jun 3 20:00:03 2002
@@ -379,6 +379,7 @@
#define SC_TOP_LEFT 0x16EC
#define SC_BOTTOM_RIGHT 0x16F0
#define SRC_SC_BOTTOM_RIGHT 0x16F4
+#define RB2D_DSTCACHE_MODE 0x3428
#define RB2D_DSTCACHE_CTLSTAT 0x342C
#define LVDS_GEN_CNTL 0x02d0
#define LVDS_PLL_CNTL 0x02d4
diff -uNr linux.orig/drivers/video/radeonfb.c linux/drivers/video/radeonfb.c
--- linux.orig/drivers/video/radeonfb.c Mon Jun 3 21:30:53 2002
+++ linux/drivers/video/radeonfb.c Mon Jun 3 22:07:08 2002
@@ -19,13 +19,15 @@
* 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
* 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
* 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
+ * 2002-06-02 console switching, mode set fixes, accel fixes
+ * 2002-06-03 MTRR support, Peter Horton, 0.1.5
*
* Special thanks to ATI DevRel team for their hardware donations.
*
*/
-#define RADEON_VERSION "0.1.4"
+#define RADEON_VERSION "0.1.5"
#include <linux/config.h>
@@ -70,6 +72,10 @@
#endif /* __powerpc__ */
+#ifdef CONFIG_MTRR
+#include <asm/mtrr.h>
+#endif
+
#include <video/fbcon.h>
#include <video/fbcon-cfb8.h>
#include <video/fbcon-cfb16.h>
@@ -299,8 +305,12 @@
struct ram_info ram;
+ int mtrr_hdl;
+
+#if 0
u32 hack_crtc_ext_cntl;
u32 hack_crtc_v_sync_strt_wid;
+#endif
#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
union {
@@ -507,8 +517,7 @@
SOFT_RESET_RE |
SOFT_RESET_PP |
SOFT_RESET_E2 |
- SOFT_RESET_RB |
- SOFT_RESET_HDP);
+ SOFT_RESET_RB);
INREG(RBBM_SOFT_RESET);
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
~(SOFT_RESET_CP |
@@ -517,8 +526,7 @@
SOFT_RESET_RE |
SOFT_RESET_PP |
SOFT_RESET_E2 |
- SOFT_RESET_RB |
- SOFT_RESET_HDP));
+ SOFT_RESET_RB));
INREG(RBBM_SOFT_RESET);
OUTPLL(MCLK_CNTL, mclk_cntl);
@@ -594,15 +602,24 @@
static char fontname[40] __initdata;
static char *mode_option __initdata;
-static char noaccel __initdata = 0;
+static char noaccel = 0;
static int panel_yres __initdata = 0;
static char force_dfp __initdata = 0;
static struct radeonfb_info *board_list = NULL;
+static char nomtrr __initdata = 0;
#ifdef FBCON_HAS_CFB8
static struct display_switch fbcon_radeon8;
#endif
+#ifdef FBCON_HAS_CFB16
+static struct display_switch fbcon_radeon16;
+#endif
+
+#ifdef FBCON_HAS_CFB32
+static struct display_switch fbcon_radeon32;
+#endif
+
/*
* prototypes
@@ -665,13 +682,15 @@
static struct pmu_sleep_notifier radeon_sleep_notifier = {
radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
};
+#endif /* CONFIG_PMAC_PBOOK */
+#ifdef CONFIG_PMAC_BACKLIGHT
static int radeon_set_backlight_enable(int on, int level, void *data);
static int radeon_set_backlight_level(int level, void *data);
static struct backlight_controller radeon_backlight_controller = {
radeon_set_backlight_enable,
radeon_set_backlight_level
};
-#endif /* CONFIG_PMAC_PBOOK */
+#endif /* CONFIG_PMAC_BACKLIGHT */
#endif /* CONFIG_ALL_PPC */
@@ -731,6 +750,8 @@
force_dfp = 1;
} else if (!strncmp(this_opt, "panel_yres:", 11)) {
panel_yres = simple_strtoul((this_opt+11), NULL, 0);
+ } else if (!strncmp(this_opt, "nomtrr", 6)) {
+ nomtrr = 1;
} else
mode_option = this_opt;
}
@@ -915,6 +936,22 @@
rinfo->bios_seg = radeon_find_rom(rinfo);
radeon_get_pllinfo(rinfo, rinfo->bios_seg);
+ /*
+ * Hack to get around some busted production M6's
+ * reporting no ram
+ */
+ if (rinfo->video_ram == 0) {
+ switch (pdev->device) {
+ case PCI_DEVICE_ID_RADEON_LY:
+ case PCI_DEVICE_ID_RADEON_LZ:
+ rinfo->video_ram = 8192;
+ break;
+ default:
+ break;
+ }
+ }
+
+
RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
#if !defined(__powerpc__)
@@ -960,9 +997,6 @@
return -ENODEV;
}
- /* XXX turn off accel for now, blts aren't working right */
- noaccel = 1;
-
/* currcon not yet configured, will be set by first switch */
rinfo->currcon = -1;
@@ -998,6 +1032,12 @@
return -ENODEV;
}
+#ifdef CONFIG_MTRR
+ rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
+ rinfo->video_ram,
+ MTRR_TYPE_WRCOMB, 1);
+#endif
+
if (!noaccel) {
/* initialize the engine */
radeon_engine_init (rinfo);
@@ -1046,6 +1086,11 @@
/* restore original state */
radeon_write_mode (rinfo, &rinfo->init_state);
+#ifdef CONFIG_MTRR
+ if (rinfo->mtrr_hdl >= 0)
+ mtrr_del(rinfo->mtrr_hdl, 0, 0);
+#endif
+
unregister_framebuffer ((struct fb_info *) rinfo);
iounmap ((void*)rinfo->mmio_base);
@@ -1281,21 +1326,24 @@
#ifdef CONFIG_ALL_PPC
static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
{
- struct device_node *dp;
- unsigned char *pedid = NULL;
-
- dp = pci_device_to_OF_node(rinfo->pdev);
- pedid = (unsigned char *) get_property(dp, "DFP,EDID", 0);
- if (!pedid)
- pedid = (unsigned char *) get_property(dp, "LCD,EDID", 0);
- if (!pedid)
- pedid = (unsigned char *) get_property(dp, "EDID", 0);
-
- if (pedid) {
- rinfo->EDID = pedid;
- return 1;
- } else
- return 0;
+ struct device_node *dp;
+ unsigned char *pedid = NULL;
+ static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
+ int i;
+
+ dp = pci_device_to_OF_node(rinfo->pdev);
+ while (dp != NULL) {
+ for (i = 0; propnames[i] != NULL; ++i) {
+ pedid = (unsigned char *)
+ get_property(dp, propnames[i], NULL);
+ if (pedid != NULL) {
+ rinfo->EDID = pedid;
+ return 1;
+ }
+ }
+ dp = dp->child;
+ }
+ return 0;
}
#endif /* CONFIG_ALL_PPC */
@@ -1540,7 +1588,7 @@
radeon_engine_reset ();
radeon_fifo_wait (1);
- OUTREG(DSTCACHE_MODE, 0);
+ OUTREG(RB2D_DSTCACHE_MODE, 0);
/* XXX */
rinfo->pitch = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6;
@@ -1621,12 +1669,6 @@
disp = &rinfo->disp;
disp->var = radeonfb_default_var;
-#if defined(__powerpc__)
- if (rinfo->dviDisp_type == MT_LCD) {
- if (mac_vmode_to_var(VMODE_1152_768_60, CMODE_8, &disp->var))
- disp->var = radeonfb_default_var;
- }
-#endif
rinfo->depth = var_to_depth(&disp->var);
rinfo->bpp = disp->var.bits_per_pixel;
@@ -1703,14 +1745,14 @@
switch (disp->var.bits_per_pixel) {
#ifdef FBCON_HAS_CFB8
case 8:
- disp->dispsw = &fbcon_cfb8;
+ disp->dispsw = accel ? &fbcon_radeon8 : &fbcon_cfb8;
disp->visual = FB_VISUAL_PSEUDOCOLOR;
disp->line_length = disp->var.xres_virtual;
break;
#endif
#ifdef FBCON_HAS_CFB16
case 16:
- disp->dispsw = &fbcon_cfb16;
+ disp->dispsw = accel ? &fbcon_radeon16 : &fbcon_cfb16;
disp->dispsw_data = &rinfo->con_cmap.cfb16;
disp->visual = FB_VISUAL_DIRECTCOLOR;
disp->line_length = disp->var.xres_virtual * 2;
@@ -1726,7 +1768,7 @@
#endif
#ifdef FBCON_HAS_CFB32
case 32:
- disp->dispsw = &fbcon_cfb32;
+ disp->dispsw = accel ? &fbcon_radeon32 : &fbcon_cfb32;
disp->dispsw_data = &rinfo->con_cmap.cfb32;
disp->visual = FB_VISUAL_DIRECTCOLOR;
disp->line_length = disp->var.xres_virtual * 4;
@@ -1892,12 +1934,11 @@
(disp->var.yres != var->yres) ||
(disp->var.xres_virtual != var->xres_virtual) ||
(disp->var.yres_virtual != var->yres_virtual) ||
- (disp->var.bits_per_pixel != var->bits_per_pixel) ||
- memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
- memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
- memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
+ (disp->var.bits_per_pixel != var->bits_per_pixel));
}
+printk("set_var: chgvar = %d\n", chgvar);
+
memcpy (&v, var, sizeof (v));
switch (v.bits_per_pixel) {
@@ -2020,7 +2061,7 @@
memcpy (&disp->var, &v, sizeof (v));
if (chgvar) {
- radeon_set_dispsw(rinfo, disp);
+ radeon_set_dispsw(rinfo, disp);
if (noaccel)
disp->scrollmode = SCROLL_YREDRAW;
@@ -2030,8 +2071,13 @@
if (info && info->changevar)
info->changevar(con);
}
-
+
radeon_load_video_mode (rinfo, &v);
+
+ if (!noaccel) {
+ /* (re)initialize the engine */
+ radeon_engine_init (rinfo);
+ }
do_install_cmap(con, info);
@@ -2131,8 +2177,15 @@
if (cmap->len)
fb_get_cmap (cmap, 1, radeon_getcolreg, info);
}
-
- switchmode = (con != rinfo->currcon);
+
+ if ((disp->var.xres != rinfo->xres) ||
+ (disp->var.yres != rinfo->yres) ||
+ (disp->var.pixclock != rinfo->pixclock) ||
+ (disp->var.bits_per_pixel != rinfo->bpp))
+ switchmode = 1;
+
+ if(rinfo->currcon == -1)
+ switchmode = 1;
rinfo->currcon = con;
rinfo->currcon_display = disp;
@@ -2140,16 +2193,19 @@
if (switchmode) {
radeonfb_set_var (&disp->var, con, info);
- radeon_set_dispsw (rinfo, disp);
do_install_cmap(con, info);
}
+ radeon_set_dispsw (rinfo, disp);
+
+#if 0
/* XXX absurd hack for X to restore console */
{
OUTREGP(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl,
CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
}
+#endif
return 0;
}
@@ -2493,8 +2549,10 @@
rinfo->bpp = mode->bits_per_pixel;
rinfo->depth = depth;
+#if 0
rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
+#endif
if (freq > rinfo->pll.ppll_max)
freq = rinfo->pll.ppll_max;
@@ -2593,13 +2651,13 @@
newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
if (mode->yres != rinfo->panel_yres) {
- vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
- rinfo->panel_yres);
- newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
- (newmode.fp_vert_stretch &
- (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
- newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
- VERT_STRETCH_ENABLE);
+ vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
+ rinfo->panel_yres);
+ newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
+ (newmode.fp_vert_stretch &
+ (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
+ newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
+ VERT_STRETCH_ENABLE);
}
newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
@@ -2628,14 +2686,19 @@
/* DFP */
newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
- ICHCSEL) & ~(TMDS_PLLRST);
+ ICHCSEL | TMDS_PLL_EN) &
+ ~(TMDS_PLLRST);
newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
}
- newmode.fp_crtc_h_total_disp = newmode.crtc_h_total_disp;
- newmode.fp_crtc_v_total_disp = newmode.crtc_v_total_disp;
- newmode.fp_h_sync_strt_wid = newmode.crtc_h_sync_strt_wid;
- newmode.fp_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
+ newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
+ (((mode->xres / 8) - 1) << 16));
+ newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
+ ((mode->yres - 1) << 16);
+ newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
+ (hsync_wid << 16) | (h_sync_pol << 23));
+ newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
+ (vsync_wid << 16) | (v_sync_pol << 23));
}
/* do it! */
@@ -2656,9 +2719,7 @@
int i;
int primary_mon = PRIMARY_MONITOR(rinfo);
- /* blank screen */
- OUTREGP(CRTC_EXT_CNTL, CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS,
- ~(CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS));
+ radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
for (i=0; i<9; i++)
OUTREG(common_regs[i].reg, common_regs[i].val);
@@ -2742,8 +2803,7 @@
}
}
- /* unblank screen */
- OUTREG8(CRTC_EXT_CNTL + 1, 0);
+ radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
return;
}
@@ -2958,6 +3018,7 @@
{
struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
u32 dp_cntl = DST_LAST_PEL;
+ u32 dp_cntl_save = 0;
srcx *= fontwidth(p);
srcy *= fontheight(p);
@@ -2967,17 +3028,19 @@
height *= fontheight(p);
if (srcy < dsty) {
- srcy += height - 1;
- dsty += height - 1;
+ srcy += height;
+ dsty += height;
} else
dp_cntl |= DST_Y_TOP_TO_BOTTOM;
if (srcx < dstx) {
- srcx += width - 1;
- dstx += width - 1;
+ srcx += width;
+ dstx += width;
} else
dp_cntl |= DST_X_LEFT_TO_RIGHT;
+ dp_cntl_save = INREG(DP_CNTL);
+
radeon_fifo_wait(6);
OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
GMC_BRUSH_NONE |
@@ -2989,11 +3052,37 @@
OUTREG(SRC_Y_X, (srcy << 16) | srcx);
OUTREG(DST_Y_X, (dsty << 16) | dstx);
OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
+
+ radeon_fifo_wait(1);
+ OUTREG(DP_CNTL, dp_cntl_save);
+
+ radeon_engine_idle();
+}
+
+
+
+static void radeon_rectfill(struct radeonfb_info *rinfo,
+ int dsty, int dstx,
+ int height, int width,
+ u32 clr)
+{
+ radeon_fifo_wait(6);
+ OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
+ GMC_BRUSH_SOLID_COLOR |
+ GMC_SRC_DATATYPE_COLOR |
+ ROP3_P));
+ OUTREG(DP_BRUSH_FRGD_CLR, clr);
+ OUTREG(DP_WRITE_MSK, 0xffffffff);
+ OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
+ OUTREG(DST_Y_X, (dsty << 16) | dstx);
+ OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
}
-static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
+#ifdef FBCON_HAS_CFB8
+
+static void fbcon_radeon8_clear(struct vc_data *conp, struct display *p,
int srcy, int srcx, int height, int width)
{
struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
@@ -3008,25 +3097,15 @@
width *= fontwidth(p);
height *= fontheight(p);
- radeon_fifo_wait(6);
- OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
- GMC_BRUSH_SOLID_COLOR |
- GMC_SRC_DATATYPE_COLOR |
- ROP3_P));
- OUTREG(DP_BRUSH_FRGD_CLR, clr);
- OUTREG(DP_WRITE_MSK, 0xffffffff);
- OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
- OUTREG(DST_Y_X, (srcy << 16) | srcx);
- OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
+ radeon_rectfill(rinfo, srcy, srcx, height, width, clr);
}
-#ifdef FBCON_HAS_CFB8
static struct display_switch fbcon_radeon8 = {
setup: fbcon_cfb8_setup,
bmove: fbcon_radeon_bmove,
- clear: fbcon_radeon_clear,
+ clear: fbcon_radeon8_clear,
putc: fbcon_cfb8_putc,
putcs: fbcon_cfb8_putcs,
revc: fbcon_cfb8_revc,
@@ -3034,3 +3113,71 @@
fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
};
#endif
+
+#ifdef FBCON_HAS_CFB16
+
+
+static void fbcon_radeon16_clear(struct vc_data *conp, struct display *p,
+ int srcy, int srcx, int height, int width)
+{
+ struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
+ u32 clr;
+
+ clr = ((u16 *)p->dispsw_data)[attr_bgcol_ec(p, conp)];
+ clr |= (clr << 16);
+
+ srcx *= fontwidth(p);
+ srcy *= fontheight(p);
+ width *= fontwidth(p);
+ height *= fontheight(p);
+
+ radeon_rectfill(rinfo, srcy, srcx, height, width, clr);
+}
+
+
+
+static struct display_switch fbcon_radeon16 = {
+ setup: fbcon_cfb16_setup,
+ bmove: fbcon_radeon_bmove,
+ clear: fbcon_radeon16_clear,
+ putc: fbcon_cfb16_putc,
+ putcs: fbcon_cfb16_putcs,
+ revc: fbcon_cfb16_revc,
+ clear_margins: fbcon_cfb16_clear_margins,
+ fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
+};
+#endif
+
+#ifdef FBCON_HAS_CFB32
+
+
+static void fbcon_radeon32_clear(struct vc_data *conp, struct display *p,
+ int srcy, int srcx, int height, int width)
+{
+ struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
+ u32 clr;
+
+ clr = ((u32 *)p->dispsw_data)[attr_bgcol_ec(p, conp)];
+
+ srcx *= fontwidth(p);
+ srcy *= fontheight(p);
+ width *= fontwidth(p);
+ height *= fontheight(p);
+
+ radeon_rectfill(rinfo, srcy, srcx, height, width, clr);
+}
+
+
+
+static struct display_switch fbcon_radeon32 = {
+ setup: fbcon_cfb32_setup,
+ bmove: fbcon_radeon_bmove,
+ clear: fbcon_radeon32_clear,
+ putc: fbcon_cfb32_putc,
+ putcs: fbcon_cfb32_putcs,
+ revc: fbcon_cfb32_revc,
+ clear_margins: fbcon_cfb32_clear_margins,
+ fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
+};
+#endif
+
diff -uNr linux.orig/drivers/video/riva/fbdev.c linux/drivers/video/riva/fbdev.c
--- linux.orig/drivers/video/riva/fbdev.c Mon Jun 3 21:30:53 2002
+++ linux/drivers/video/riva/fbdev.c Mon Jun 3 18:07:17 2002
@@ -1912,6 +1912,26 @@
rinfo->riva.IO = (MISCin(rinfo) & 0x01) ? 0x3D0 : 0x3B0;
+ if(rinfo->riva.Architecture == NV_ARCH_03) {
+ /*
+ * We have to map the full BASE_1 aperture for Riva128's
+ * because they use the PRAMIN set in "framebuffer" space
+ */
+ if (!request_mem_region(rinfo->fb_base_phys,
+ rinfo->base1_region_size, "rivafb")) {
+ printk(KERN_ERR PFX "cannot reserve FB region\n");
+ goto err_out_free_base0;
+ }
+
+ rinfo->fb_base = ioremap(rinfo->fb_base_phys,
+ rinfo->base1_region_size);
+
+ if (!rinfo->fb_base) {
+ printk(KERN_ERR PFX "cannot ioremap FB base\n");
+ goto err_out_iounmap_ctrl;
+ }
+ }
+
switch (rinfo->riva.Architecture) {
case NV_ARCH_03:
rinfo->riva.PRAMIN = (unsigned *)(rinfo->fb_base + 0x00C00000);
@@ -1929,17 +1949,23 @@
rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024;
rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000;
- if (!request_mem_region(rinfo->fb_base_phys,
- rinfo->ram_amount, "rivafb")) {
- printk(KERN_ERR PFX "cannot reserve FB region\n");
- goto err_out_free_base0;
- }
+ if (rinfo->riva.Architecture != NV_ARCH_03) {
+ /*
+ * Now the _normal_ chipsets can just map the amount of
+ * real physical ram instead of the whole aperture
+ */
+ if (!request_mem_region(rinfo->fb_base_phys,
+ rinfo->ram_amount, "rivafb")) {
+ printk(KERN_ERR PFX "cannot reserve FB region\n");
+ goto err_out_free_base0;
+ }
- rinfo->fb_base = ioremap(rinfo->fb_base_phys,
+ rinfo->fb_base = ioremap(rinfo->fb_base_phys,
rinfo->ram_amount);
- if (!rinfo->fb_base) {
- printk(KERN_ERR PFX "cannot ioremap FB base\n");
- goto err_out_iounmap_ctrl;
+ if (!rinfo->fb_base) {
+ printk(KERN_ERR PFX "cannot ioremap FB base\n");
+ goto err_out_iounmap_ctrl;
+ }
}
#ifdef CONFIG_MTRR
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: radeonfb 0.1.5 testing
2002-06-04 2:41 radeonfb 0.1.5 testing Ani Joshi
@ 2002-06-04 16:11 ` benh
2002-06-04 19:11 ` Ani Joshi
2002-06-04 20:24 ` James Simmons
1 sibling, 1 reply; 4+ messages in thread
From: benh @ 2002-06-04 16:11 UTC (permalink / raw)
To: Ani Joshi, linux-fbdev-devel
>Attatched is a patch against 2.4.19-pre9 which fixes a host of problems
>with radeonfb, for those experiencing problems please test and give
>feedback, thanks!
You included rivafb diffs as well ;)
Ben.
_______________________________________________________________
Don't miss the 2002 Sprint PCS Application Developer's Conference
August 25-28 in Las Vegas -- http://devcon.sprintpcs.com/adp/index.cfm
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: radeonfb 0.1.5 testing
2002-06-04 16:11 ` benh
@ 2002-06-04 19:11 ` Ani Joshi
0 siblings, 0 replies; 4+ messages in thread
From: Ani Joshi @ 2002-06-04 19:11 UTC (permalink / raw)
To: benh; +Cc: linux-fbdev-devel
Oops, well test those too! The rivafb hunks unbreak Riva128 support.
ani
On Tue, 4 Jun 2002 benh@kernel.crashing.org wrote:
> >Attatched is a patch against 2.4.19-pre9 which fixes a host of problems
> >with radeonfb, for those experiencing problems please test and give
> >feedback, thanks!
>
> You included rivafb diffs as well ;)
>
> Ben.
>
>
>
_______________________________________________________________
Don't miss the 2002 Sprint PCS Application Developer's Conference
August 25-28 in Las Vegas -- http://devcon.sprintpcs.com/adp/index.cfm
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: radeonfb 0.1.5 testing
2002-06-04 2:41 radeonfb 0.1.5 testing Ani Joshi
2002-06-04 16:11 ` benh
@ 2002-06-04 20:24 ` James Simmons
1 sibling, 0 replies; 4+ messages in thread
From: James Simmons @ 2002-06-04 20:24 UTC (permalink / raw)
To: Ani Joshi; +Cc: linux-fbdev-devel
BTW are the pieces of extra code in the DJ tree valid for the Riva
fbdev driver?
P.S
I plan to port that driver over to the new api code soon. I have a
Nvidia card here at work.
. ---
|o_o |
|:_/ | Give Micro$oft the Bird!!!!
// \ \ Use Linux!!!!
(| | )
/'\_ _/`\
\___)=(___/
On Mon, 3 Jun 2002, Ani Joshi wrote:
>
> Hi all,
>
> Attatched is a patch against 2.4.19-pre9 which fixes a host of problems
> with radeonfb, for those experiencing problems please test and give
> feedback, thanks!
>
>
>
> ani
>
_______________________________________________________________
Don't miss the 2002 Sprint PCS Application Developer's Conference
August 25-28 in Las Vegas -- http://devcon.sprintpcs.com/adp/index.cfm
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2002-06-04 20:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2002-06-04 2:41 radeonfb 0.1.5 testing Ani Joshi
2002-06-04 16:11 ` benh
2002-06-04 19:11 ` Ani Joshi
2002-06-04 20:24 ` James Simmons
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