[PATCH v2 00/10] Add basic support for Rockchip RK1108 SOC

[PATCH v2 00/10] Add basic support for Rockchip RK1108 SOC

[Andy Yan]

RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch series add basic support for it, which can boot a board with
initramfs into shell.
More new feathers will come soon.

Changes in v2:
- split dt-binding header from clk driver
- fix some CodingStyle issues
- add dt-binding documentation for pinctrl
- add pull and drive-strength functionality for pinctrl
- fix timer and gic dt description
- ordering devices by register address
- move the board in the rockchip.txt to the block of Rockchip boards

Andy Yan (6):
  dt-bindings: add documentation for rk1108 pinctrl
  pinctrl: rockchip: add support for rk1108
  ARM: add low level debug uart for rk1108
  ARM: dts: add basic support for Rockchip RK1108 SOC
  ARM: rockchip: enable support for RK1108 SoC
  ARM: dts: rockchip: add rockchip RK1108 Evaluation board

Shawn Lin (4):
  dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description
  dt-bindings: add documentation for rk1108 cru
  clk: rockchip: add dt-binding header for rk1108
  clk: rockchip: add clock controller for rk1108

 Documentation/devicetree/bindings/arm/rockchip.txt |   5 +-
 .../bindings/clock/rockchip,rk1108-cru.txt         |  60 +++
 .../devicetree/bindings/mmc/rockchip-dw-mshc.txt   |   1 +
 .../bindings/pinctrl/rockchip,pinctrl.txt          |   9 +-
 arch/arm/Kconfig.debug                             |  30 ++
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/rk1108-evb.dts                   |  69 ++++
 arch/arm/boot/dts/rk1108.dtsi                      | 428 +++++++++++++++++++
 arch/arm/mach-rockchip/rockchip.c                  |   1 +
 drivers/clk/rockchip/Makefile                      |   1 +
 drivers/clk/rockchip/clk-rk1108.c                  | 451 +++++++++++++++++++++
 drivers/clk/rockchip/clk.h                         |  14 +
 drivers/pinctrl/pinctrl-rockchip.c                 |  87 +++-
 include/dt-bindings/clock/rk1108-cru.h             | 270 ++++++++++++
 14 files changed, 1421 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt
 create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
 create mode 100644 arch/arm/boot/dts/rk1108.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rk1108.c
 create mode 100644 include/dt-bindings/clock/rk1108-cru.h

-- 
2.7.4

[PATCH v2 05/10] dt-bindings: add documentation for rk1108 pinctrl

[Andy Yan]

This adds the dt-binding documentation for rk1108 pinctrl

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

---

Changes in v2:
- add dt-binding documentation for pinctrl

 Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index c68b955..4722bc6 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -19,10 +19,11 @@ The pins are grouped into up to 5 individual pin banks which need to be
 defined as gpio sub-nodes of the pinmux controller.
 
 Required properties for iomux controller:
-  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
-		       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
-		       "rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
-		       "rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl"
+  - compatible: one of "rockchip,rk1108-pinctrl", "rockchip,rk2928-pinctrl"
+		       "rockchip,rk3066a-pinctrl", "rockchip,rk3066b-pinctrl"
+		       "rockchip,rk3188-pinctrl", "rockchip,rk3228-pinctrl"
+		       "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
+		       "rockchip,rk3399-pinctrl"
   - rockchip,grf: phandle referencing a syscon providing the
 	 "general register files"
 
-- 
2.7.4

[PATCH v2 06/10] pinctrl: rockchip: add support for rk1108

[Andy Yan]

This add pinctrl support for Rockchip RK1108 Soc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

---

Changes in v2:
- add pull and drive-strength functionality

 drivers/pinctrl/pinctrl-rockchip.c | 87 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 86 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 49bf7dc..fcc89fb 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -59,6 +59,7 @@
 #define GPIO_LS_SYNC		0x60
 
 enum rockchip_pinctrl_type {
+	RK1108,
 	RK2928,
 	RK3066B,
 	RK3188,
@@ -624,6 +625,65 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 	return ret;
 }
 
+#define RK1108_PULL_PMU_OFFSET		0x10
+#define RK1108_PULL_OFFSET		0x110
+#define RK1108_PULL_PINS_PER_REG	8
+#define RK1108_PULL_BITS_PER_PIN	2
+#define RK1108_PULL_BANK_STRIDE		16
+
+static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+					 int pin_num, struct regmap **regmap,
+					 int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+
+	/* The first 24 pins of the first bank are located in PMU */
+	if (bank->bank_num == 0) {
+		*regmap = info->regmap_pmu;
+		*reg = RK1108_PULL_PMU_OFFSET;
+	} else {
+		*reg = RK1108_PULL_OFFSET;
+		*regmap = info->regmap_base;
+		/* correct the offset, as we're starting with the 2nd bank */
+		*reg -= 0x10;
+		*reg += bank->bank_num * RK1108_PULL_BANK_STRIDE;
+	}
+
+	*reg += ((pin_num / RK1108_PULL_PINS_PER_REG) * 4);
+	*bit = (pin_num % RK1108_PULL_PINS_PER_REG);
+	*bit *= RK1108_PULL_BITS_PER_PIN;
+}
+
+#define RK1108_DRV_PMU_OFFSET           0x20
+#define RK1108_DRV_GRF_OFFSET           0x210
+#define RK1108_DRV_BITS_PER_PIN         2
+#define RK1108_DRV_PINS_PER_REG         8
+#define RK1108_DRV_BANK_STRIDE          16
+
+static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+					int pin_num, struct regmap **regmap,
+					int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+
+	/* The first 24 pins of the first bank are located in PMU */
+	if (bank->bank_num == 0) {
+		*regmap = info->regmap_pmu;
+		*reg = RK1108_DRV_PMU_OFFSET;
+	} else {
+		*regmap = info->regmap_base;
+		*reg = RK1108_DRV_GRF_OFFSET;
+
+		/* correct the offset, as we're starting with the 2nd bank */
+		*reg -= 0x10;
+		*reg += bank->bank_num * RK1108_DRV_BANK_STRIDE;
+	}
+
+	*reg += ((pin_num / RK1108_DRV_PINS_PER_REG) * 4);
+	*bit = pin_num % RK1108_DRV_PINS_PER_REG;
+	*bit *= RK1108_DRV_BITS_PER_PIN;
+}
+
 #define RK2928_PULL_OFFSET		0x118
 #define RK2928_PULL_PINS_PER_REG	16
 #define RK2928_PULL_BANK_STRIDE		8
@@ -1123,6 +1183,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 		return !(data & BIT(bit))
 				? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 				: PIN_CONFIG_BIAS_DISABLE;
+	case RK1108:
 	case RK3188:
 	case RK3288:
 	case RK3368:
@@ -1169,6 +1230,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 
 		spin_unlock_irqrestore(&bank->slock, flags);
 		break;
+	case RK1108:
 	case RK3188:
 	case RK3288:
 	case RK3368:
@@ -1358,6 +1420,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 					pull == PIN_CONFIG_BIAS_DISABLE);
 	case RK3066B:
 		return pull ? false : true;
+	case RK1108:
 	case RK3188:
 	case RK3288:
 	case RK3368:
@@ -1385,7 +1448,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 	for (i = 0; i < num_configs; i++) {
 		param = pinconf_to_config_param(configs[i]);
 		arg = pinconf_to_config_argument(configs[i]);
-
 		switch (param) {
 		case PIN_CONFIG_BIAS_DISABLE:
 			rc =  rockchip_set_pull(bank, pin - bank->pin_base,
@@ -2455,6 +2517,27 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static struct rockchip_pin_bank rk1108_pin_banks[] = {
+	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU,
+					     IOMUX_SOURCE_PMU),
+	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
+	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
+};
+
+static struct rockchip_pin_ctrl rk1108_pin_ctrl = {
+	.pin_banks		= rk1108_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk1108_pin_banks),
+	.label			= "RK1108-GPIO",
+	.type			= RK1108,
+	.grf_mux_offset		= 0x10,
+	.pmu_mux_offset		= 0x0,
+	.pull_calc_reg		= rk1108_calc_pull_reg_and_bit,
+	.drv_calc_reg		= rk1108_calc_drv_reg_and_bit,
+};
+
 static struct rockchip_pin_bank rk2928_pin_banks[] = {
 	PIN_BANK(0, 32, "gpio0"),
 	PIN_BANK(1, 32, "gpio1"),
@@ -2684,6 +2767,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
 };
 
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
+	{ .compatible = "rockchip,rk1108-pinctrl",
+		.data = (void *)&rk1108_pin_ctrl },
 	{ .compatible = "rockchip,rk2928-pinctrl",
 		.data = (void *)&rk2928_pin_ctrl },
 	{ .compatible = "rockchip,rk3036-pinctrl",
-- 
2.7.4

Re: [PATCH v2 05/10] dt-bindings: add documentation for rk1108 pinctrl

[Heiko Stuebner]

Am Montag, 14. November 2016, 20:09:53 CET schrieb Andy Yan:
> This adds the dt-binding documentation for rk1108 pinctrl
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

pretty straight forward
Reviewed-by: Heiko Stuebner <heiko@sntech.de>

I guess at some later point we should move the compatible list to one 
compatible per line, similar to what the mshc mmc does, because as we're 
seeing right now, soc numbering is not incremental :-) .


Heiko

Re: [PATCH v2 06/10] pinctrl: rockchip: add support for rk1108

[Heiko Stuebner]

Am Montag, 14. November 2016, 20:10:47 CET schrieb Andy Yan:
> This add pinctrl support for Rockchip RK1108 Soc.
> 
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

still looks mostly good. I think I've now compared every register offset with 
the TRM - they all look good. I've noticed two styling issues below, with 
those fixed:

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
> Changes in v2:
> - add pull and drive-strength functionality
> 
>  drivers/pinctrl/pinctrl-rockchip.c | 87
> +++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1
> deletion(-)
> 
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> b/drivers/pinctrl/pinctrl-rockchip.c index 49bf7dc..fcc89fb 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -59,6 +59,7 @@
>  #define GPIO_LS_SYNC		0x60
> 
>  enum rockchip_pinctrl_type {
> +	RK1108,
>  	RK2928,
>  	RK3066B,
>  	RK3188,
> @@ -624,6 +625,65 @@ static int rockchip_set_mux(struct rockchip_pin_bank
> *bank, int pin, int mux) return ret;
>  }
> 
> +#define RK1108_PULL_PMU_OFFSET		0x10
> +#define RK1108_PULL_OFFSET		0x110
> +#define RK1108_PULL_PINS_PER_REG	8
> +#define RK1108_PULL_BITS_PER_PIN	2
> +#define RK1108_PULL_BANK_STRIDE		16
> +
> +static void rk1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> +					 int pin_num, struct regmap **regmap,
> +					 int *reg, u8 *bit)
> +{
> +	struct rockchip_pinctrl *info = bank->drvdata;
> +
> +	/* The first 24 pins of the first bank are located in PMU */
> +	if (bank->bank_num == 0) {
> +		*regmap = info->regmap_pmu;
> +		*reg = RK1108_PULL_PMU_OFFSET;
> +	} else {
> +		*reg = RK1108_PULL_OFFSET;
> +		*regmap = info->regmap_base;
> +		/* correct the offset, as we're starting with the 2nd bank */
> +		*reg -= 0x10;
> +		*reg += bank->bank_num * RK1108_PULL_BANK_STRIDE;
> +	}
> +
> +	*reg += ((pin_num / RK1108_PULL_PINS_PER_REG) * 4);
> +	*bit = (pin_num % RK1108_PULL_PINS_PER_REG);
> +	*bit *= RK1108_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK1108_DRV_PMU_OFFSET           0x20
> +#define RK1108_DRV_GRF_OFFSET           0x210
> +#define RK1108_DRV_BITS_PER_PIN         2
> +#define RK1108_DRV_PINS_PER_REG         8
> +#define RK1108_DRV_BANK_STRIDE          16

styling nitpick, spaces instead of tabs between name and value. The pull 
constants are correct though and only the drv constants need a fixup.

> +
> +static void rk1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> +					int pin_num, struct regmap **regmap,
> +					int *reg, u8 *bit)
> +{
> +	struct rockchip_pinctrl *info = bank->drvdata;
> +
> +	/* The first 24 pins of the first bank are located in PMU */
> +	if (bank->bank_num == 0) {
> +		*regmap = info->regmap_pmu;
> +		*reg = RK1108_DRV_PMU_OFFSET;
> +	} else {
> +		*regmap = info->regmap_base;
> +		*reg = RK1108_DRV_GRF_OFFSET;
> +
> +		/* correct the offset, as we're starting with the 2nd bank */
> +		*reg -= 0x10;
> +		*reg += bank->bank_num * RK1108_DRV_BANK_STRIDE;
> +	}
> +
> +	*reg += ((pin_num / RK1108_DRV_PINS_PER_REG) * 4);
> +	*bit = pin_num % RK1108_DRV_PINS_PER_REG;
> +	*bit *= RK1108_DRV_BITS_PER_PIN;
> +}
> +
>  #define RK2928_PULL_OFFSET		0x118
>  #define RK2928_PULL_PINS_PER_REG	16
>  #define RK2928_PULL_BANK_STRIDE		8

[...]

> @@ -1385,7 +1448,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev
> *pctldev, unsigned int pin, for (i = 0; i < num_configs; i++) {
>  		param = pinconf_to_config_param(configs[i]);
>  		arg = pinconf_to_config_argument(configs[i]);
> -

unrelated change that should be removed.

>  		switch (param) {
>  		case PIN_CONFIG_BIAS_DISABLE:
>  			rc =  rockchip_set_pull(bank, pin - bank->pin_base,

Re: [PATCH v2 05/10] dt-bindings: add documentation for rk1108 pinctrl

[Linus Walleij]

On Mon, Nov 14, 2016 at 1:09 PM, Andy Yan <andy.yan@rock-chips.com> wrote:

> This adds the dt-binding documentation for rk1108 pinctrl
>
> Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

Patch applied with Heiko's review tag.

Yours,
Linus Walleij

Re: [PATCH v2 06/10] pinctrl: rockchip: add support for rk1108

[Linus Walleij]

On Mon, Nov 14, 2016 at 1:10 PM, Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:

> This add pinctrl support for Rockchip RK1108 Soc.
>
> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Please repost with the minor fixes from Heiko and
add his reviewed-by tag and I will apply it.

Yours,
Linus Walleij