From: Andrew Jeffery <andrew@aj.id.au>
To: Joel Stanley <joel@jms.id.au>, Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
OpenBMC Maillist <openbmc@lists.ozlabs.org>
Subject: Re: [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux state
Date: Thu, 29 Sep 2016 17:24:59 +0930 [thread overview]
Message-ID: <1475135699.24463.21.camel@aj.id.au> (raw)
In-Reply-To: <CACPK8Xc7y3GtcJCVYYs-JKTqBZvqVeZaz5MUk=UX151SX1xEFw@mail.gmail.com>
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On Thu, 2016-09-29 at 16:15 +0930, Joel Stanley wrote:
> On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > The System Control Unit IP in the Aspeed SoCs is typically where the
> > pinmux configuration is found.
> >
> > But not always.
> >
> > On the AST2400 and AST2500 a number of pins depend on state in one of
> > the SIO, LPC or GFX IP blocks, so add support to at least capture what
> > that state is. The pinctrl engine for the Aspeed SoCs doesn't try to
> > inspect or modify the state of the off-SCU IP blocks. Instead, it logs
> > the state requirement with the expectation that the platform
> > designer/maintainer arranges for the appropriate configuration to be
> > applied through the associated drivers.
> This is unfortunate.
>
> This patch kicks the can down the road, but doesn't solve the problem
> for a user who wants to configure some functionality that depends on
> the non-SCU bits. Because of this I'm not sure if we want to put it in
> the tree.
I agree that there's not much functionality from a user's perspective,
but the "kicking the can down the road" assessment might be a little
harsh. Given the lack of user functionality it becomes more difficult
to argue for the patch's inclusion given the additional complexity, but
it does mean that the g4/g5 drivers can completely specify their
dependencies and not have the aspeed pinctrl core do the wrong thing
when it encounters the non-SCU IP offsets. It gets us half-way to
having the pinctrl driver actually configure the state (knowing what it
needs to configure), which I feel is more than a kick-the-can-down-the-
road boondoggle.
>
> However, I'm not sure what a proper solution would look like.
So if we accept that a proper solution includes specifying the off-SCU
dependencies, the remaining question is how do we tastefully apply the
desired state on register-spaces the pinctrl driver doesn't own.
> Perhaps
> Linus can point out another SoC that has a similar problem?
Or failing that, an approach that is acceptable...
Cheers,
Andrew
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next prev parent reply other threads:[~2016-09-29 7:54 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-27 14:50 [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins Andrew Jeffery
[not found] ` <cover.115463f791b69859c5ce9dafd61a5755ea039f4b.1474986045.git-series.andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-09-27 14:50 ` [PATCH 1/8] pinctrl: aspeed: "Not enabled" is a significant mux state Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 7:55 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 4/8] pinctrl: aspeed-g5: Fix pin association of SPI1 function Andrew Jeffery
[not found] ` <bdd34f8c4bfabbc1d3cd05a66ac8734da514b1e5.1474986045.git-series.andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-09-29 0:54 ` Joel Stanley
2016-10-03 18:57 ` Rob Herring
2016-10-10 7:59 ` Linus Walleij
2016-10-10 7:59 ` [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins Linus Walleij
2016-10-10 23:27 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 2/8] pinctrl: aspeed-g5: Fix names of GPID2 pins Andrew Jeffery
[not found] ` <69eda17c16684f4212a9f3e64d9587abfcc7ae74.1474986045.git-series.andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-09-29 0:54 ` Joel Stanley
2016-10-10 7:56 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 3/8] pinctrl: aspeed-g5: Fix GPIOE1 typo Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 7:57 ` Linus Walleij
2016-09-27 14:50 ` [PATCH 5/8] pinctrl: aspeed: Enable capture of off-SCU pinmux state Andrew Jeffery
[not found] ` <a266046d34009e6e92c4c76699c550c2ba44bd5c.1474986045.git-series.andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-09-29 6:45 ` Joel Stanley
2016-09-29 7:54 ` Andrew Jeffery [this message]
2016-10-23 22:20 ` Linus Walleij
2016-10-24 0:29 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 6/8] pinctrl: aspeed-g4: Capture SuperIO pinmux dependency Andrew Jeffery
[not found] ` <b5f67ba76018314d08e240f95951751896687d37.1474986045.git-series.andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-10-20 11:53 ` Linus Walleij
2016-10-21 0:33 ` Andrew Jeffery
[not found] ` <1477010011.8917.20.camel-zrmu5oMJ5Fs@public.gmane.org>
2016-10-23 22:09 ` Linus Walleij
[not found] ` <CACRpkdYZPcjGuRKVL6qwof1p7ZXT4EvwzAuz59oTgp9Z5Dzixw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-10-24 0:30 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
[not found] ` <e0d8fa6cd444972e6f048f98da98f0439e6ca39b.1474986045.git-series.andrew-zrmu5oMJ5Fs@public.gmane.org>
2016-10-03 19:08 ` Rob Herring
2016-10-04 1:02 ` Andrew Jeffery
2016-09-27 14:50 ` [PATCH 8/8] pinctrl: aspeed-g5: " Andrew Jeffery
2016-09-29 0:54 ` Joel Stanley
2016-10-10 0:53 ` Rob Herring
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