[PATCH v1 0/2] polarfire gpio driver follow-ups

[PATCH v1 0/2] polarfire gpio driver follow-ups

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Yo,

I realised last week, while rebasing the interrupt portion of the
driver, that coregpio a compatible in the kernel as well as a dts user.
Given how long the driver has taken to even get partially accepted, I
waited to get it to gpio/for-next rather than showing up with last
minute additions to it.

Cheers,
Conor.

CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Bartosz Golaszewski <brgl@bgdev.pl>
CC: linux-kernel@vger.kernel.org
CC: linux-gpio@vger.kernel.org

Conor Dooley (2):
  gpio: mpfs: add CoreGPIO support
  MAINTAINERS: add gpio driver to PolarFire entry

 MAINTAINERS              |  1 +
 drivers/gpio/gpio-mpfs.c | 38 +++++++++++++++++++++++++++++++++-----
 2 files changed, 34 insertions(+), 5 deletions(-)

-- 
2.45.2

[PATCH v1 1/2] gpio: mpfs: add CoreGPIO support

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

coreGPIO, which the "hard" core in PolarFire SoC is based on, has
different offsets for inp/outp. Add some match_data handling to account
for the differences.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 drivers/gpio/gpio-mpfs.c | 38 +++++++++++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/gpio/gpio-mpfs.c b/drivers/gpio/gpio-mpfs.c
index 3718121eb97a..4aefae05a9fb 100644
--- a/drivers/gpio/gpio-mpfs.c
+++ b/drivers/gpio/gpio-mpfs.c
@@ -10,6 +10,7 @@
 #include <linux/errno.h>
 #include <linux/gpio/driver.h>
 #include <linux/init.h>
+#include <linux/of_device.h>
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
@@ -30,11 +31,20 @@
 #define MPFS_GPIO_TYPE_INT_LEVEL_HIGH	0x00
 #define MPFS_GPIO_TYPE_INT_MASK		GENMASK(7, 5)
 #define MPFS_IRQ_REG			0x80
+
 #define MPFS_INP_REG			0x84
+#define COREGPIO_INP_REG		0x90
 #define MPFS_OUTP_REG			0x88
+#define COREGPIO_OUTP_REG		0xA0
+
+struct mpfs_gpio_reg_offsets {
+	u8 inp;
+	u8 outp;
+};
 
 struct mpfs_gpio_chip {
 	struct regmap *regs;
+	const struct mpfs_gpio_reg_offsets *offsets;
 	struct gpio_chip gc;
 };
 
@@ -60,7 +70,7 @@ static int mpfs_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio_in
 
 	regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index),
 			   MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_IN);
-	regmap_update_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index),
+	regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index),
 			   value << gpio_index);
 
 	return 0;
@@ -84,9 +94,9 @@ static int mpfs_gpio_get(struct gpio_chip *gc, unsigned int gpio_index)
 	struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
 
 	if (mpfs_gpio_get_direction(gc, gpio_index) == GPIO_LINE_DIRECTION_OUT)
-		return regmap_test_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index));
+		return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index));
 	else
-		return regmap_test_bits(mpfs_gpio->regs, MPFS_INP_REG, BIT(gpio_index));
+		return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->inp, BIT(gpio_index));
 }
 
 static void mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value)
@@ -95,7 +105,7 @@ static void mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int val
 
 	mpfs_gpio_get(gc, gpio_index);
 
-	regmap_update_bits(mpfs_gpio->regs, MPFS_OUTP_REG, BIT(gpio_index),
+	regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index),
 			   value << gpio_index);
 
 	mpfs_gpio_get(gc, gpio_index);
@@ -113,6 +123,8 @@ static int mpfs_gpio_probe(struct platform_device *pdev)
 	if (!mpfs_gpio)
 		return -ENOMEM;
 
+	mpfs_gpio->offsets = of_device_get_match_data(&pdev->dev);
+
 	base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(base))
 		return dev_err_probe(dev, PTR_ERR(base), "failed to ioremap memory resource\n");
@@ -145,8 +157,24 @@ static int mpfs_gpio_probe(struct platform_device *pdev)
 	return devm_gpiochip_add_data(dev, &mpfs_gpio->gc, mpfs_gpio);
 }
 
+static const struct mpfs_gpio_reg_offsets mpfs_reg_offsets = {
+	.inp = MPFS_INP_REG,
+	.outp = MPFS_OUTP_REG,
+};
+
+static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = {
+	.inp = COREGPIO_INP_REG,
+	.outp = COREGPIO_OUTP_REG,
+};
+
 static const struct of_device_id mpfs_gpio_of_ids[] = {
-	{ .compatible = "microchip,mpfs-gpio", },
+	{
+		.compatible = "microchip,mpfs-gpio",
+		.data = &mpfs_reg_offsets,
+	}, {
+		.compatible = "microchip,coregpio-rtl-v3",
+		.data = &coregpio_reg_offsets,
+	},
 	{ /* end of list */ }
 };
 
-- 
2.45.2

Re: [PATCH v1 1/2] gpio: mpfs: add CoreGPIO support

[Bartosz Golaszewski]

On Thu, Nov 7, 2024 at 11:33 AM Conor Dooley <conor@kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley@microchip.com>
>
> coreGPIO, which the "hard" core in PolarFire SoC is based on, has
> different offsets for inp/outp. Add some match_data handling to account
> for the differences.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  drivers/gpio/gpio-mpfs.c | 38 +++++++++++++++++++++++++++++++++-----
>  1 file changed, 33 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpio/gpio-mpfs.c b/drivers/gpio/gpio-mpfs.c
> index 3718121eb97a..4aefae05a9fb 100644
> --- a/drivers/gpio/gpio-mpfs.c
> +++ b/drivers/gpio/gpio-mpfs.c
> @@ -10,6 +10,7 @@
>  #include <linux/errno.h>
>  #include <linux/gpio/driver.h>
>  #include <linux/init.h>
> +#include <linux/of_device.h>

You don't need this. Include property.h and use device_get_match_data() instead.

Bart

[PATCH v1 2/2] MAINTAINERS: add gpio driver to PolarFire entry

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Lewis' original GPIO driver patchset didn't add MAINTAINERS coverage of
the driver and I forgot to add it to the existing entry. Make up for the
minimal amount of lost time.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1d6aca7ffc0a..e73a0b848bf2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19837,6 +19837,7 @@ F:	arch/riscv/boot/dts/microchip/
 F:	drivers/char/hw_random/mpfs-rng.c
 F:	drivers/clk/microchip/clk-mpfs*.c
 F:	drivers/firmware/microchip/mpfs-auto-update.c
+F:	drivers/gpio/gpio-mpfs.c
 F:	drivers/i2c/busses/i2c-microchip-corei2c.c
 F:	drivers/mailbox/mailbox-mpfs.c
 F:	drivers/pci/controller/plda/pcie-microchip-host.c
-- 
2.45.2

Re: (subset) [PATCH v1 0/2] polarfire gpio driver follow-ups

[Bartosz Golaszewski]

From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>


On Thu, 07 Nov 2024 10:33:39 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Yo,
> 
> I realised last week, while rebasing the interrupt portion of the
> driver, that coregpio a compatible in the kernel as well as a dts user.
> Given how long the driver has taken to even get partially accepted, I
> waited to get it to gpio/for-next rather than showing up with last
> minute additions to it.
> 
> [...]

Applied, thanks!

I must admit I like your b4 topic names. :)

[2/2] MAINTAINERS: add gpio driver to PolarFire entry
      commit: 10287f0f9ee91f75a60ec1b19d962f459b18f589

Best regards,
-- 
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>

Re: (subset) [PATCH v1 0/2] polarfire gpio driver follow-ups

[Conor Dooley]

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On Sun, Nov 10, 2024 at 08:10:31PM +0100, Bartosz Golaszewski wrote:
 
> I must admit I like your b4 topic names. :)

Heh, no credit to me - they're not b4 topic names. The branch was
actually called "gpio-noirq-core". It's a sendemail-validate hook in
git that generates it using diceware that came out of a conversation
between Brauner/Greg/Konstantin. Beats the usual send-email message-ids
given it is more human readable.

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