From: Yu-Chun Lin <eleanor.lin@realtek.com>
To: <linusw@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <afaerber@suse.com>
Cc: <bartosz.golaszewski@oss.qualcomm.com>, <james.tai@realtek.com>,
<cy.huang@realtek.com>, <stanley_chang@realtek.com>,
<eleanor.lin@realtek.com>, <tychang@realtek.com>,
<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-realtek-soc@lists.infradead.org>
Subject: [PATCH v3 5/7] pinctrl: realtek: add support for slew rate, input voltage and high VIL
Date: Thu, 12 Mar 2026 19:30:38 +0800 [thread overview]
Message-ID: <20260312113040.68189-6-eleanor.lin@realtek.com> (raw)
In-Reply-To: <20260312113040.68189-1-eleanor.lin@realtek.com>
From: Tzuyi Chang <tychang@realtek.com>
Add support for configuring slew rate, input voltage level and high VIL
mode. This involves updating the pin configuration parsing logic to handle
PIN_CONFIG_SLEW_RATE, PIN_CONFIG_INPUT_VOLTAGE_UV and the new custom
property "realtek,high-vil-microvolt".
Signed-off-by: Tzuyi Chang <tychang@realtek.com>
Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
Changes in v3:
- Changed default value of realtek,high-vil-microvolt from 1 to 0.
- Synced with binding changes to handle PIN_CONFIG_SLEW_RATE as valid numbers.
---
drivers/pinctrl/realtek/pinctrl-rtd.c | 66 ++++++++++++++++++++++++++-
drivers/pinctrl/realtek/pinctrl-rtd.h | 3 ++
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
index 60dfb39bc986..c5e44e29bab1 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd.c
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -37,11 +37,13 @@ struct rtd_pinctrl {
#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1)
#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2)
#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3)
+#define RTD_HIGH_VIL (PIN_CONFIG_END + 4)
static const struct pinconf_generic_params rtd_custom_bindings[] = {
{"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0},
{"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0},
{"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},
+ {"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0},
};
static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
@@ -288,7 +290,8 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
u16 strength;
u32 val;
u32 mask;
- u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off;
+ u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off,
+ input_volt_off, sr_off, hvil_off;
const char *name = data->info->pins[pinnr].name;
int ret = 0;
@@ -409,6 +412,67 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
val = set_val ? mask : 0;
break;
+ case PIN_CONFIG_SLEW_RATE:
+ if (config_desc->slew_rate_offset == NA) {
+ dev_err(data->dev, "Slew rate setting unsupported for pin: %s\n", name);
+ return -ENOTSUPP;
+ }
+
+ switch (arg) {
+ case 1:
+ set_val = 0;
+ break;
+ case 10:
+ set_val = 1;
+ break;
+ case 20:
+ set_val = 2;
+ break;
+ case 30:
+ set_val = 3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ sr_off = config_desc->base_bit + config_desc->slew_rate_offset;
+ reg_off = config_desc->reg_offset;
+ mask = 0x3 << sr_off;
+ val = arg << sr_off;
+ break;
+
+ case PIN_CONFIG_INPUT_VOLTAGE_UV:
+ if (config_desc->input_volt_offset == NA) {
+ dev_err(data->dev, "Input voltage level setting unsupported for pin:%s\n",
+ name);
+ return -ENOTSUPP;
+ }
+
+ if (arg == 3300000)
+ set_val = 1;
+ else if (arg == 1800000)
+ set_val = 0;
+ else
+ return -EINVAL;
+
+ input_volt_off = config_desc->base_bit + config_desc->input_volt_offset;
+ reg_off = config_desc->reg_offset;
+
+ mask = BIT(input_volt_off);
+ val = set_val ? BIT(input_volt_off) : 0;
+ break;
+
+ case RTD_HIGH_VIL:
+ if (config_desc->hvil_offset == NA) {
+ dev_err(data->dev, "High vil setting unsupported for pin:%s\n", name);
+ return -ENOTSUPP;
+ }
+ hvil_off = config_desc->base_bit + config_desc->hvil_offset;
+ reg_off = config_desc->reg_offset;
+ mask = BIT(hvil_off);
+ val = 1;
+ break;
+
case RTD_DRIVE_STRENGH_P:
sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
if (!sconfig_desc) {
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h
index 7fb0955ce749..02e2d8d269b5 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd.h
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.h
@@ -34,6 +34,9 @@ struct rtd_pin_config_desc {
unsigned int smt_offset;
unsigned int power_offset;
unsigned int curr_type;
+ unsigned int input_volt_offset;
+ unsigned int slew_rate_offset;
+ unsigned int hvil_offset;
};
struct rtd_pin_sconfig_desc {
--
2.34.1
next prev parent reply other threads:[~2026-03-12 11:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-12 11:30 [PATCH v3 0/7] pinctrl: realtek: Core improvements and RTD1625 support Yu-Chun Lin
2026-03-12 11:30 ` [PATCH v3 1/7] dt-bindings: pincfg-node: Add input-voltage-microvolt property Yu-Chun Lin
2026-03-12 17:42 ` Conor Dooley
2026-03-12 17:44 ` Conor Dooley
2026-03-16 9:02 ` Yu-Chun Lin [林祐君]
2026-03-12 11:30 ` [PATCH v3 2/7] pinctrl: pinconf-generic: Add properties 'input-voltage-microvolt' Yu-Chun Lin
2026-03-16 13:48 ` Linus Walleij
2026-03-12 11:30 ` [PATCH v3 3/7] dt-bindings: pinctrl: realtek: Improve 'realtek,duty-cycle' description Yu-Chun Lin
2026-03-12 17:42 ` Conor Dooley
2026-03-16 13:47 ` Linus Walleij
2026-03-12 11:30 ` [PATCH v3 4/7] dt-bindings: pinctrl: realtek: Add RTD1625 pinctrl binding Yu-Chun Lin
2026-03-12 17:46 ` Conor Dooley
2026-03-16 13:48 ` Linus Walleij
2026-03-12 11:30 ` Yu-Chun Lin [this message]
2026-03-16 13:49 ` [PATCH v3 5/7] pinctrl: realtek: add support for slew rate, input voltage and high VIL Linus Walleij
2026-03-12 11:30 ` [PATCH v3 2/3] pinctrl: realtek: add rtd1625 pinctrl driver Yu-Chun Lin
2026-03-12 11:30 ` [PATCH v3 3/3] arm64: dts: realtek: Add pinctrl support for RTD1625 Yu-Chun Lin
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