* [PATCH] pinctrl-amd: Don't clear S4 wake bits at probe
@ 2026-07-20 16:28 Mario Limonciello
2026-07-25 9:32 ` Linus Walleij
0 siblings, 1 reply; 2+ messages in thread
From: Mario Limonciello @ 2026-07-20 16:28 UTC (permalink / raw)
To: Basavaraj.Natikar, Shyam-sundar.S-k, linusw, mario.limonciello; +Cc: linux-gpio
commit 6bc3462a0f5e ("pinctrl: amd: Mask wake bits on probe again")
introduced a regression where Wake-on-LAN no longer works after suspend
or shutdown on some AMD platforms.
Firmware-programmed S4 wake bits for devices like PCIe NICs using PCI
PME are cleared at probe, but nothing restores them. Unlike S0i3/S3 wake
sources that use enable_irq_wake() -> amd_gpio_irq_set_wake(), PCIe PME
does not use GPIO IRQ infrastructure and relies on firmware configuration.
The original intent of commit 6bc3462a0f5e ("pinctrl: amd: Mask wake
bits on probe again") was to clear spurious wake bits left by firmware
to prevent unwanted wakeups. However, S4 wake bits are used for
hardware-level wake sources like WoL that bypass the kernel's IRQ wake
API.
Fix by preserving S4 wake bits at probe and only clearing S0i3/S3 bits:
- Firmware-configured S4 wake sources (WoL) continue working
- Kernel maintains control of S3/S0i3 wake policy via set_wake()
- S3-only wake sources work correctly per commit f31f33dbb3ba ("pinctrl:
amd: Take suspend type into consideration which pins are non-wake")
The trade-off is that firmware-programmed spurious S4 wake bits remain
set, but this is less problematic than breaking WoL.
Fixes: 6bc3462a0f5e ("pinctrl: amd: Mask wake bits on probe again")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
drivers/pinctrl/pinctrl-amd.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index e3128b0045d22..15a398bb3be23 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -884,8 +884,7 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
u32 pin_reg, mask;
int i;
- mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
- BIT(WAKE_CNTRL_OFF_S4);
+ mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number;
--
2.43.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] pinctrl-amd: Don't clear S4 wake bits at probe
2026-07-20 16:28 [PATCH] pinctrl-amd: Don't clear S4 wake bits at probe Mario Limonciello
@ 2026-07-25 9:32 ` Linus Walleij
0 siblings, 0 replies; 2+ messages in thread
From: Linus Walleij @ 2026-07-25 9:32 UTC (permalink / raw)
To: Mario Limonciello; +Cc: Basavaraj.Natikar, Shyam-sundar.S-k, linux-gpio
On Mon, Jul 20, 2026 at 6:29 PM Mario Limonciello
<mario.limonciello@amd.com> wrote:
> commit 6bc3462a0f5e ("pinctrl: amd: Mask wake bits on probe again")
> introduced a regression where Wake-on-LAN no longer works after suspend
> or shutdown on some AMD platforms.
>
> Firmware-programmed S4 wake bits for devices like PCIe NICs using PCI
> PME are cleared at probe, but nothing restores them. Unlike S0i3/S3 wake
> sources that use enable_irq_wake() -> amd_gpio_irq_set_wake(), PCIe PME
> does not use GPIO IRQ infrastructure and relies on firmware configuration.
>
> The original intent of commit 6bc3462a0f5e ("pinctrl: amd: Mask wake
> bits on probe again") was to clear spurious wake bits left by firmware
> to prevent unwanted wakeups. However, S4 wake bits are used for
> hardware-level wake sources like WoL that bypass the kernel's IRQ wake
> API.
>
> Fix by preserving S4 wake bits at probe and only clearing S0i3/S3 bits:
> - Firmware-configured S4 wake sources (WoL) continue working
> - Kernel maintains control of S3/S0i3 wake policy via set_wake()
> - S3-only wake sources work correctly per commit f31f33dbb3ba ("pinctrl:
> amd: Take suspend type into consideration which pins are non-wake")
>
> The trade-off is that firmware-programmed spurious S4 wake bits remain
> set, but this is less problematic than breaking WoL.
>
> Fixes: 6bc3462a0f5e ("pinctrl: amd: Mask wake bits on probe again")
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Patch applied for fixes, thanks for always fixing these
issues Mario!
Yours,
Linus Walleij
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